MCP454X/456X/464X/466X 7/8-Bit Single/Dual I2C Digital POT with Nonvolatile Memory Features Description • Single or Dual Resistor Network Options • Potentiometer or Rheostat Configuration Options • Resistor Network Resolution - 7-bit: 128 Resistors (129 Steps) - 8-bit: 256 Resistors (257 Steps) • RAB Resistances Options of: - 5 k - 10 k - 50 k - 100 k • Zero-Scale to Full-Scale Wiper Operation • Low Wiper Resistance: 75 (typical) • Low Tempco: - Absolute (Rheostat): 50 ppm typical (0°C to 70°C) - Ratiometric (Potentiometer): 15 ppm typical • Nonvolatile Memory - Automatic Recall of Saved Wiper Setting - WiperLock™ Technology - 10 General Purpose Memory Locations • I2C Serial Interface - 100 kHz, 400 kHz and 3.4 MHz Support • Serial Protocol Allows: - High-Speed Read/Write to Wiper - Read/Write to EEPROM - Write Protect to be Enabled/Disabled - WiperLock to be Enabled/Disabled • Resistor Network Terminal Disconnect Feature via the Terminal Control (TCON) Register • Write Protect Feature: - Hardware Write Protect (WP) Control Pin - Software Write Protect (WP) Configuration Bit • Brown-out Reset Protection (1.5V typical) • Serial Interface Inactive Current (2.5 uA typical) • High-Voltage Tolerant Digital Inputs: Up to 12.5V • Wide Operating Voltage: - 2.7V to 5.5V - Device Characteristics Specified - 1.8V to 5.5V - Device Operation • Wide Bandwidth (-3dB) Operation: - 2 MHz (typ.) for 5.0 k Device • Extended Temperature Range (-40°C to +125°C) The MCP45XX and MCP46XX devices offer a wide range of product offerings using an I2C interface. This family of devices support 7-bit and 8-bit resistor networks, nonvolatile memory configurations, and Potentiometer and Rheostat pinouts. WiperLock Technology allows application-specific calibration settings to be secured in the EEPROM. Package Types (top view) MCP45X1 Single Potentiometer HVC / A0 SCL SDA VSS 1 2 3 4 8 7 6 5 VDD P0B P0W P0A MCP45X2 Single Rheostat HVC / A0 SCL SDA VSS 1 2 3 4 MSOP HVC / A0 1 SCL 2 SDA 3 VSS 4 VDD A1 P0B P0W MSOP 8 VDD HVC / A0 1 SCL 2 7 P0B SDA P0W 6 3 VSS 4 5 P0A EP 9 8 7 6 5 DFN 3x3 (MF) * 8 VDD EP 9 7 A1 6 P0B 5 P0W DFN 3x3 (MF) * HVC/A0 SCL SDA VSS P1B P1W P1A 1 2 3 4 5 6 7 14 13 12 11 10 9 8 TSSOP VDD A1 A2 WP P0B P0W P0A HVC/A0 VDD A1 A2 MCP46X1 Dual Potentiometers 16 15 14 13 SCL SDA VSS VSS 1 2 3 4 EP 17 12 WP 11 NC 10 P0B 9 P0W P1B P1W P1A P0A 5 6 7 8 QFN-16 4x4 (ML) * MCP46X2 Dual Rheostat HVC/A0 SCL SDA VSS P1B 1 2 3 4 5 10 VDD HVC / A0 1 9 A1 SCL 2 8 P0B SDA 3 7 P0W V 4 SS P1W 6 P1B 5 MSOP 10 VDD EP 11 9 A1 8 P0B 7 P0W 6 P1W DFN 3x3 (MF) * * Includes Exposed Thermal Pad (EP); see Table 3-1. 2008-2013 Microchip Technology Inc. DS22107B-page 1 MCP454X/456X/464X/466X Device Block Diagram VDD VSS A2 A1 HVC/A0 SCL SDA 2 I C Interface Power-up/ Brown-out Control Resistor Network 0 (Pot 0) I2C Serial Interface Module & Control Logic (WiperLock™ Technology) Wiper 0 & TCON Register P0A P0W P0B P1A Resistor Network 1 (Pot 1) WP Memory (16x9) Wiper0 (V & NV) Wiper1 (V & NV) TCON STATUS Data EEPROM (10 x 9-bits) P1W Wiper 1 & TCON Register P1B For Dual Resistor Network Devices Only I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V MCP4532 (3) 1 I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V I2C Wiper Configuration Rheostat (1) Resistance (typical) RAB Options (k) Wiper - RW () # of Steps WiperLock Technology 1 Potentiometer (1) Device POR Wiper Setting Memory Type MCP4531 (3) # of POTs Control Interface Device Features VDD Operating Range (2) MCP4541 1 Potentiometer EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4542 1 Rheostat I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4551 (3) 1 Potentiometer (1) I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4552 (3) 1 Rheostat I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V 2 (1) MCP4561 1 Potentiometer I C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V MCP4562 1 Rheostat I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V MCP4631 (3) 2 Potentiometer (1) I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V MCP4632 (3) 2 Rheostat I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V MCP4641 2 Potentiometer (1) I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4642 2 Rheostat I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V 2 I C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V MCP4651 (3) MCP4652 (3) 2 Potentiometer 2 Rheostat MCP4661 2 Potentiometer MCP4662 2 Note 1: 2: 3: (1) Rheostat (1) Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor). Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted. Please check Microchip web site for device release and availability DS22107B-page 2 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings† Voltage on VDD with respect to VSS ........................................................................................................... -0.6V to +7.0V Voltage on HVC/A0, A1, A2, SCL, SDA and WP with respect to VSS ....................................................... -0.6V to 12.5V Voltage on all other pins (PxA, PxW, and PxB) with respect to VSS ..................................................-0.3V to VDD + 0.3V Input clamp current, IIK (VI < 0, VI > VDD, VI > VPP ON HV pins)........................................................................... ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .................................................................................................. ±20 mA Maximum output current sunk by any Output pin....................................................................................................25 mA Maximum output current sourced by any Output pin .............................................................................................25 mA Maximum current out of VSS pin ...........................................................................................................................100 mA Maximum current into VDD pin ..............................................................................................................................100 mA Maximum current into PXA, PXW & PXB pins ...................................................................................................... ±2.5 mA Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C Package power dissipation (TA = +50°C, TJ = +150°C) MSSOP-8 .......................................................................................................................................................473 mW MSSOP-10 .....................................................................................................................................................495 mW DFN-8 (3x3) ......................................................................................................................................................1.76W DFN-10 (3x3) ....................................................................................................................................................1.87W TSSOP-14.........................................................................................................................................................1.00W QFN-16 (4x4) ....................................................................................................................................................2.18W Soldering temperature of leads (10 seconds) ....................................................................................................... +300°C ESD protection on all pins 4 kV (HBM), 300V (MM) Maximum Junction Temperature (TJ) ................................................................................................................... +150°C † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2008-2013 Microchip Technology Inc. DS22107B-page 3 MCP454X/456X/464X/466X AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) DC Characteristics Parameters Supply Voltage HVC pin voltage range All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Sym Min Typ Max Units VDD 2.7 — 5.5 V 1.8 — 2.7 V VSS — 12.5V V VSS — VDD + 8.0V V 1.65 V VHV — Serial Interface only. VDD The HVC pin will be at one 4.5V of three input levels V < (VIL, VIH or VIHH). (Note 6) DD 4.5V VDD Start Voltage to ensure Wiper Reset VBOR VDD Rise Rate to ensure Power-on Reset VDDRR Delay after device exits the reset state (VDD > VBOR) TBORD — 10 20 µs IDD — — 600 µA Serial Interface Active, HVC/A0 = VIH (or VIL) (Note 11) Write all 0’s to Volatile Wiper 0 VDD = 5.5V, FSCL = 3.4 MHz — — 250 µA Serial Interface Active, HVC/A0 = VIH (or VIL) (Note 11) Write all 0’s to Volatile Wiper 0 VDD = 5.5V, FSCL = 100 kHz — — 575 µA EE Write Current (Write Cycle) (Nonvolatile device only), VDD = 5.5V, FSCL = 400 kHz, Write all 0’s to Nonvolatile Wiper 0 SCL = VIL or VIH — 2.5 5 µA Serial Interface Inactive, (Stop condition, SCL = SDA = VIH), Wiper = 0 VDD = 5.5V, HVC/A0 = VIH Supply Current (Note 10) — Conditions (Note 9) RAM retention voltage (VRAM) < VBOR V/ms Note 1: 2: 3: 4: 5: 6: 7: Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. DS22107B-page 4 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) DC Characteristics Parameters Resistance (± 20%) Resolution Step Resistance Nominal Resistance Match Wiper Resistance (Note 3, Note 4) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Sym RAB Min Typ Max Units Conditions 4.0 5 6.0 k -502 devices(Note 1) 8.0 10 12.0 k -103 devices(Note 1) 40.0 50 60.0 k -503 devices(Note 1) 80.0 100 120.0 k -104 devices(Note 1) N 257 Taps 8-bit No Missing Codes 129 Taps 7-bit No Missing Codes — RAB / (256) — 8-bit Note 6 — RAB / (128) — 7-bit Note 6 |RAB0 - RAB1| / RAB — 0.2 1.25 % MCP46X1 devices only |RBW0 - RBW1| / RBW — 0.25 1.5 % MCP46X2 devices only, Code = Full-Scale RW — 75 160 VDD = 5.5 V, IW = 2.0 mA, code = 00h — 75 300 VDD = 2.7 V, IW = 2.0 mA, code = 00h — 50 — ppm/°C TA = -20°C to +70°C — 100 — ppm/°C TA = -40°C to +85°C — 150 — ppm/°C TA = -40°C to +125°C ppm/°C Code = Mid-scale (80h or 40h) RS Nominal Resistance Tempco RAB/T Ratiometeric Tempco VWB/T — 15 — Resistor Terminal Input Voltage Range (Terminals A, B and W) VA,VW,VB Vss — VDD V Note 5, Note 6 Note 1: 2: 3: 4: 5: 6: 7: Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. 2008-2013 Microchip Technology Inc. DS22107B-page 5 MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) DC Characteristics Parameters Maximum current through Terminal (A, W or B) Note 6 Leakage current into A, W or B All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Sym Min Typ Max Units IT — — 2.5 mA Terminal A IAW, W = Full-Scale (FS) — — 2.5 mA Terminal B IBW, W = Zero Scale (ZS) — — 2.5 mA Terminal W IAW or IBW, W = FS or ZS — — 1.38 mA IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 4000 — — 0.688 mA IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 8000 IWL Conditions Terminal A and Terminal B — — 0.138 mA — — 0.069 mA — 100 — nA MCP4XX1 PxA = PxW = PxB = VSS — 100 — nA MCP4XX2 PxB = PxW = VSS — 100 — nA Terminals Disconnected (R1HW = R0HW = 0) IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 40000 IAB, VB = 0V, VA = 5.5V, RAB(MIN) = 80000 Note 1: 2: 3: 4: 5: 6: 7: Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. DS22107B-page 6 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Parameters Sym Min Typ Max Units Full-Scale Error (MCP4XX1 only) (8-bit code = 100h, 7-bit code = 80h) VWFSE -6.0 -0.1 — LSb -4.0 -0.1 — LSb -3.5 -0.1 — LSb -2.0 -0.1 — LSb -0.8 -0.1 — LSb -0.5 -0.1 — LSb -0.5 -0.1 — -0.5 -0.1 — — +0.1 +6.0 LSb — +0.1 +3.0 LSb — +0.1 +3.5 LSb Zero-Scale Error (MCP4XX1 only) (8-bit code = 00h, 7-bit code = 00h) VWZSE Potentiometer Integral Non-linearity INL Potentiometer Differential Non-linearity DNL Conditions 8-bit 3.0V VDD 5.5V 7-bit 3.0V VDD 5.5V 8-bit 3.0V VDD 5.5V 7-bit 3.0V VDD 5.5V 8-bit 3.0V VDD 5.5V 7-bit 3.0V VDD 5.5V LSb 100 k 8-bit 3.0V VDD 5.5V LSb 7-bit 3.0V VDD 5.5V 5 k 8-bit 3.0V VDD 5.5V 7-bit 3.0V VDD 5.5V 10 k 8-bit 3.0V VDD 5.5V — +0.1 +2.0 LSb — +0.1 +0.8 LSb 5 k 10 k 50 k 50 k 7-bit 3.0V VDD 5.5V 8-bit 3.0V VDD 5.5V — +0.1 +0.5 LSb 7-bit 3.0V VDD 5.5V — +0.1 +0.5 LSb 100 k 8-bit 3.0V VDD 5.5V — +0.1 +0.5 LSb 7-bit 3.0V VDD 5.5V -1 ±0.5 +1 LSb 8-bit -0.5 ±0.25 +0.5 LSb 7-bit -0.5 ±0.25 +0.5 LSb 8-bit -0.25 ±0.125 +0.25 LSb 7-bit 3.0V VDD 5.5V MCP4XX1 devices only (Note 2) 3.0V VDD 5.5V MCP4XX1 devices only (Note 2) Note 1: 2: 3: 4: 5: 6: 7: Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. 2008-2013 Microchip Technology Inc. DS22107B-page 7 MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) DC Characteristics Parameters Bandwidth -3 dB (See Figure 2-58, load = 30 pF) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Sym Min Typ Max Units Conditions BW — 2 — MHz — 2 — MHz — 1 — MHz — 1 — MHz — 200 — kHz 8-bit Code = 80h — 200 — kHz 7-bit Code = 40h — 100 — kHz 100 k 8-bit Code = 80h — 100 — kHz 7-bit Code = 40h 5 k 10 k 50 k 8-bit Code = 80h 7-bit Code = 40h 8-bit Code = 80h 7-bit Code = 40h Note 1: 2: 3: 4: 5: 6: 7: Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. DS22107B-page 8 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Parameters Sym Rheostat Integral Non-linearity MCP45X1 (Note 4, Note 8) MCP4XX2 devices only (Note 4) R-INL Min Typ Max Units -1.5 ±0.5 +1.5 LSb -8.25 +4.5 +8.25 LSb -1.125 ±0.5 +1.125 LSb -6.0 +4.5 +6.0 LSb -1.5 ±0.5 +1.5 LSb -5.5 +2.5 +5.5 LSb -1.125 ±0.5 +1.125 LSb -4.0 +2.5 +4.0 LSb -1.5 ±0.5 +1.5 LSb -2.0 +1 +2.0 LSb -1.125 ±0.5 +1.125 LSb -1.5 +1 +1.5 LSb -1.0 ±0.5 +1.0 LSb -1.5 +0.25 +1.5 LSb -0.8 ±0.5 +0.8 LSb -1.125 +0.25 +1.125 LSb Conditions 5 k 8-bit 5.5V, IW = 900 µA 3.0V, IW = 480 µA (Note 7) 7-bit 5.5V, IW = 900 µA 3.0V, IW = 480 µA (Note 7) 10 k 8-bit 5.5V, IW = 450 µA 3.0V, IW = 240 µA (Note 7) 7-bit 5.5V, IW = 450 µA 3.0V, IW = 240 µA (Note 7) 50 k 8-bit 5.5V, IW = 90 µA 3.0V, IW = 48 µA (Note 7) 7-bit 5.5V, IW = 90 µA 3.0V, IW = 48 µA (Note 7) 100 k 8-bit 5.5V, IW = 45 µA 3.0V, IW = 24 µA (Note 7) 7-bit 5.5V, IW = 45 µA 3.0V, IW = 24 µA (Note 7) Note 1: 2: 3: 4: 5: 6: 7: Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. 2008-2013 Microchip Technology Inc. DS22107B-page 9 MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Parameters Sym Rheostat Differential Non-linearity MCP45X1 (Note 4, Note 8) MCP4XX2 devices only (Note 4) R-DNL Min Typ Max Units -0.5 ±0.25 +0.5 LSb -1.0 +0.5 +1.0 LSb -0.375 ±0.25 +0.375 LSb -0.75 +0.5 +0.75 LSb -0.5 ±0.25 +0.5 LSb -1.0 +0.25 +1.0 LSb -0.375 ±0.25 +0.375 LSb -0.75 +0.5 +0.75 LSb -0.5 ±0.25 +0.5 LSb -0.5 ±0.25 +0.5 LSb -0.375 ±0.25 +0.375 LSb -0.375 ±0.25 +0.375 LSb -0.5 ±0.25 +0.5 LSb -0.5 ±0.25 +0.5 LSb -0.375 ±0.25 +0.375 LSb -0.375 ±0.25 +0.375 LSb Conditions 5 k 8-bit 5.5V, IW = 900 µA 3.0V, IW = 480 µA (Note 7) 7-bit 5.5V, IW = 900 µA 3.0V, IW = 480 µA (Note 7) 10 k 8-bit 5.5V, IW = 450 µA 3.0V, IW = 240 µA (Note 7) 7-bit 5.5V, IW = 450 µA 3.0V, IW = 240 µA (Note 7) 50 k 8-bit 5.5V, IW = 90 µA 3.0V, IW = 48 µA (Note 7) 7-bit 5.5V, IW = 90 µA 3.0V, IW = 48 µA (Note 7) 100 k 8-bit 5.5V, IW = 45 µA 3.0V, IW = 24 µA (Note 7) 7-bit 5.5V, IW = 45 µA 3.0V, IW = 24 µA (Note 7) Capacitance (PA) CAW — 75 — pF f =1 MHz, Code = Full-Scale Capacitance (Pw) CW — 120 — pF f =1 MHz, Code = Full-Scale Capacitance (PB) CBW — 75 — pF f =1 MHz, Code = Full-Scale Note 1: 2: 3: 4: 5: 6: 7: Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. DS22107B-page 10 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) DC Characteristics Parameters All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Sym Min Typ Max Units Conditions Digital Inputs/Outputs (SDA, SCK, HVC/A0, A1, A2, WP) Schmitt Trigger High-Input Threshold Schmitt Trigger Low-Input Threshold Hysteresis of Schmitt Trigger Inputs (Note 6) VIH VIL VHYS 0.45 VDD — — V 0.5 VDD — — V 0.7 VDD — VMAX V 0.7 VDD — VMAX V 0.7 VDD — VMAX V 0.7 VDD — VMAX V — — 0.2VDD V -0.5 — 0.3VDD V -0.5 — 0.3VDD V -0.5 — 0.3VDD V -0.5 — 0.3VDD V — 0.1VDD — V N.A. — — V N.A. — — V 0.1 VDD — — V 0.05 VDD — — V 0.1 VDD — — V 0.1 VDD — — V High-Voltage Input Entry Voltage VIHHEN 8.5 — 12.5 (6) V High-Voltage Input Exit Voltage VIHHEX — — VDD + 0.8V (6) V High-Voltage Limit VMAX — — 12.5 (6) V All Inputs except SDA and SCL 2.7V VDD 5.5V (Allows 2.7V Digital VDD with 5V Analog VDD) 1.8V VDD 2.7V 100 kHz SDA and SCL 400 kHz 1.7 MHz 3.4 Mhz All inputs except SDA and SCL 100 kHz SDA and SCL 400 kHz 1.7 MHz 3.4 Mhz All inputs except SDA and SCL 100 kHz SDA and SCL 400 kHz VDD < 2.0V VDD 2.0V VDD < 2.0V VDD 2.0V 1.7 MHz 3.4 Mhz Threshold for WiperLock™ Technology Pin can tolerate VMAX or less. Note 1: 2: 3: 4: 5: 6: 7: Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. 2008-2013 Microchip Technology Inc. DS22107B-page 11 MCP454X/456X/464X/466X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) DC Characteristics Parameters All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Sym Output Low Voltage (SDA) VOL Weak Pull-up / Pull-down Current IPU HVC Pull-up / Pull-down Resistance Input Leakage Current Pin Capacitance Min Typ Max Units Conditions VSS — 0.2VDD V VDD < 2.0V, IOL = 1 mA VSS — 0.4 V VDD 2.0V, IOL = 3 mA — — 1.75 mA Internal VDD pull-up, VIHH pull-down VDD = 5.5V, VIHH = 12.5V — 170 — µA HVC pin, VDD = 5.5V, VHVC = 3V RHVC — 16 — k VDD = 5.5V, VHVC = 3V IIL -1 — 1 µA VIN = VDD and VIN = VSS CIN, COUT — 10 — pF fC = 3.4 MHz N 0h — 1FFh hex 8-bit device — 1FFh hex 7-bit device hex All Terminals connected RAM (Wiper) Value Value Range 0h TCON POR/BOR Value 1FFh NTCON EEPROM Endurance Endurance — EEPROM Range N 0h Initial Factory Setting N EEPROM Programming Write Cycle Time 1M — — 1FFh 80h 40h Cycles hex hex 8-bit WiperLock Technology = Off hex 7-bit WiperLock Technology = Off tWC — 5 10 ms PSS — 0.0015 0.0035 %/% 8-bit VDD = 2.7V to 5.5V, VA = 2.7V, Code = 80h — 0.0015 0.0035 %/% 7-bit VDD = 2.7V to 5.5V, VA = 2.7V, Code = 40h Power Requirements Power Supply Sensitivity (MCP45X2 and MCP46X2 only) Note 1: 2: 3: 4: 5: 6: 7: Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP4XX1 only. MCP4XX2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and temperature. 8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. DS22107B-page 12 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X SCL 93 91 90 92 SDA STOP Condition START Condition I2C Bus Start/Stop Bits Timing Waveforms. FIGURE 1-1: I2C BUS START/STOP BITS REQUIREMENTS TABLE 1-1: I2C AC Characteristics Param. Symbol No. Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C TA +125C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Characteristic FSCL D102 Cb Bus capacitive loading 90 TSU:STA START condition Setup time 91 THD:STA START condition Hold time 92 TSU:STO STOP condition Setup time 93 THD:STO STOP condition Hold time 2008-2013 Microchip Technology Inc. Standard mode Fast mode High-Speed 1.7 High-Speed 3.4 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode Min Max Units 0 0 0 0 — — — — 4700 600 160 160 4000 600 160 160 4000 600 160 160 4000 600 160 160 100 400 1.7 3.4 400 400 400 100 — — — — — — — — — — — — — — — — kHz kHz MHz MHz pF pF pF pF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions Cb = 400 pF, 1.8V - 5.5V Cb = 400 pF, 2.7V - 5.5V Cb = 400 pF, 4.5V - 5.5V Cb = 100 pF, 4.5V - 5.5V Only relevant for repeated START condition After this period the first clock pulse is generated DS22107B-page 13 MCP454X/456X/464X/466X 103 102 100 101 SCL 90 106 91 92 107 SDA In 110 109 109 SDA Out I2C Bus Data Timing. FIGURE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE) TABLE 1-2: I2C AC Characteristics Param. No. Sym Characteristic 100 THIGH Clock high time 101 Note 1: 2: 3: 4: 5: 6: 7: TLOW Clock low time Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C TA +125C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Min Max Units 100 kHz mode 4000 — ns 1.8V-5.5V 400 kHz mode 600 — ns 2.7V-5.5V 1.7 MHz mode 120 ns 4.5V-5.5V 3.4 MHz mode 60 — ns 4.5V-5.5V 100 kHz mode 4700 — ns 1.8V-5.5V 400 kHz mode 1300 — ns 2.7V-5.5V ns 4.5V-5.5V — ns 4.5V-5.5V 1.7 MHz mode 320 3.4 MHz mode 160 Conditions As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not tested. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. Ensured by the TAA 3.4 MHz specification test. DS22107B-page 14 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X TABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) I2C AC Characteristics Param. No. Sym 102A (5) TRSCL 102B (5) 103A 103B (5) (5) 106 Note 1: 2: 3: 4: 5: 6: 7: TRSDA TFSCL TFSDA THD:DAT Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C TA +125C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Characteristic SCL rise time SDA rise time SCL fall time SDA fall time Data input hold time Min Max Units Conditions 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF (100 pF maximum for 3.4 MHz mode) 1.7 MHz mode 20 80 ns 1.7 MHz mode 20 160 ns 3.4 MHz mode 10 40 ns 3.4 MHz mode 10 80 ns After a Repeated Start condition or an Acknowledge bit 100 kHz mode — 1000 ns Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode) 400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 160 ns 3.4 MHz mode 10 80 ns 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 80 ns 3.4 MHz mode 10 40 ns 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb (4) 300 ns 1.7 MHz mode 20 160 ns 3.4 MHz mode 10 80 ns After a Repeated Start condition or an Acknowledge bit Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode) Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode) 100 kHz mode 0 — ns 1.8V-5.5V, Note 6 400 kHz mode 0 — ns 2.7V-5.5V, Note 6 1.7 MHz mode 0 — ns 4.5V-5.5V, Note 6 3.4 MHz mode 0 — ns 4.5V-5.5V, Note 6 As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not tested. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. Ensured by the TAA 3.4 MHz specification test. 2008-2013 Microchip Technology Inc. DS22107B-page 15 MCP454X/456X/464X/466X I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) TABLE 1-2: I2C AC Characteristics Param. No. 107 109 110 Sym 2: 3: 4: 5: 6: 7: Characteristic TSU:DAT Data input setup time TAA TBUF TSP Note 1: Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C TA +125C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Output valid from clock Bus free time Input filter spike suppression (SDA and SCL) Min Max Units Conditions 100 kHz mode 250 — ns 400 kHz mode 100 — ns 1.7 MHz mode 10 — ns 3.4 MHz mode 10 — ns 100 kHz mode — 3450 ns 400 kHz mode — 900 ns 1.7 MHz mode — 150 ns Cb = 100 pF, Note 1, Note 7 — 310 ns Cb = 400 pF, Note 1, Note 5 3.4 MHz mode — 150 ns Cb = 100 pF, Note 1 100 kHz mode 4700 — ns Time the bus must be free before a new transmission can start 400 kHz mode 1300 — ns 1.7 MHz mode N.A. — ns 3.4 MHz mode N.A. — ns 100 kHz mode — 50 ns 400 kHz mode — 50 ns Note 2 Note 1 Philips Spec states N.A. 1.7 MHz mode — 10 ns Spike suppression 3.4 MHz mode — 10 ns Spike suppression As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not tested. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. Ensured by the TAA 3.4 MHz specification test. DS22107B-page 16 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 8L-DFN (3x3) JA — 56.7 — °C/W Thermal Resistance, 8L-MSOP JA — 211 — °C/W Thermal Resistance, 8L-SOIC JA — 149.5 — °C/W Thermal Resistance, 10L-DFN (3x3) JA — 57 — °C/W Thermal Resistance, 10L-MSOP JA — 202 — °C/W Thermal Resistance, 14L-MSOP JA — N/A — °C/W Thermal Resistance, 14L-SOIC JA — 95.3 — °C/W Thermal Resistance, 16L-QFN JA — 47 — °C/W Conditions Temperature Ranges Thermal Package Resistances 2008-2013 Microchip Technology Inc. DS22107B-page 17 MCP454X/456X/464X/466X NOTES: DS22107B-page 18 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 450 1.7MHz, 5.5V 300 250 1.7MHz, 2.7V 200 400kHz, 5.5V 100kHz, 5.5V 150 100 400kHz, 2.7V 50 0 40 IHVC 150 100 50 100kHz, 2.7V RHVC 0 -40 80 0 120 2 3 4 5 Temperature (°C) FIGURE 2-1: Device Current (IDD) vs. I2C Frequency (fSCL) and Ambient Temperature (VDD = 2.7V and 5.5V). 6 7 VHVC (V) 8 9 10 FIGURE 2-4: HVC Pull-up/Pull-down Resistance (RHVC) and Current (IHVC) vs. HVC Input Voltage (VHVC) (VDD = 5.5V). 12 HVC VPP Threshold (V) 3 2.5 Istandby (uA) 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 200 3.4MHz, 2.7V 350 RHVC (kOhms) 400 IDD (uA) 250 3.4MHz, 5.5V IHVC (µA) Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 5.5V 2 1.5 1 2.7V 0.5 10 5.5V Entry 8 2.7V Entry 5.5V Exit 6 4 2.7V Exit 2 0 -40 0 40 80 120 Temperature (°C) FIGURE 2-2: Device Current (ISHDN) and VDD. (HVC = VDD) vs. Ambient Temperature. -40 -20 0 20 40 60 80 Ambient Temperature (°C) 100 120 FIGURE 2-5: HVC High Input Entry/Exit Threshold vs. Ambient Temperature and VDD. 420 IWRITE (µA) 400 380 360 5.5V 340 320 300 -40 0 40 80 120 Temperature (°C) FIGURE 2-3: Write Current (IWRITE) vs. Ambient Temperature. 2008-2013 Microchip Technology Inc. DS22107B-page 19 MCP454X/456X/464X/466X Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. INL DNL 0.3 0.2 0.1 80 0 60 -0.1 40 125°C 20 0 -40°C 25°C 85°C 120 100 -0.2 RW -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) 32 260 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL INL 220 DNL 180 0 140 RW 100 -0.1 125°C 60 -40°C 20 0 32 25°C 85°C -0.2 -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-7: 5 k Pot Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). DS22107B-page 20 0.75 -0.25 40 125°C 85°C 25°C 32 DNL -40°C -0.75 RW -1.25 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-8: 5 k Rheo Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 6 INL 220 0.1 1.25 60 260 0.2 125C Rw 125C INL 125C DNL 0.25 300 0.3 85C Rw 85C INL 85C DNL 80 0 Error (LSb) Wiper Resistance (R W) (ohms) -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL INL 20 FIGURE 2-6: 5 k Pot Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 300 -40C Rw -40C INL -40C DNL Error (LSb) 125C Rw 125C INL 125C DNL 4 180 2 140 RW 100 0 -40°C 60 125°C 20 0 32 85°C 25°C Error (LSb) 85C Rw 85C INL 85C DNL Wiper Resistance (R W ) (ohms) 100 25C Rw 25C INL 25C DNL Wiper Resistance (R W ) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (R W ) (ohms) 120 DNL -2 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-9: 5 k Rheo Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 5300 6000 5250 5000 RWB (Ohms) Nominal Resistance (RAB) (Ohms) Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 2.7V 5200 5150 5100 4000 3000 2000 -40°C 25°C 85°C 125°C 1000 5.5V 5050 0 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-10: 5 k – Nominal Resistance () vs. Ambient Temperature and VDD. 2008-2013 Microchip Technology Inc. 0 32 64 96 128 160 192 Wiper Setting (decimal) 224 256 FIGURE 2-11: 5 k – RWB () vs. Wiper Setting and Ambient Temperature. DS22107B-page 21 MCP454X/456X/464X/466X Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. FIGURE 2-12: 5 k – Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 µs/Div). FIGURE 2-15: 5 k – Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 µs/Div). FIGURE 2-13: 5 k – Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 µs/Div). FIGURE 2-16: 5 k – Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 µs/Div). FIGURE 2-14: 5 k – Power-Up Wiper Response Time (20 ms/Div). DS22107B-page 22 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 125C Rw 125C INL 125C DNL INL DNL 0.3 0.2 0.1 80 0 60 -0.1 25°C -40°C 125°C 85°C -0.2 RW 20 -0.3 0 260 220 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL INL DNL 125C Rw 125C INL 125C DNL 0.1 0 140 100 RW 60 25°C 125°C 85°C 20 0 0 60 40 125°C 32 -40°C 300 -0.1 -0.2 -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-18: 10 k Pot Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). 2008-2013 Microchip Technology Inc. 1 32 85°C 25°C RW -40°C DNL -0.5 -1 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-19: 10 k Rheo Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 0.3 180 125C Rw 125C INL 125C DNL 80 0 0.2 85C Rw 85C INL 85C DNL 0.5 20 Error (LSb) Wiper Resistance (R W) (ohms) -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL INL 25 50 75 100 125 150 175 200 225 250 Wiper Setting (decimal) FIGURE 2-17: 10 k Pot Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 300 -40C Rw -40C INL -40C DNL 100 Wiper Resistance (R W ) (ohms) 40 120 Error (LSb) 85C Rw 85C INL 85C DNL -40C Rw -40C INL -40C DNL 260 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 4 3 INL 220 2 180 1 140 0 100 -40°C 60 DNL RW Error (LSb) 100 25C Rw 25C INL 25C DNL Wiper Resistance (R W ) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (R W ) (ohms) 120 -1 125°C 85°C 25°C 20 -2 0 25 50 75 100 125 150 175 200 225 250 Wiper Setting (decimal) FIGURE 2-20: 10 k Rheo Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). DS22107B-page 23 MCP454X/456X/464X/466X Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 12000 10250 10000 10200 10150 10100 RWB (Ohms) Nominal Resistance (R AB) (Ohms) 10300 2.7V 10050 10000 5.5V 9950 1.8V 8000 6000 4000 -40°C 25°C 85°C 125°C 2000 9900 9850 0 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-21: 10 k – Nominal Resistance () vs. Ambient Temperature and VDD. DS22107B-page 24 0 32 64 96 128 160 192 Wiper Setting (decimal) 224 256 FIGURE 2-22: 10 k – RWB () vs. Wiper Setting and Ambient Temperature. 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. FIGURE 2-23: 10 k – Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 µs/Div). FIGURE 2-26: 10 k – Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 µs/Div). FIGURE 2-24: 10 k – Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 µs/Div). FIGURE 2-27: 10 k – Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 µs/Div). FIGURE 2-25: 10 k – Power-Up Wiper Response Time (1 µs/Div). 2008-2013 Microchip Technology Inc. DS22107B-page 25 MCP454X/456X/464X/466X Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. INL DNL 0.3 0.2 0.1 80 0 60 -0.1 40 125°C 25°C 85°C 20 0 -40°C 120 100 -0.2 RW -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) 32 260 220 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL INL DNL 125C Rw 125C INL 125C DNL 180 0 140 RW 100 -40°C 60 -0.1 -0.2 -0.1 40 0 32 -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-29: 50 k Pot Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). DS22107B-page 26 85°C 25°C 125°C 32 -40°C RW -0.2 -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-30: 50 k Rheo Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL INL 125C Rw 125C INL 125C DNL 1 0.75 0.5 DNL 0.25 180 0 140 RW 100 -0.25 -0.5 -40°C 60 125°C 85°C 25°C 20 0.1 0 220 0.1 0.2 60 260 0.2 0.3 125C Rw 125C INL 125C DNL DNL 300 0.3 85C Rw 85C INL 85C DNL 80 0 Error (LSb) Wiper Resistance (R W) (ohms) -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL INL 20 FIGURE 2-28: 50 k Pot Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 300 -40C Rw -40C INL -40C DNL Error (LSb) 125C Rw 125C INL 125C DNL Error (LSb) 85C Rw 85C INL 85C DNL Wiper Resistance (R W) (ohms) 100 25C Rw 25C INL 25C DNL Wiper Resistance (R W ) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (R W ) (ohms) 120 125°C 85°C 25°C 20 0 32 64 -0.75 -1 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-31: 50 k Rheo Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 60000 52000 50000 51500 1.8V RWB (Ohms) Nominal Resistance (R (Ohms) AB) 52500 51000 50500 50000 2.7V 40000 30000 20000 -40°C 25°C 85°C 125°C 10000 49500 5.5V 49000 0 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-32: 50 k – Nominal Resistance () vs. Ambient Temperature and VDD. 2008-2013 Microchip Technology Inc. 0 32 64 96 128 160 192 Wiper Setting (decimal) 224 256 FIGURE 2-33: 50 k – RWB () vs. Wiper Setting and Ambient Temperature. DS22107B-page 27 MCP454X/456X/464X/466X Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. FIGURE 2-34: 50 k – Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 µs/Div). FIGURE 2-37: 50 k – Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 µs/Div). FIGURE 2-35: 50 k – Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 µs/Div). FIGURE 2-38: 50 k – Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 µs/Div). FIGURE 2-36: 50 k – Power-Up Wiper Response Time (1 µs/Div). DS22107B-page 28 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 125C Rw 125C INL 125C DNL 0.2 DNL 0 60 -0.1 40 25°C -40°C -40C Rw -40C INL -40C DNL 100 0.1 INL 80 120 RW 32 -0.2 64 96 128 160 192 224 256 Wiper Setting (decimal) -40C Rw -40C INL -40C DNL 260 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL INL 220 DNL 125C Rw 125C INL 125C DNL -0.1 40 -40°C 260 0 140 -0.05 100 RW 60 20 -40°C 125°C 85°C 25°C 0 32 -0.1 -0.15 -0.2 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-40: 100 k Pot Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). 2008-2013 Microchip Technology Inc. 32 -0.2 -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-41: 100 k Rheo Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 0.15 0.05 180 RW 125°C 85°C 25°C 300 0.1 0.1 0 0.2 Error (LSb) Wiper Resistance (R W) (ohms) 300 0.2 60 0 FIGURE 2-39: 100 k Pot Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 0.3 125C Rw 125C INL 125C DNL DNL 80 20 Wiper Resistance (Rw) (ohms) 0 85C Rw 85C INL 85C DNL INL 125°C 85°C 20 25C Rw 25C INL 25C DNL Error (LSb) 85C Rw 85C INL 85C DNL -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL INL 220 125C Rw 125C INL 125C DNL 0.6 0.4 0.2 DNL 180 0 140 RW 100 60 20 -40°C -0.2 Error (LSb) 100 25C Rw 25C INL 25C DNL Wiper Resistance (R W ) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (R W ) (ohms) 120 -0.4 125°C 85°C 25°C 0 32 -0.6 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-42: 100 k Rheo Mode – RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). DS22107B-page 29 MCP454X/456X/464X/466X 120000 103500 103000 102500 102000 101500 101000 100500 100000 99500 99000 98500 100000 Rwb (Ohms) Nominal Resistance (R (Ohms) AB) Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 1.8V 2.7V 80000 60000 40000 -40°C 25°C 85°C 125°C 20000 5.5V 0 -40 0 40 80 Ambient Temperature (°C) 120 FIGURE 2-43: 100 k – Nominal Resistance () vs. Ambient Temperature and VDD . DS22107B-page 30 0 32 64 96 128 160 192 Wiper Setting (decimal) 224 256 FIGURE 2-44: 100 k – RWB () vs. Wiper Setting and Ambient Temperature. 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. FIGURE 2-45: 100 k – Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 µs/Div). FIGURE 2-47: 100 k – Low-Voltage Increment Wiper Settling Time (VDD =5.5V) (1 µs/Div). FIGURE 2-46: 100 k – Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 µs/Div). FIGURE 2-48: 100 k – Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 µs/Div) 2008-2013 Microchip Technology Inc. DS22107B-page 31 MCP454X/456X/464X/466X 0.12 0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0.1 0.08 5.5V % % Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 0.06 0.04 3.0V 0.02 3.0V 0 -40 0 40 80 Temperature (°C) 120 FIGURE 2-49: Resistor Network 0 to Resistor Network 1 RAB (5 k) Mismatch vs. VDD and Temperature. -40 0.04 0.05 0.03 0.04 40 80 Temperature (°C) 0.03 5.5V 0.01 0 120 FIGURE 2-51: Resistor Network 0 to Resistor Network 1 RAB (50 k) Mismatch vs. VDD and Temperature. 0.02 5.5V 0.02 0 % % 5.5V -0.01 3.0V 0 3.0V -0.02 0.01 -0.01 -0.03 -0.02 -0.04 -0.03 -40 0 40 80 Temperature (°C) 120 FIGURE 2-50: Resistor Network 0 to Resistor Network 1 RAB (10 k) Mismatch vs. VDD and Temperature. DS22107B-page 32 -40 10 60 Temperature (°C) 110 FIGURE 2-52: Resistor Network 0 to Resistor Network 1 RAB (100 k) Mismatch vs. VDD and Temperature. 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 4 3.5 5.5V VOL (mV) VIH (V) 3 2.5 2 2.7V 1.5 230 210 2.7V 190 170 150 130 5.5V 110 90 70 50 1 -40 0 40 80 120 Temperature (°C) FIGURE 2-53: Temperature. -40 0 40 80 120 Temperature (°C) VIH (SDA, SCL) vs. VDD and FIGURE 2-55: VOL (SDA) vs. VDD and Temperature (IOL = 3 mA). 2 VIL (V) 5.5V 1.5 2.7V 1 -40 0 40 80 120 Temperature (°C) FIGURE 2-54: Temperature. VIL (SDA, SCL) vs. VDD and 2008-2013 Microchip Technology Inc. DS22107B-page 33 MCP454X/456X/464X/466X 2.1 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. Test Circuits 4.2 +5V tWC (ms) 4.0 A VIN 3.8 3.6 B Offset GND 3.4 3.2 W + VOUT - 2.5V DC 3.0 -40 0 40 80 120 Temperature (°C) FIGURE 2-56: Nominal EEPROM Write Cycle Time vs. VDD and Temperature. FIGURE 2-58: Test. -3 db Gain vs. Frequency 1.2 1 floating VA A 5.5V VDD (V) 0.8 0.6 VW W 2.7V 0.4 IW 0.2 B 0 -40 0 40 80 VB RBW = VW/IW RW = (VW-VA)/IW 120 Temperature (°C) FIGURE 2-57: POR/BOR Trip Point vs. VDD and Temperature. DS22107B-page 34 FIGURE 2-59: RBW and RW Measurement. 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follow. TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP454X/456X/464X/466X Pin Single Dual Rheo Pot (1) Rheo Pot Symbol I/O Buffer Type Weak Pull-up/ down (1) Standard Function 8L 8L 10L 14L 16L 1 1 1 1 16 HVC/A0 I HV w/ST “smart” 2 2 2 2 1 SCL I HV w/ST No I2C clock input. 3 3 3 3 2 SDA I/O HV w/ST No I2C serial data I/O. Open Drain output 4 4 4 4 3, 4 VSS — P — Ground — — 5 5 5 P1B A Analog No Potentiometer 1 Terminal B — — 6 6 6 P1W A Analog No Potentiometer 1 Wiper Terminal — — — 7 7 P1A A Analog No Potentiometer 1 Terminal A — 5 — 8 8 P0A A Analog No Potentiometer 0 Terminal A 5 6 7 9 9 P0W A Analog No Potentiometer 0 Wiper Terminal 6 7 8 10 10 P0B A Analog No Potentiometer 0 Terminal B — — — 11 12 WP I HV w/ST “smart” Hardware EEPROM Write Protect — — — 12 13 A2 I HV w/ST “smart” Address 2 7 — 9 13 14 A1 I HV w/ST “smart” 8 8 10 14 15 VDD — P — — — — — 11 NC — — — No Connection 9 9 11 — 17 EP — — — Exposed Pad (Note 2) Legend: Note 1: 2: High Voltage Command / Address 0. Address 1 Positive Power Supply Input HV w/ST = High Voltage tolerant input (with Schmidtt trigger input) A = Analog pins (Potentiometer terminals) I = digital input (high Z) O = digital output I/O = Input / Output P = Power The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and shutdown current. The DFN and QFN packages have a contact on the bottom of the package. This contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device’s VSS pin. 2008-2013 Microchip Technology Inc. DS22107B-page 35 MCP454X/456X/464X/466X 3.1 High Voltage Command / Address 0 (HVC/A0) The HVC/A0 pin is the Address 0 input for the I2C interface as well as the High Voltage Command pin. At the device’s POR/BOR, the value of the A0 address bit is latched. This input, along with the A2 and A1 pins, completes the device address. This allows up to eight MCP45xx/46xx devices on a single I2C bus. During normal operation, the the voltage on this pin determines if the I2C command is a normal command or a High Voltage command (when HVC/A0 = VIHH). 3.2 Serial Clock (SCL) The SCL pin is the serial interfaces Serial Clock pin. This pin is connected to the Host Controllers SCL pin. The MCP45XX/46XX is a slave device, so its SCL pin accepts only external clock signals. 3.3 Serial Data (SDA) The SDA pin is the serial interfaces Serial Data pin. This pin is connected to the Host Controllers SDA pin. The SDA pin is an open-drain N-channel driver. 3.7 Potentiometer Terminal A The terminal A pin is available on the MCP4XX1 devices, and is connected to the internal potentiometer’s terminal A. The potentiometer’s terminal A is the fixed connection to the Full-Scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x100 for 8-bit devices or 0x80 for 7-bit devices. The terminal A pin does not have a polarity relative to the terminal W or B pins. The terminal A pin can support both positive and negative current. The voltage on terminal A must be between VSS and VDD. The terminal A pin is not available on the MCP4XX2 devices, and the internally terminal A signal is floating. MCP46X1 devices have two terminal A pins, one for each resistor network. 3.8 Write Protect (WP) The WP pin is used to force the nonvolatile memory to be write protected. 3.9 Address 2 (A2) The VSS pin is the device ground reference. The A2 pin is the I2C interface’s Address 2 pin. Along with the A1 and A0 pins, up to 8 MCP45XX/46XX devices can be on a single I2C bus. 3.5 3.10 3.4 Ground (VSS) Potentiometer Terminal B The terminal B pin is connected to the internal potentiometer’s terminal B. The potentiometer’s terminal B is the fixed connection to the Zero Scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x00 for both 7-bit and 8-bit devices. The terminal B pin does not have a polarity relative to the terminal W or A pins. The terminal B pin can support both positive and negative current. The voltage on terminal B must be between VSS and VDD. MCP46XX devices have two terminal B pins, one for each resistor network. 3.6 Potentiometer Wiper (W) Terminal The terminal W pin is connected to the internal potentiometer’s terminal W (the wiper). The wiper terminal is the adjustable terminal of the digital potentiometer. The terminal W pin does not have a polarity relative to terminals A or B pins. The terminal W pin can support both positive and negative current. The voltage on terminal W must be between VSS and VDD. Address 1 (A1) The A2 pin is the I2C interface’s Address 1 pin. Along with the A2 and A0 pins, up to 8 MCP45XX/46XX devices can be on a single I2C bus. 3.11 Positive Power Supply Input (VDD) The VDD pin is the device’s positive power supply input. The input power supply is relative to VSS. While the device VDD < Vmin (2.7V), the electrical performance of the device may not meet the data sheet specifications. 3.12 No Connect (NC) These pins should be either connected to VDD or VSS. 3.13 Exposed Pad (EP) This pad is conductively connected to the device’s substrate. This pad should be tied to the same potential as the VSS pin (or left unconnected). This pad could be used to assist as a heat sink for the device when connected to a PCB heat sink. MCP46XX devices have two terminal W pins, one for each resistor network. DS22107B-page 36 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 4.0 FUNCTIONAL OVERVIEW This Data Sheet covers a family of thirty-two Digital Potentiometer and Rheostat devices that will be referred to as MCP4XXX. The MCP4XX1 devices are the Potentiometer configuration, while the MCP4XX2 devices are the Rheostat configuration. As the Device Block Diagram shows, there are four main functional blocks. These are: • • • • POR/BOR Operation Memory Map Resistor Network Serial Interface (I2C) The POR/BOR operation and the Memory Map are discussed in this section and the Resistor Network and I2C operation are described in their own sections. The Device Commands commands are discussed in Section 7.0 “Device Commands”. 4.1 POR/BOR Operation The Power-on Reset is the case where the device has power applied to it, starting from the VSS level. The Brown-out Reset occurs when power is applied to the device, and that power (voltage) drops below the specified range. The device’s RAM retention voltage (VRAM) is lower than the POR/BOR voltage trip point (VPOR/VBOR). The maximum VPOR/VBOR voltage is less than 1.8V. When VPOR/VBOR < VDD < 2.7V, the electrical performance may not meet the data sheet specifications. In this region, the device is capable of reading and writing to its EEPROM and incrementing, decrementing, reading and writing to its volatile memory if the proper serial command is executed. 4.1.1 POWER-ON RESET When the device powers up, the device VDD will cross the VPOR/VBOR voltage. Once the VDD voltage crosses the VPOR/VBOR voltage the following happens: • Volatile wiper register is loaded with value in the corresponding nonvolatile wiper register • The TCON register is loaded its default value • The device is capable of digital operation 2008-2013 Microchip Technology Inc. 4.1.2 BROWN-OUT RESET When the device powers down, the device VDD will cross the VPOR/VBOR voltage. Once the VDD voltage decreases below the VPOR/VBOR voltage the following happens: • Serial Interface is disabled • EEPROM Writes are disabled If the VDD voltage decreases below the VRAM voltage the following happens: • Volatile wiper registers may become corrupted • TCON register may become corrupted As the voltage recovers above the VPOR/VBOR voltage see Section 4.1.1 “Power-on Reset”. Serial commands not completed due to a brown-out condition may cause the memory location (volatile and nonvolatile) to become corrupted. 4.2 Memory Map The device memory is 16 locations that are 9-bits wide (16x9 bits). This memory space contains both volatile and nonvolatile locations (see Table 4-1). TABLE 4-1: Address MEMORY MAP Function Memory Type 00h Volatile Wiper 0 01h Volatile Wiper 1 RAM 02h Nonvolatile Wiper 0 EEPROM 03h Nonvolatile Wiper 1 EEPROM RAM 04h Volatile TCON Register RAM 05h Status Register RAM 06h Data EEPROM EEPROM 07h Data EEPROM EEPROM 08h Data EEPROM EEPROM 09h Data EEPROM EEPROM 0Ah Data EEPROM EEPROM 0Bh Data EEPROM EEPROM 0Ch Data EEPROM EEPROM 0Dh Data EEPROM EEPROM 0Eh Data EEPROM EEPROM 0Fh Data EEPROM EEPROM DS22107B-page 37 MCP454X/456X/464X/466X 4.2.1 4.2.1.4 NONVOLATILE MEMORY (EEPROM) This memory can be grouped into two uses of nonvolatile memory. These are: • General Purpose Registers • Nonvolatile Wiper Registers The nonvolatile wipers starts functioning below the devices VPOR/VBOR trip point. 4.2.1.1 General Purpose Registers These locations allow the user to store up to 10 (9-bit) locations worth of information. 4.2.1.2 Nonvolatile Wiper Registers Special Features There are three nonvolatile bits that are not directly mapped into the address space. These bits control the following functions: • EEPROM Write Protect • WiperLock Technology for Nonvolatile Wiper 0 • WiperLock Technology for Nonvolatile Wiper 1 The operation of WiperLock Technology is discussed in Section 5.3. The state of the WL0, WL1, and WP bits is reflected in the STATUS register (see Register 4-1). EEPROM Write Protect All internal EEPROM memory can be Write Protected. When EEPROM memory is Write Protected, Write commands to the internal EEPROM are prevented. These locations contain the wiper values that are loaded into the corresponding volatile wiper register whenever the device has a POR/BOR event. There are up to two registers, one for each resistor network. Write Protect (WP) can be enabled/disabled by two methods. These are: The nonvolatile wiper register enables stand-alone operation of the device (without Microcontroller control) after being programmed to the desired value. • External WP Hardware pin (MCP46X1 devices only) • Nonvolatile configuration bit 4.2.1.3 High Voltage commands are required to enable and disable the nonvolatile WP bit. These commands are shown in Section 7.8 “Modify Write Protect or WiperLock Technology (High Voltage)”. Factory Initialization of Nonvolatile Memory (EEPROM) The Nonvolatile Wiper values will be initialized to mid-scale value. This is shown in Table 4-2. The General purpose EEPROM memory will be programmed to a default value of 0xFF. It is good practice in the manufacturing flow to configure the device to your desired settings. -502 5.0 k Mid-scale 80h 40h Disabled -103 10.0 k Mid-scale 80h 40h Disabled -503 50.0 k Mid-scale 80h 40h Disabled -104 100.0 k Mid-scale 80h 40h Disabled Resistance Code Default POR Wiper Setting Wiper Code WiperLock™ Technology and Write Protect Setting DEFAULT FACTORY SETTINGS SELECTION Typical RAB Value TABLE 4-2: DS22107B-page 38 8-bit 7-bit To write to EEPROM, both the external WP pin and the internal WP EEPROM bit must be disabled. Write Protect does not block commands to the volatile registers. 4.2.2 VOLATILE MEMORY (RAM) There are four Volatile Memory locations. These are: • Volatile Wiper 0 • Volatile Wiper 1 (Dual Resistor Network devices only) • Status Register • Terminal Control (TCON) Register The volatile memory starts functioning at the RAM retention voltage (VRAM). 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 4.2.2.1 Status (STATUS) Register This register contains four status bits. These bits show the state of the WiperLock bits, the Write Protect bit, and if an EEPROM write cycle is active. The STATUS register can be accessed via the READ commands. Register 4-1 describes each STATUS register bit. The STATUS register is placed at Address 05h. REGISTER 4-1: R-1 STATUS REGISTER (ADDRESS = 0x05) R-1 R-1 R-1 D8:D4 R-1 R-0 EEWA R-x WL1 (1) R-x WL0 (1) bit 7 R-x WP (1) bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8-4 D8:D4: Reserved. Forced to “1” bit 3 EEWA: EEPROM Write Active Status bit This bit indicates if the EEPROM Write Cycle is occurring. 1 = An EEPROM Write cycle is currently occurring. Only serial commands to the Volatile memory locations are allowed (addresses 00h, 01h, 04h, and 05h) 0 = An EEPROM Write cycle is NOT currently occurring bit 2 WL1: WiperLock Status bit for Resistor Network 1 (Refer to Section 5.3 “WiperLock™ Technology” for further information) WiperLock (WL) prevents the Volatile and Nonvolatile Wiper 1 addresses and the TCON register bits R1HW, R1A, R1W, and R1B from being written to. High Voltage commands are required to enable and disable WiperLock Technology. 1 = Wiper and TCON register bits R1HW, R1A, R1W, and R1B of Resistor Network 1 (Pot 1) are “Locked” (Write Protected) 0 = Wiper and TCON of Resistor Network 1 (Pot 1) can be modified Note: bit 1 WL0: WiperLock Status bit for Resistor Network 0 (Refer to Section 5.3 “WiperLock™ Technology” for further information) The WiperLock Technology bits (WLx) prevents the Volatile and Nonvolatile Wiper 0 addresses and the TCON register bits R0HW, R0A, R0W, and R0B from being written to. High Voltage commands are required to enable and disable WiperLock Technology. 1 = Wiper and TCON register bits R0HW, R0A, R0W, and R0B of Resistor Network 0 (Pot 0) are “Locked” (Write Protected) 0 = Wiper and TCON of Resistor Network 0 (Pot 0) can be modified Note: Note 1: The WL1 bit always reflects the result of the last programming cycle to the nonvolatile WL1 bit. After a POR or BOR event, the WL1 bit is loaded with the nonvolatile WL1 bit value. The WL0 bit always reflects the result of the last programming cycle to the nonvolatile WL0 bit. After a POR or BOR event, the WL0 bit is loaded with the nonvolatile WL0 bit value. Requires a High Voltage command to modify the state of this bit (for nonvolatile devices only). This bit is not directly written, but reflects the system state (for this feature). 2008-2013 Microchip Technology Inc. DS22107B-page 39 MCP454X/456X/464X/466X REGISTER 4-1: bit 0 Note 1: STATUS REGISTER (ADDRESS = 0x05) (CONTINUED) WP: EEPROM Write Protect Status bit (Refer to the section EEPROM Write Protect for further information) This bit indicates the status of the write protection on the EEPROM memory. When Write Protect is enabled, writes to all nonvolatile memory are prevented. This includes the General Purpose EEPROM memory, and the nonvolatile Wiper registers. Write Protect does not block modification of the volatile wiper register values or the volatile TCON register value (via Increment, Decrement, or Write commands). This status bit is an OR of the devices Write Protect pin (WP) and the internal nonvolatile WP bit. High Voltage commands are required to enable and disable the internal WP EEPROM bit. 1 = EEPROM memory is Write Protected 0 = EEPROM memory can be written Requires a High Voltage command to modify the state of this bit (for nonvolatile devices only). This bit is not directly written, but reflects the system state (for this feature). DS22107B-page 40 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 4.2.2.2 Terminal Control (TCON) Register This register contains eight control bits. Four bits are for Wiper 0, and four bits are for Wiper 1. Register 4-2 describes each bit of the TCON register. The state of each resistor network terminal connection is individually controlled. That is, each terminal connection (A, B and W) can be individually connected/ disconnected from the resistor network. This allows the system to minimize the currents through the digital potentiometer. The value that is written to this register will appear on the resistor network terminals when the serial command has completed. When the WL1 bit is enabled, writes to the TCON register bits R1HW, R1A, R1W, and R1B are inhibited. When the WL0 bit is enabled, writes to the TCON register bits R0HW, R0A, R0W, and R0B are inhibited. On a POR/BOR this register is loaded with 1FFh (9-bits), for all terminals connected. The Host Controller needs to detect the POR/BOR event and then update the Volatile TCON register value. Additionally, there is a bit which enables the operation of General Call commands. 2008-2013 Microchip Technology Inc. DS22107B-page 41 MCP454X/456X/464X/466X REGISTER 4-2: TCON BITS (ADDRESS = 0x04) (1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GCEN R1HW R1A R1W R1B R0HW R0A R0W R0B bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8 GCEN: General Call Enable bit This bit specifies if I2C General Call commands are accepted 1 = Enable Device to “Accept” the General Call Address (0000h) 0 = The General Call Address is disabled bit 7 R1HW: Resistor 1 Hardware Configuration Control bit This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin 1 = Resistor 1 is NOT forced to the hardware pin “shutdown” configuration 0 = Resistor 1 is forced to the hardware pin “shutdown” configuration bit 6 R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network 1 = P1A pin is connected to the Resistor 1 Network 0 = P1A pin is disconnected from the Resistor 1 Network bit 5 R1W: Resistor 1 Wiper (P1W pin) Connect Control bit This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network 1 = P1W pin is connected to the Resistor 1 Network 0 = P1W pin is disconnected from the Resistor 1 Network bit 4 R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network 1 = P1B pin is connected to the Resistor 1 Network 0 = P1B pin is disconnected from the Resistor 1 Network bit 3 R0HW: Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin 1 = Resistor 0 is NOT forced to the hardware pin “shutdown” configuration 0 = Resistor 0 is forced to the hardware pin “shutdown” configuration bit 2 R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network 1 = P0A pin is connected to the Resistor 0 Network 0 = P0A pin is disconnected from the Resistor 0 Network bit 1 R0W: Resistor 0 Wiper (P0W pin) Connect Control bit This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network 1 = P0W pin is connected to the Resistor 0 Network 0 = P0W pin is disconnected from the Resistor 0 Network bit 0 R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network 1 = P0B pin is connected to the Resistor 0 Network 0 = P0B pin is disconnected from the Resistor 0 Network Note 1: These bits do not affect the wiper register values. DS22107B-page 42 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 5.0 RESISTOR NETWORK 5.1 The Resistor Network has either 7-bit or 8-bit resolution. Each Resistor Network allows zero scale to full-scale connections. Figure 5-1 shows a block diagram for the resistive network of a device. The Resistor Network is made up of several parts. These include: • Resistor Ladder • Wiper • Shutdown (Terminal Connections) Devices have either one or two resistor networks, These are referred to as Pot 0 and Pot 1. A RW RS RW R RAB S The resistor ladder is a series of equal value resistors (RS) with a connection point (tap) between the two resistors. The total number of resistors in the series (ladder) determines the RAB resistance (see Figure 5-1). The end points of the resistor ladder are connected to analog switches which are connected to the device Terminal A and Terminal B pins. The RAB (and RS) resistance has small variations over voltage and temperature. For an 8-bit device, there are 256 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 256 resistors thus providing 257 possible settings (including terminal A and terminal B). 8-Bit N= 256 (1) (100h) 7-Bit N= 128 (80h) For a 7-bit device, there are 128 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 128 resistors thus providing 129 possible settings (including terminal A and terminal B). 255 (FFh) 127 (7Fh) Equation 5-1 shows the calculation for the step resistance. 254 (FEh) 126 (7Eh) EQUATION 5-1: RW (1) RS Resistor Ladder Module (1) RS CALCULATION R AB R S = ------------ 256 8-bit Device RAB R S = ------------- 128 7-bit Device W RW RS RW 1 (1) (01h) 1 (01h) 0 (00h) 0 (00h) (1) Analog Mux B Note 1: The wiper resistance is dependent on several factors including, wiper code, device VDD, Terminal voltages (on A, B, and W), and temperature. Also for the same conditions, each tap selection resistance has a small variation. This RW variation has greater effects on some specifications (such as INL) for the smaller resistance devices (5.0 k) compared to larger resistance devices (100.0 k). FIGURE 5-1: Resistor Block Diagram. 2008-2013 Microchip Technology Inc. DS22107B-page 43 MCP454X/456X/464X/466X 5.2 Wiper 5.3 Each tap point (between the RS resistors) is a connection point for an analog switch. The opposite side of the analog switch is connected to a common signal which is connected to the Terminal W (Wiper) pin. A value in the volatile wiper register selects which analog switch to close, connecting the W terminal to the selected node of the resistor ladder. The wiper can connect directly to Terminal B or to Terminal A. A zero-scale connection, connects the Terminal W (wiper) to Terminal B (wiper setting of 000h). A full-scale connection, connects the Terminal W (wiper) to Terminal A (wiper setting of 100h or 80h). In these configurations, the only resistance between the Terminal W and the other Terminal (A or B) is that of the analog switches. A wiper setting value greater than full-scale (wiper setting of 100h for 8-bit device or 80h for 7-bit devices) will also be a Full-Scale setting (Terminal W (wiper) connected to Terminal A). Table 5-1 illustrates the full wiper setting map. Equation 5-2 illustrates the calculation used to determine the resistance between the wiper and terminal B. The MCP4XXX device’s WiperLock technology allows application-specific calibration settings to be secured in the EEPROM without requiring the use of an additional write-protect pin. There are two WiperLock Technology configuration bits (WL0 and WL1). These bits prevent the Nonvolatile and Volatile addresses and bits for the specified resistor network from being written. The WiperLock technology prevents commands from doing the following: 8-bit Device N = 0 to 256 (decimal) R AB N R WB = -------------- + R W 128 7-bit Device • Nonvolatile Wiper Register • Volatile Wiper Register • Volatile TCON register bits RxHW, RxA, RxW, and RxB High Voltage commands are required to enable and disable WiperLock. Please refer to the Modify Write Protect or WiperLock Technology (High Voltage) command for operation. TABLE 5-2: 100h Reserved (Full-Scale (W = A)), Increment and Decrement commands ignored Full-Scale (W = A), Increment commands ignored 07Fh 041h 0FFh 081 W=N 040h 080h W = N (Mid-Scale) 03Fh 001h 07Fh 001 W=N 000h 000h Zero Scale (W = B) Decrement command ignored DS22107B-page 44 Factory Default POR Wiper Setting 080h 3FFh 101h DEFAULT FACTORY SETTINGS SELECTION Typical RAB Value Properties 7-bit Pot 8-bit Pot -502 5.0 k Mid-scale 80h 40h -103 10.0 k Mid-scale 80h 40h -503 50.0 k Mid-scale 80h 40h -104 100.0 k Mid-scale 80h 40h Resistance Code VOLATILE WIPER VALUE VS. WIPER POSITION MAP Wiper Setting 3FFh 081h POR/BOR OPERATION WHEN WIPERLOCK TECHNOLOGY ENABLED The WiperLock Technology state is not affected by a POR/BOR event. A POR/BOR event will load the Volatile Wiper register value with the Nonvolatile Wiper register value, refer to Section 4.1. N = 0 to 128 (decimal) TABLE 5-1: serial For either Resistor Network 0 or Resistor Network 1 (Potx), the WLx bit controls the following: RWB CALCULATION R AB N R WB = -------------- + R W 256 the • Changing a volatile wiper value • Writing to a nonvolatile wiper memory location • Changing the volatile TCON register value 5.3.1 EQUATION 5-2: WiperLock™ Technology Wiper Code 8-bit 7-bit 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 5.4 5.4.2 Shutdown Shutdown is used to minimize the device’s current consumption. The MCP4XXX achieves this through the Terminal Control Register (TCON). 5.4.1 TERMINAL CONTROL REGISTER (TCON) The Terminal Control (TCON) register is a volatile register used to configure the connection of each resistor network terminal pin (A, B, and W) to the Resistor Network. This bits are described in Register 4-2. When the RxHW bit is a “0”, the selected resistor network is forced into the following state: INTERACTION OF RxHW BIT AND RxA, RxW, AND RxB BITS (TCON REGISTER) Using the TCON bits allows each resistor network (Pot 0 and Pot 1) to be individually “shutdown”. The state of the RxHW bit does NOT corrupt the other bit values in the TCON register nor the value of the Volatile Wiper Registers. When the Shutdown mode is exited (RxHW changes state from “0” to “1”): • The device returns to the Wiper setting specified by the Volatile Wiper value • The RxA, RxB, and RxW bits return to controlling the terminal connection state of that resistor network • The PxA terminal is disconnected • The PxW terminal is simultaneously connected to the PxB terminal (see Figure 5-2) • The Serial Interface is NOT disabled, and all Serial Interface activity is executed • Any EEPROM write cycles are completed Alternate low power configurations may be achieved with the RxA, RxW, and RxB bits. Note 1: The RxHW bits are identical to the RxHW bits of the MCP41XX/42XX devices. The MCP42XX devices also have a SHDN pin which forces the resistor network into the same state as that resistor networks RxHW bit. 2: When RxHW = “0”, the state of the TCON register RxA, RxW, and RxB bits is overridden (ignored). When the state of the RxHW bit returns to “1”, the TCON register RxA, RxW, and RxB bits return to controlling the terminal connection state. In other words, the RxHW bit does not corrupt the state of the RxA, RxW, and RxB bits. Resistor Network A FIGURE 5-2: Configuration. W B Resistor Network Shutdown 2008-2013 Microchip Technology Inc. DS22107B-page 45 MCP454X/456X/464X/466X NOTES: DS22107B-page 46 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 6.0 SERIAL INTERFACE (I2C) 6.1 The MCP45XX/46XX devices support the I2C serial protocol. The MCP45XX/46XX I2C’s module operates in Slave mode (does not generate the serial clock). Figure 6-1 shows a typical I2C Interface connection. All I2C interface signals are high-voltage tolerant. The MCP45XX/46XX devices use the two-wire I2C serial interface. This interface can operate in standard, fast or High-Speed mode. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access and generates the START and STOP conditions. The MCP45XX/46XX device works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. Communication is initiated by the master (microcontroller) which sends the START bit, followed by the slave address byte. The first byte transmitted is always the slave address byte, which contains the device code, the address bits, and the R/W bit. 2C Refer to the Phillips I the I2C specifications. document for more details of Typical I2C Interface Connections MCP4XXX Host Controller SCL SCL SDA SDA I/O (1) HVC/A0 (2) A1 (2, 3) A2 (2, 3) Note 1: If High voltage commands are desired, some type of external circuitry needs to be implemented. 2: These pins have internal pull-ups. If faster rise times are required, then external pull-ups should be added. 3: This pin could be tied high, low, or connected to an I/O pin of the Host Controller. FIGURE 6-1: Diagram. Typical I2C Interface Block Signal Descriptions The I2C interface uses up to five pins (signals). These are: • • • • • SDA (Serial Data) SCL (Serial Clock) A0 (Address 0 bit) A1 (Address 1 bit) A2 (Address 2 bit) 6.1.1 SERIAL DATA (SDA) The Serial Data (SDA) signal is the data signal of the device. The value on this pin is latched on the rising edge of the SCL signal when the signal is an input. With the exception of the START and STOP conditions, the high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. During the high period of the clock the SDA pin’s value (high or low) must be stable. Changes in the SDA pin’s value while the SCL pin is HIGH will be interpreted as a START or a STOP condition. 6.1.2 SERIAL CLOCK (SCL) The Serial Clock (SCL) signal is the clock signal of the device. The rising edge of the SCL signal latches the value on the SDA pin. The MCP45XX/46XX supports three I2C interface clock modes: • Standard Mode: clock rates up to 100 kHz • Fast Mode: clock rates up to 400 kHz • High-Speed Mode (HS mode): clock rates up to 3.4 MHz The MCP4XXX will not strech the clock signal (SCL) since memory read acceses occur fast enough. Depending on the clock rate mode, the interface will display different characteristics. 6.1.3 THE ADDRESS BITS (A2:A1:A0) There are up to three hardware pins used to specify the device address. The number of adress pins is determined by the part number. Address 0 is multiplexed with the High Voltage Command (HVC) function. So the state of A0 is latched on the MCP4XXX’s POR/BOR event. The state of the A2 and A1 pins should be static, that is they should be tied high or tied low. 6.1.3.1 The High Voltage Command (HVC) Signal The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage mode. High Voltage commands allow the device’s WiperLock Technology and write protect features to be enabled and disabled. The HVC pin has an internal resistor connection to the MCP45XX/46XXs internal VDD signal. 2008-2013 Microchip Technology Inc. DS22107B-page 47 MCP454X/456X/464X/466X 6.2 I2C Operation 6.2.1.3 The MCP45XX/46XX’s I2C module is compatible with the Philips I2C specification. The following lists some of the modules features: • 7-bit slave addressing • Supports three clock rate modes: - Standard mode, clock rates up to 100 kHz - Fast mode, clock rates up to 400 kHz - High-speed mode (HS mode), clock rates up to 3.4 MHz • Support Multi-Master Applications • General call addressing • Internal weak pull-ups on interface signals The I2C 10-bit addressing mode is not supported. The Philips I2C specification only defines the field types, field lengths, timings, etc. of a frame. The frame content defines the behavior of the device. The frame content for the MCP4XXX is defined in Section 7.0. 6.2.1 I2C BIT STATES AND SEQUENCE Figure 6-8 shows the I2C transfer sequence. The serial clock is generated by the master. The following definitions are used for the bit states: • Start bit (S) • Data bit • Acknowledge (A) bit (driven low) / No Acknowledge (A) bit (not driven low) • Repeated Start bit (Sr) • Stop bit (P) 6.2.1.1 2nd Bit SCL S FIGURE 6-2: 6.2.1.2 Start Bit. Data Bit The SDA signal may change state while the SCL signal is Low. While the SCL signal is High, the SDA signal MUST be stable (see Figure 6-5). SDA 1st Bit SCL DS22107B-page 48 SCL FIGURE 6-4: Data Bit. D0 A 8 9 Acknowledge Waveform. Not A (A) Response The A bit has the SDA signal high. Table 6-1 shows some of the conditions where the Slave Device will issue a Not A (A). If an error condition occurs (such as an A instead of A), then an START bit must be issued to reset the command state machine. MCP45XX/MCP46XX A / A RESPONSES Acknowledge Bit Response Comment General Call A Slave Address valid A Slave Address not valid A Device Memory Address and specified command (AD3:AD0 and C1:C0) are an invalid combination A After device has received address and command Communication during EEPROM write cycle A After device has received address and command, and valid conditions for EEPROM write N.A. I2C Module Resets, or a “Don’t Care” if the collision occurs on the Masters “Start bit”. 2nd Bit Bus Collision Data Bit FIGURE 6-3: SDA Event The Start bit (see Figure 6-2) indicates the beginning of a data transfer sequence. The Start bit is defined as the SDA signal falling when the SCL signal is “High”. 1st Bit The A bit (see Figure 6-4) is typically a response from the receiving device to the transmitting device. Depending on the context of the transfer sequence, the A bit may indicate different things. Typically the Slave device will supply an A response after the Start bit and eight “data” bits have been received. An A bit has the SDA signal low. TABLE 6-1: Start Bit SDA Acknowledge (A) Bit Only if GCEN bit is set 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 6.2.1.4 6.2.1.5 Repeated Start Bit The Repeated Start bit (see Figure 6-5) indicates the current Master Device wishes to continue communicating with the current Slave Device without releasing the I2C bus. The Repeated Start condition is the same as the Start condition, except that the Repeated Start bit follows a Start bit (with the Data bits + A bit) and not a Stop bit. Stop Bit The Stop bit (see Figure 6-6) Indicates the end of the I2C Data Transfer Sequence. The Stop bit is defined as the SDA signal rising when the SCL signal is “High”. A Stop bit resets the I2C interface of all MCP4XXX devices. SDA A / A The Start bit is the beginning of a data transfer sequence and is defined as the SDA signal falling when the SCL signal is “High”. SCL P Note 1: A bus collision during the Repeated Start condition occurs if: FIGURE 6-6: Transmit Mode. • SDA is sampled low when SCL goes from low to high. 6.2.2 • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". Stop Condition Receive or CLOCK STRETCHING “Clock Stretching” is something that the receiving device can do, to allow additional time to “respond” to the “data” that has been received. The MCP4XXX will not strech the clock signal (SCL) since memory read acceses occur fast enough. 1st Bit SDA 6.2.3 If any part of the I2C transmission does not meet the command format, it is aborted. This can be intentionally accomplished with a START or STOP condition. This is done so that noisy transmissions (usually an extra START or STOP condition) are aborted before they corrupt the device. SCL Sr = Repeated Start FIGURE 6-5: Waveform. ABORTING A TRANSMISSION Repeat Start Condition SDA SCL S FIGURE 6-7: 1st Bit 2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit A/A P Typical 8-Bit I2C Waveform Format. SDA SCL START Condition FIGURE 6-8: Data allowed to change Data or A valid STOP Condition I2C Data States and Bit Sequence. 2008-2013 Microchip Technology Inc. DS22107B-page 49 MCP454X/456X/464X/466X 6.2.4 ADDRESSING The address byte is the first byte received following the START condition from the master device. The address contains four (or more) fixed bits and (up to) three user defined hardware address bits (pins A2, A1, and A0). These 7-bits address the desired I2C device. The A7:A4 address bits are fixed to “0101” and the device appends the value of following three address pins (A2, A1, A0). Address pins that are not present on the device are pulled up (a bit value of ‘1’). Since there are up to three adress bits controlled by hardware pins, there may be up to eight MCP4XXX devices on the same I2C bus. Figure 6-9 shows the slave address byte format, which contains the seven address bits. There is also a read/ write bit. Table 6-2 shows the fixed address for device. Hardware Address Pins The hardware address bits (A2, A1, and A0) correspond to the logic level on the associated address pins. This allows up to eight devices on the bus. These pins have a weak pull-up enabled when the VDD < VBOR. The weak pull-up utilizes the “smart” pull-up technology and exhibits the same characteristics as the High-voltage tolerant I/O structure. The state of the A0 address pin is latch on POR/BOR. This is required since High Voltage commands force this pin (HVC/A0) to the VIHH level. Slave Address S A6 A5 A4 A3 A2 A1 A0 R/W “0” “1” “0” “1” See Table 6-2 Start bit A/A R/W bit R/W = 0 = write R/W = 1 = read A bit (controlled by slave device) A = 0 = Slave Device Acknowledges byte A = 1 = Slave Device does not Acknowledge byte FIGURE 6-9: I2C Control Byte. TABLE 6-2: Slave Address Bits in the DEVICE SLAVE ADDRESSES Device Address MCP45X1 ‘0101 11’b + A0 Comment Supports up to devices. Note 1 MCP45X2 ‘0101 1’b + A1:A0 Supports up to devices. Note 1 MCP46X1 ‘0101’b + A2:A1:A0 Supports up to devices. Note 1 MCP46X2 ‘0101 1’b + A1:A0 Supports up to devices. Note 1 Note 1: A0 is used for High-Voltage commands and the value is latched at POR. 6.2.5 2 4 8 4 SLOPE CONTROL The MCP45XX/46XX implements slope control on the SDA output. As the device transitions from HS mode to FS mode, the slope control parmameter will change from the HS specification to the FS specification. For Fast (FS) and High-Speed (HS) modes, the device has a spike suppression and a Schmidt trigger at SDA and SCL inputs. DS22107B-page 50 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 6.2.6 HS MODE After switching to the High-Speed mode, the next transferred byte is the I2C control byte, which specifies the device to communicate with, and any number of data bytes plus acknowledgements. The Master Device can then either issue a Repeated Start bit to address a different device (at High-Speed) or a Stop bit to return to Fast/Standard bus speed. After the Stop bit, any other Master Device (in a Multi-Master system) can arbitrate for the I2C bus. 2 The I C specification requires that a high-speed mode device must be ‘activated’ to operate in high-speed (3.4 Mbit/s) mode. This is done by the Master sending a special address byte following the START bit. This byte is referred to as the high-speed Master Mode Code (HSMMC). The MCP45XX/46XX device does not acknowledge this byte. However, upon receiving this command, the device switches to HS mode. The device can now communicate at up to 3.4 Mbit/s on SDA and SCL lines. The device will switch out of the HS mode on the next STOP condition. See Figure 6-10 for an illustration of the HS mode command sequence. For more information on the HS mode, or other I2C modes, please refer to the Phillips I2C specification. The master code is sent as follows: 1. 2. 3. 6.2.6.1 START condition (S) High-Speed Master Mode Code (0000 1XXX), The XXX bits are unique to the high-speed (HS) mode Master. No Acknowledge (A) Slope Control The slope control on the SDA output is different between the Fast/Standard Speed and the High-Speed Clock modes of the interface. 6.2.6.2 Pulse Gobbler The pulse gobbler on the SCL pin is automatically adjusted to suppress spikes < 10 ns during HS mode. F/S-mode HS-mode P F/S-mode S ‘0 0 0 0 1 X X X’b A Sr ‘Slave Address’ R/W A HS Select Byte Control Byte “Data” Command/Data Byte(s) S = Start bit Sr = Repeated Start bit A = Acknowledge bit A = Not Acknowledge bit R/W = Read/Write bit P = Stop bit (Stop condition terminates HS Mode) FIGURE 6-10: A/A HS-mode continues Sr ‘Slave Address’ R/W A Control Byte HS Mode Sequence. 2008-2013 Microchip Technology Inc. DS22107B-page 51 MCP454X/456X/464X/466X 6.2.7 GENERAL CALL The General Call is a method that the “Master” device can communicate with all other “Slave” devices. In a Multi-Master application, the other Master devices are operating in Slave mode. The General Call address has two documented formats. These are shown in Figure 6-11. We have added a MCP45XX/46XX format in this figure as well. This will allow customers to have multiple I2C Digital Potentiometers on the bus and have them operate in a synchronous fashion (analogous to the DAC Sync pin functionality). If these MCP45XX/46XX 7-bit commands conflict with other I2C devices on the bus, then the customer will need two I2C busses and ensure that the devices are on the correct bus for their desired application functionality. Dual Pot devices can not update both Pot0 and Pot1 from a single command. To address this, there are General Call commands for the Wiper 0, Wiper 1, and the TCON registers. Table 6-3 shows the General Call Commands. Three commands are specified by the I2C specification and are not applicable to the MCP45XX/46XX (so command is Not Acknowledged) The MCP45XX/46XX General Call Commands are Acknowledge. Any other command is Not Acknowledged. Note: Only one General Call command per issue of the General Call control byte. Any additional General Call commands are ignored and Not Acknowledged. DS22107B-page 52 TABLE 6-3: 7-bit Command GENERAL CALL COMMANDS Comment (1, 2, 3) ‘1000 00d’b Write Next Byte (Third Byte) to Volatile Wiper 0 Register ‘1001 00d’b Write Next Byte (Third Byte) to Volatile Wiper 1 Register ‘1100 00d’b Write Next Byte (Third Byte) to TCON Register ‘1000 010’b Increment Wiper 0 Register or ‘1000 011’b ‘1001 010’b Increment Wiper 1 Register or ‘1001 011’b ‘1000 100’b Decrement Wiper 0 Register or ‘1000 101’b ‘1001 100’b Decrement Wiper 1 Register or ‘1001 101’b Note 1: 2: 3: Any other code is Not Acknowledged. These codes may be used by other devices on the I2C bus. The 7-bit command always appends a “0” to form 8-bits. . “d” is the D8 bit for the 9-bit write value. 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X Second Byte S 0 0 0 0 0 0 0 0 A X X X X X General Call Address X X 0 A P “7-bit Command” Reserved 7-bit Commands (By I2C Specification - Philips # 9398 393 40011, Ver. 2.1 January 2000) ‘0000 011’b - Reset and write programmable part of slave address by hardware. ‘0000 010’b - Write programmable part of slave address by hardware. ‘0000 000’b - NOT Allowed MCP45XX/MCP46XX 7-bit Commands ‘1000 01x’b - Increment Wiper 0 Register. ‘1001 01x’b - Increment Wiper 1 Register. ‘1000 10x’b - Decrement Wiper 0 Register. ‘1001 10x’b - Decrement Wiper 1 Register. The Following is a Microchip Extension to this General Call Format Second Byte S 0 0 0 0 0 0 0 0 A X X X X X General Call Address X d 0 Third Byte A d “7-bit Command” d d d d d d d A P “0” for General Call Command MCP45XX/MCP46XX 7-bit Commands ‘1000 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 0 Register. ‘1001 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 1 Register. ‘1100 00d’b - Write Next Byte (Third Byte) to TCON Register. The Following is a “Hardware General Call” Format Second Byte S 0 0 0 0 0 0 0 0 General Call Address FIGURE 6-11: A X X X X X “7-bit Command” X n occurrences of (Data + A) X 1 A X X X X X X X X A P This indicates a “Hardware General Call” MCP45XX/MCP46XX will ignore this byte and all following bytes (and A), until a Stop bit (P) is encountered. General Call Formats. 2008-2013 Microchip Technology Inc. DS22107B-page 53 MCP454X/456X/464X/466X NOTES: DS22107B-page 54 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 7.0 DEVICE COMMANDS The MCP4XXX’s I2C command formats are specified in this section. The I2C protocol does not specify how commands are formatted. The MCP4XXX supports four basic commands. Depending on the location accessed, this determines the commands that are supported. For the Volatile Wiper Registers, these commands are: • • • • Table 7-3 shows an overview of all the device commands and their interaction with other device features. For the Nonvolatile wiper EEPROM, general purpose data EEPROM, and the TCON Register these commands are: • Write Data • Read Data These commands have formats for both a single command or continuous commands. These commands are shown in Table 7-1. Each command has two operational states. The operational state determines if the device commands control the special features (Write Protect and WiperLock Technology). These operational states are referred to as: • Normal Serial Commands • High-Voltage Serial Commands I2C COMMANDS Command Operation Mode Additionally, there are two commands used to enable or disable the special features (Write Protect and Wiper Lock Technology) of the device. The commands are special cases of the Increment and Decrement High-Voltage Serial Command. Table 7-2 shows the supported commands for each memory location. Write Data Read Data Increment Data Decrement Data TABLE 7-1: Normal serial commands are those where the HVC pin is driven to VIH or VIL. With High-Voltage Serial Commands, the HVC pin is driven to VIHH. In each mode, there are four possible commands. # of Bit Clocks (1) Write Data Operates on Volatile/ Nonvolatile memory Single 29 Both Continuous 18n + 11 Volatile Only Read Data Single 29 Both Random 48 Both Continuous 18n + 11 Both (2) Increment Single 20 Volatile Only (3) Continuous 9n + 11 Volatile Only 20 Volatile Only Decrement Single (3) Continuous 9n + 11 Volatile Only Note 1: “n” indicates the number of times the command operation is to be repeated. 2: This command is useful to determine if a nonvolatile memory write cycle has completed. 3: High Voltage Increment and Decrement commands on select nonvolatile memory locations enable/disable WiperLock Technology and the software Write Protect feature. 2008-2013 Microchip Technology Inc. 7.1 Command Byte The MCP4XXX’s Command Byte has three fields: the Address, the Command Operation, and 2 Data bits, see Figure 7-1. Currently only one of the data bits is defined (D8). The device memory is accessed when the Master sends a proper Command Byte to select the desired operation. The memory location getting accessed is contained in the Command Byte’s AD3:AD0 bits. The action desired is contained in the Command Byte’s C1:C0 bits, see Table 7-1. C1:C0 determines if the desired memory location will be read, written, Incremented (wiper setting +1) or Decremented (wiper setting -1). The Increment and Decrement commands are only valid on the volatile wiper registers, and in High Voltage commands to enable/disable WiperLock Technology and Software Write Protect. If the Address bits and Command bits are not a valid combination, then the MCP4XXX will generate a Not Acknowledge pulse to indicate the invalid combination. The I2C Master device must then force a Start Condition to reset the MCP4XXX’s 2C module. D9 and D8 are the most significant bits for the digital potentiometer’s wiper setting. The 8-bit devices utilize D8 as their MSb while the 7-bit devices utilize D7 (from the data byte) as it’s MSb. COMMAND BYTE A A A A A C C D D A D D D D 1 0 9 8 3 2 1 0 MSbits (Data) MCP4XXX Memory Address Command Operation bits 00 = Write Data 01 = Increment 10 = Decrement 11 = Read Data FIGURE 7-1: Command Byte Format. DS22107B-page 55 MCP454X/456X/464X/466X TABLE 7-2: MEMORY MAP AND THE SUPPORTED COMMANDS Address Command Operation Value 00h 01h 02h 03h 04h (2) 05h (2) Function Volatile Wiper 0 Volatile Wiper 1 Non Volatile Wiper 0 Non Volatile Wiper 1 Volatile TCON Register Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn Increment Wiper — Decrement Wiper — Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn Increment Wiper — Decrement Wiper — Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn — Wiper Lock 0 Disable High Voltage Decrement — Wiper Lock 0 Enable Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn High Voltage Increment — Wiper Lock 1 Disable High Voltage Decrement — Wiper Lock 1 Enable Write Data nn nnnn nnnn (3) nn nnnn nnnn Read Data Write Data Read Data Data EEPROM Note 1: 2: 3: nn nnnn nnnn nn nnnn nnnn (3) Write Data Read Data nn nnnn nnnn nn nnnn nnnn (3) Write Data Read Data 0Fh nn nnnn nnnn nn nnnn nnnn (3) Write Data Read Data 0Eh (2) Data EEPROM nn nnnn nnnn nn nnnn nnnn (3) Write Data Read Data 0Dh (2) Data EEPROM nn nnnn nnnn nn nnnn nnnn (3) Write Data Read Data 0Ch (2) Data EEPROM nn nnnn nnnn nn nnnn nnnn (3) Write Data Read Data 0Bh (2) Data EEPROM nn nnnn nnnn nn nnnn nnnn (3) Write Data Read Data nn nnnn nnnn nn nnnn nnnn (3) Write Data Read Data 0Ah (2) Data EEPROM nn nnnn nnnn (3) Write Data Read Data 09h (2) Data EEPROM nn nnnn nnnn Read Data (3) Status Register 08h (2) Data EEPROM Comment High Voltage Increment 06h (2) Data EEPROM 07h (2) Data EEPROM Data (10-bits) (1) nn nnnn nnnn nn nnnn nnnn (3) nn nnnn nnnn High Voltage Increment — Write Protect Disable High Voltage Decrement — Write Protect Enable The Data Memory is only 9-bits wide, so the MSb is ignored by the device. Increment or Decrement commands are invalid for these addresses. I2C read operation will read 2 bytes, of which the 10-bits of data are contained within. DS22107B-page 56 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 7.2 Data Byte 7.3 Only the Read Command and the Write Command have Data Byte(s). The Write command concatenates the 8-bits of the Data Byte with the one data bit (D8) contained in the Command Byte to form 9-bits of data (D8:D0). The Command Byte format supports up to 9-bits of data so that the 8-bit resistor network can be set to Full-Scale (100h or greater). This allows wiper connections to Terminal A and to Terminal B. The D9 bit is currently unused. Error Condition If the four address bits received (AD3:AD0) and the two command bits received (C1:C0) are a valid combination, the MCP4XXX will Acknowledge the I2C bus. If the address bits and command bits are an invalid combination, then the MCP4XXX will Not Acknowledge the I2C bus. Once an error condition has occurred, any following commands are ignored until the I2C bus is reset with a Start Condition. 7.3.1 ABORTING A TRANSMISSION A Restart or Stop condition in the expected data bit position will abort the current command sequence and data will not be written to the MCP4XXX. TABLE 7-3: COMMANDS Writes Value in EEPROM Operates on Volatile/ Nonvolatile memory High Voltage (VIHH) on HVC pin? Impact on WiperLock or Write Protect Works when Wiper is “locked”? Write Data Yes (1) Both — unlocked (1) No Read Data — Both — unlocked (1) No (1) No No Command Name Increment Wiper — Volatile Only — unlocked Decrement Wiper — Volatile Only — unlocked (1) High Voltage Write Data Yes Both Yes unchanged No High Voltage Read Data — Both Yes unchanged Yes High Voltage Increment Wiper — Volatile Only Yes unchanged No High Voltage Decrement Wiper — Volatile Only Yes unchanged No Modify Write Protect or WiperLock Technology (High Voltage) - Enable — (2) Nonvolatile Only Yes locked/ protected(2) Yes Modify Write Protect or WiperLock Technology (High Voltage) - Disable — (3) Yes unlocked/ unprotected(3) Yes Note 1: 2: 3: (2) Nonvolatile Only (3) This command will only complete, if wiper is “unlocked” (WiperLock Technology is Disabled). If the command is executed using address 02h or 03h, that corresponding wiper is locked or if with address 0Fh, then Write Protect is enabled. If the command is executed using with address 02h or 03h, that corresponding wiper is unlocked or if with address 0Fh, then Write Protect is disabled. 2008-2013 Microchip Technology Inc. DS22107B-page 57 MCP454X/456X/464X/466X 7.4 Write Data Normal and High Voltage The Write Command can be issued to both the Volatile and Nonvolatile memory locations. The format of the command, see Figure 7-2, includes the I2C Control Byte, an A bit, the MCP4XXX Command Byte, an A bit, the MCP4XXX Data Byte, an A bit, and a Stop (or Restart) condition. The MCP4XXX generates the A / A bits. A Write command to a Volatile memory location changes that location after a properly formatted Write Command and the A / A clock have been received. A Write command to a Nonvolatile memory location will only start a write cycle after a properly formatted Write Command have been received and the Stop condition has occurred. Note: 7.4.1 Writes to certain memory locations will be dependant on the state of the WiperLock Technology bits and the Write Protect bit. SINGLE WRITE TO VOLATILE MEMORY For volatile memory locations, data is written to the MCP4XXX after every byte transfer (during the Acknowledge). If a Stop or Restart condition is generated during a data transfer (before the A), the data will not be written to the MCP4XXX. After the A bit, the master can initiate the next sequence with a Stop or Restart condition. 7.4.3 CONTINUOUS WRITES TO VOLATILE MEMORY A continuous write mode of operation is possible when writing to the volatile memory registers (address 00h, 01h, and 04h). This continuous write mode allows writes without a Stop or Restart condition or repeated transmissions of the I2C Control Byte. Figure 7-3 shows the sequence for three continuous writes. The writes do not need to be to the same volatile memory address. The sequence ends with the master sending a STOP or RESTART condition. 7.4.4 CONTINUOUS WRITES TO NONVOLATILE MEMORY If a continuous write is attempted on Nonvolatile memory, the missing Stop condition will cause the command to be an error condition (A). A Start bit is required to reset the command state machine. 7.4.5 THE HIGH VOLTAGE COMMAND (HVC) SIGNAL The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage operational state. High Voltage commands allow the device’s WiperLock Technology and write protect features to be enabled and disabled. The HVC pin has an internal resistor connection to the MCP45XX/46XXs internal VDD signal. Refer to Figure 7-2 for the byte write sequence. 7.4.2 SINGLE WRITE TO NONVOLATILE MEMORY The sequence to write to a single nonvolatile memory location is the same as a single write to volatile memory with the exception that the EEPROM write cycle (twc) is started after a properly formatted command, including the Stop bit, is received. After the Stop condition occurs, the serial interface may immediately be re-enabled by initiating a Start condition. During an EEPROM write cycle, access to volatile memory (addresses 00h, 01h, 04h, and 05h) is allowed when using the appropriate command sequence. Commands that address nonvolatile memory are ignored until the EEPROM write cycle (twc) completes. This allows the Host Controller to operate on the Volatile Wiper registers, the TCON register, and to Read the Status Register. The EEWA bit in the Status register indicates the status of an EEPROM Write Cycle. Once a write command to a Nonvolatile memory location has been received, no other commands should be received before the Stop condition occurs. Figure 7-2 show the waveform for a single write. DS22107B-page 58 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X Write bit Fixed Address S 0 1 Device Memory Address Variable Address 0 1 A2 A1 A0 0 A AD AD AD AD 3 2 1 0 0 0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P WRITE Command Control Byte Write bit Fixed Address S 0 1 Variable Address 0 1 A2 A1 A0 0 A Device Memory Address Write “Data” bits Command AD AD AD AD 3 2 1 0 0 0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A WRITE Command Control Byte AD AD AD AD 3 2 1 0 0 Write Data bits 0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A WRITE Command AD AD AD AD 3 2 1 0 0 Write Data bits STOP bit 0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P WRITE Command FIGURE 7-3: Write Data bits I2C Write Sequence. FIGURE 7-2: Note: Write “Data” bits Command Write Data bits Only functions when writing the volatile wiper registers (AD3:AD0 = 00h, 01h, and 04h) or the TCON register I2C Continuous Volatile Wiper Write. 2008-2013 Microchip Technology Inc. DS22107B-page 59 MCP454X/456X/464X/466X 7.5 Read Data Normal and High Voltage The Read Command can be issued to both the Volatile and Nonvolatile memory locations. The format of the command, see Figure 7-4, includes the Start condition, I2C Control Byte (with R/W bit set to “0”), A bit, MCP4XXX Command Byte, A bit, followed by a Repeated Start bit, I2C Control Byte (with R/W bit set to “1”), and the MCP4XXX transmitting the requested Data High Byte, and A bit, the Data Low Byte, the Master generating the A, and Stop condition. The I2C Control Byte requires the R/W bit equal to a logic one (R/W = 1) to generate a read sequence. The memory location read will be the last address contained in a valid write MCP4XXX Command Byte or address 00h if no write operations have occurred since the device was reset (Power-on Reset or Brown-out Reset). During a write cycle (Write or High Voltage Write to a Nonvolatile memory location) the Read command can only read the Volatile memory locations. By reading the Status Register (04h), the Host Controller can determine when the write cycle has completed (via the state of the EEWA bit). Read operations initially include the same address byte sequence as the write sequence (shown in Figure 6-9). This sequence is followed by another control byte (including the Start condition and Ackowledge) with the R/W bit equal to a logic one (R/W = 1) to indicate a read. The MCP4XXX will then transmit the data contained in the addressed register. This is followed by the master generating an A bit in preparation for more data, or an A bit followed by a Stop. The sequence is ended with the master generating a Stop or Restart condition. 7.5.2 CONTINUOUS READS Continuous reads allows the device’s memory to be read quickly. Continuous reads are possible to all memory locations. If a nonvolatile memory write cycle is occurring, then Read commands may only access the volatile memory locations. Figure 7-6 shows the sequence for three continuous reads. For continuous reads, instead of transmitting a Stop or Restart condition after the data transfer, the master reads the next data byte. The sequence ends with the master Not Acknowledging and then sending a Stop or Restart. 7.5.3 THE HIGH VOLTAGE COMMAND (HVC) SIGNAL The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage mode. High Voltage commands allow the device’s WiperLock Technology and write protect features to be enabled and disabled. The HVC pin has an internal resistor connection to the MCP4XXXs internal VDD signal. 7.5.4 IGNORING AN I2C TRANSMISSION AND “FALLING OFF” THE BUS The MCP4XXX expects to receive entire, valid I2C commands and will assume any command not defined as a valid command is due to a bus corruption and will enter a passive high condition on the SDA signal. All signals will be ignored until the next valid Start condition and Control Byte are received. The internal address pointer is maintained. If this address pointer is for a nonvolatile memory address and the read control byte addresses the device during a Nonvolatile Write Cycle (tWC) the device will respond with an A bit. 7.5.1 SINGLE READ Figure 7-4 show the waveforms for a single read. For single reads the master sends a STOP or RESTART condition after the data byte is sent from the slave. 7.5.1.1 Random Read Figure 7-5 shows the sequence for a Random Reads. Refer to Figure 7-5 for the random byte read sequence. DS22107B-page 60 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X Read bit S 0 1 STOP bit Variable Address Fixed Address Read Data bits 0 1 A2 A1 A0 1 A 0 0 0 0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2 0 0 0 P Read bits Control Byte Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will abort this transfer and release the bus. 2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the Master Device can generate a Stop or Repeated Start condition. 3: The MCP45xx/46xx retains the last “Device Memory Address” that it has received. This is the MCP45XX/46XX does not “corrupt” the “Device Memory Address” after Repeated Start or Stop conditions. 4: The Device Memory Address pointer defaults to 00h on POR and BOR conditions. I2C Read (Last Memory Address Accessed). FIGURE 7-4: Write bit Fixed Address S 0 1 0 Repeated Start bit Device Memory Address Variable Address 1 A2 A1 A0 0 A Command AD AD AD AD 3 2 1 0 1 1 x X A Sr READ Command Control Byte STOP bit Read bit 0 1 0 1 A2 A1 A0 1 A 0 Control Byte Read Data bits 0 0 0 0 0 0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2 P Read bits Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will abort this transfer and release the bus. 2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the Master Device can generate a Stop or Repeated Start condition. 3: The MCP45XX/46XX retains the last “Device Memory Address” that it has received. This is the MCP45XX/46XX does not “corrupt” the “Device Memory Address” after Repeated Start or Stop conditions. FIGURE 7-5: I2C Random Read. 2008-2013 Microchip Technology Inc. DS22107B-page 61 MCP454X/456X/464X/466X Read bit Fixed Address S 0 1 0 Variable Address Read Data bits 1 A2 A1 A0 1 A 0 0 0 0 0 0 0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A1 Read bits Control Byte Read Data bits 0 0 0 0 0 0 0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A1 STOP bit Read Data bits 0 0 0 0 0 0 0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2 P Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will abort this transfer and release the bus. 2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the Master Device can generate a Stop or Repeated Start condition. FIGURE 7-6: DS22107B-page 62 I2C Continuous Reads. 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 7.6 Increment Wiper Normal and High Voltage The advantage of using an Increment Command instead of a read-modify-write series of commands is speed and simplicity. The wiper will transition after each Command Acknowledge when accessing the volatile wiper registers. The Increment Command provide a quick and easy method to modify the potentiometer’s wiper by +1 with minimal overhead. The Increment Command will only function on the volatile wiper setting memory locations 00h and 01h. The Increment Command to Nonvolatile addresses will be ignored and will generate a A. Note: TABLE 7-4: Current Wiper Setting Table 7-2 shows the valid addresses for the Increment Wiper command. Other addresses are invalid. When executing an Increment Command, the volatile wiper setting will be altered from n to n+1 for each Increment Command received. The value will increment up to 100h max on 8-bit devices and 80h on 7-bit devices. If multiple Increment Commands are received after the value has reached 100h (or 80h), the value will not be incremented further. Table 7-4 shows the Increment Command versus the current volatile wiper value. The Increment Command will most commonly be performed on the Volatile Wiper locations until a desired condition is met. The value in the Volatile Wiper register would need to be read using a Read operation in order to write the new setting to the corresponding Nonvolatile wiper memory using a Write operation. The MCP4XXX is responsible for generating the A bits. Write bit S 0 1 0 Variable Address 1 A2 A1 A0 0 Control Byte A Device Memory Address 8-bit Pot 3FFh 081h 3FFh 101h Reserved No (Full-Scale (W = A)) 080h 100h Full-Scale (W = A) 07Fh 041h 0FFh 081 W=N 040h 080h W = N (Mid-Scale) 03Fh 001h 07Fh 001 W=N 000h 000h Zero Scale (W = B) Yes No Yes THE HIGH VOLTAGE COMMAND (HVC) SIGNAL The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage mode. Signals > VIHH (~8.5V) on the HVC/A0 pin puts MCP45XX/46XX devices into High Voltage mode. High Voltage commands allow the device’s WiperLock Technology and write protect features to be enabled and disabled. The command sequence can go from an increment to any other valid command for the specified address. Issuing an increment or decrement to a nonvolatile location will cause an error condition (A will be generated). Fixed Address Increment Command Operates? Wiper (W) Properties 7-bit Pot 7.6.1 Refer to Figure 7-7 for the Increment Command sequence. The sequence is terminated by the Stop condition. So when executing a continuous command string, the Increment command can be followed by any other valid command. This means that writes do not need to be to the same volatile memory address. Note: INCREMENT OPERATION VS. VOLATILE WIPER VALUE Note: There is a required delay after the HVC pin is driven to the VIHH level to the 1st edge of the SCL pin. The HVC pin has an internal resistor connection to the MCP45XX/46XXs internal VDD signal. Command AD AD AD AD 3 2 1 0 0 1 x AD AD AD AD X A 4 3 2 1 0 INCR Command (n+1) 1 x X A P (2) INCR Command (n+2) Note 1: Increment Command (INCR) only functions when accessing the volatile wiper reg- isters (AD3:AD0 = 0h and 1h). 2: This command sequence does not need to terminate (using the Stop bit) and can change to any other desired command sequence (Increment, Read, or Write). FIGURE 7-7: I2C Increment Command Sequence. 2008-2013 Microchip Technology Inc. DS22107B-page 63 MCP454X/456X/464X/466X 7.7 Decrement Wiper Normal and High Voltage The Decrement Command provide a quick and easy method to modify the potentiometer’s wiper by -1 with minimal overhead. The Decrement Command will only function on the volatile wiper setting memory locations 00h and 01h. Decrement Commands to Nonvolatile addresses will be ignored and will generate an A bit. Note: The advantage of using an Decrement Command instead of a read-modify-write series of commands is speed and simplicity. The wiper will transition after each Command Acknowledge when accessing the volatile wiper registers. TABLE 7-5: Current Wiper Setting Table 7-2 shows the valid addresses for the Decrement Wiper command. Other addresses are invalid. When executing a Decrement Command, the volatile wiper setting will be altered from n to n-1 for each Decrement Command received. The value will decrement down to 000h min. If multiple Decrement Commands are received after the value has reached 000h, the value will not be decremented further. Table 7-5 shows the Increment Command versus the current volatile wiper value. The Decrement Command will most commonly be performed on the Volatile Wiper locations until a desired condition is met. The value in the Volatile Wiper register would need to be read using a Read operation in order to write the new setting to the corresponding Nonvolatile wiper memory using a Write operation. The MCP4XXX is responsible for generating the A bits. Refer to Figure 7-8 for the Decrement Command sequence. The sequence is terminated by the Stop condition. So when executing a continuous command string, the Increment command can be followed by any other valid command. This means that writes do not need to be to the same volatile memory address. Note: The command sequence can go from an increment to any other valid command for the specified address. Issuing an increment or decrement to a nonvolatile location will cause an error condition (A will be generated). Write bit Fixed Address S 0 1 0 Variable Address 1 A2 A1 A0 0 A Control Byte DECREMENT OPERATION VS. VOLATILE WIPER VALUE Wiper (W) Properties Decrement Command Operates? 7-bit Pot 8-bit Pot 3FFh 081h 3FFh 101h Reserved No (Full-Scale (W = A)) 080h 100h Full-Scale (W = A) 07Fh 041h 0FFh 081 W=N 040h 080h W = N (Mid-Scale) 03Fh 001h 07Fh 001 W=N 000h 000h Zero Scale (W = B) No 7.7.1 Yes Yes THE HIGH VOLTAGE COMMAND (HVC) SIGNAL The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage mode. Signals > VIHH (~8.5V) on the HVC/A0 pin puts MCP45XX/46XX devices into High Voltage mode. High Voltage commands allow the device’s WiperLock Technology and write protect features to be enabled and disabled. Note: There is a required delay after the HVC pin is driven to the VIHH level to the 1st edge of the SCL pin. The HVC pin has an internal resistor connection to the MCP45XX/46XXs internal VDD signal. Device Memory Address Command AD AD AD AD 3 2 1 0 1 AD AD AD AD 0 X X A 4 3 2 1 1 DECR Command (n-1) 0 X X A P (2) DECR Command (n-2) Note 1: Decrement Command (DECR) only functions when accessing the volatile wiper registers (AD3:AD0 = 0h and 1h). 2: This command sequence does not need to terminate (using the Stop bit) and can change to any other desired command sequence (INCR, Read, or Write). FIGURE 7-8: DS22107B-page 64 I2C Decrement Command Sequence. 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 7.8 7.8.1 Modify Write Protect or WiperLock Technology (High Voltage) Enable and Disable These commands are special cases of the High Voltage Decrement Wiper and the High Voltage Increment Wiper commands to the nonvolatile memory locations 02h, 03h, and 0Fh. This command is used to enable or disable either the software Write Protect, wiper 0 WiperLock Technology, or wiper 1 WiperLock Technology. Table 7-6 shows the memory addresses, the High Voltage command and the result of those commands on the nonvolatile WP, WL0, 0r WL1 bits. TABLE 7-6: Memory Address 00h SINGLE MODIFY (ENABLE OR DISABLE) WRITE PROTECT OR WIPERLOCK TECHNOLOGY (HIGH VOLTAGE) Figure 7-9 (Disable) and Figure 7-10 (Enable) show the formats for a single Modify Write Protect or WiperLock Technology command. A Modify Write Protect or WiperLock Technology Command will only start an EEPROM write cycle (twc) after a properly formatted Command has been received and the Stop condition occurs. During an EEPROM write cycle, only serial commands to Volatile memory (addresses 00h, 01h, 04h, and 05h) are accepted. All other serial commands are ignored until the EEPROM write cycle (twc) completes. This allows the Host Controller to operate on the Volatile Wiper registers and the TCON register, and to Read the Status Register. The EEWA bit in the Status register indicates the status of an EEPROM Write Cycle. ADDRESS MAP TO MODIFY WRITE PROTECT AND WIPERLOCK TECHNOLOGY Commands and Result High Voltage Decrement Wiper High Voltage Increment Wiper Wiper 0 register is incremented Wiper 0 register is incremented 01h Wiper 1 register is decremented Wiper 1 register is incremented 02h WL0 is enabled WL0 is disabled 03h WL1 is enabled WL1 is disabled TCON register not changed TCON register not changed Reserved Reserved WP is enabled WP is disabled 04h (1) 05h - 0Eh (1) 0Fh Note 1: Reserved addresses: Increment or Decrement commands are invalid for these addresses. Write bit Fixed Address S 0 1 0 Device Memory Address Variable Address 1 A2 A1 A0 0 A AD AD AD AD 3 2 1 0 0 I2C Disable Command Sequence. Write bit Fixed Address S 0 1 0 Device Memory Address Variable Address 1 A2 A1 A0 0 A Command (Decrement) AD AD AD AD 3 2 1 0 1 Control Byte FIGURE 7-10: 1 X X A P Disable Command Control Byte FIGURE 7-9: Command (Increment) 0 X X A P Enable Command 2 I C Enable Command Sequence. 2008-2013 Microchip Technology Inc. DS22107B-page 65 MCP454X/456X/464X/466X NOTES: DS22107B-page 66 2008-2013 Microchip Technology Inc. MCP454X/456X/464X/466X 8.0 APPLICATIONS EXAMPLES Nonvolatile digital potentiometers h