MCP45HVX1 7/8-Bit Single, +36V (±18V) Digital POT with I2C™ Serial Interface and Volatile Memory 2014 Microchip Technology Inc. MCP45HVX1 Single Potentiometer TSSOP (ST) VL SCL A1 SDA A0 WLAT NC 14 13 12 11 10 9 8 1 2 3 4 5 6 7 V+ PA0 PW0 PB0 V— DGND SHDN V+ NC (2) NC (2) NC (2) QFN 5x5 (MQ) NC (2) 20 19 18 17 16 2 A1 3 SDA 4 A0 5 P0A 21 EP(1) 6 7 8 13 P0B 12 V- 11 DGND 9 10 NC (2) SCL 15 14 P0W NC (2) 1 NC (2) VL SHDN • High-Voltage Analog Support: - +36V Terminal Voltage Range (DGND = V-) - ±18V Terminal Voltage Range (DGND = V- + 18V) • Wide Operating Voltage: - Analog: 10V to 36V (specified performance) - Digital: 2.7V to 5.5V 1.8V to 5.5V (VL V- + 2.7V) • Single-Resistor Network • Resistor Network Resolution - 7-bit: 127 Resistors (128 Taps) - 8-bit: 255 Resistors (256 Taps) • RAB Resistance Options: - 5 k 10 k - 50 k 100 k • High Terminal/Wiper Current (IW) Support: - 25 mA (for 5 k) - 12.5 mA (for 10 k) - 6.5 mA (for 50 k and 100 k) • Zero-Scale to Full-Scale Wiper Operation • Low Wiper Resistance: 75 (typical) • Low Tempco: - Absolute (Rheostat): 50 ppm typical (0°C to +70°C) - Ratiometric (Potentiometer): 15 ppm typical • I2C Serial Interface: - 100 kHz, 400 kHz, 1.7 MHz, and 3.4 MHz support • Resistor Network Terminal Disconnect Via: - Shutdown Pin (SHDN) - Terminal Control (TCON) Register • Write Latch (WLAT) Pin to Control Update of Volatile Wiper Register (such as Zero Crossing) • Power-On Reset/Brown-Out Reset for Both: - Digital supply (VL/DGND); 1.5V typical - Analog supply (V+/V-); 3.5V typical • Serial Interface Inactive Current (3 µA typical) • 500 kHz Typical Bandwidth (-4 dB) Operation (5.0 k Device) • Extended Temperature Range (-40°C to +125°C) • Package Types: TSSOP-14 and QFN-20 (5x5) Package Types (Top View) WLAT Features: Note 1: Exposed Pad (EP) 2: NC = Not Internally Connected Description: The MCP45HVX1 family of devices have dual power rails (analog and digital). The analog power rail allows high voltage on the resistor network terminal pins. The analog voltage range is determined by the V+ and V– voltages. The maximum analog voltage is +36V, while the operating analog output minimum specifications are specified from either 10V or 20V. As the analog supply voltage becomes smaller, the analog switch resistances increase, which affect certain performance specifications. The system can be implemented as dual rail (±18V) relative to the digital logic ground (DGND). The device also has a Write Latch (WLAT) function, which will inhibit the volatile Wiper register from being updated (latched) with the received data, until the WLAT pin is Low. This allows the application to specify a condition where the volatile Wiper register is updated (such as zero crossing). DS20005304A-page 1 MCP45HVX1 Device Block Diagram V+ V– VL DGND SCL SDA A0 A1 Power-Up/ Brown-Out Control (Digital) Power-Up/ Brown-Out Control (Analog) I2C™ Serial Interface Module and Control Logic P0A Resistor Network 0 (Pot 0) WLAT SHDN P0W Wiper 0 and TCON Register Memory (2x8) Wiper0 (V) P0B TCON Resistance (Typical) Number of: RAB Options Wiper (k) RW () Specified Operating Range VL (2) 3Fh 5.0, 10.0, 50.0, 100.0 75 127 128 1.8V to 5.5V 10V (4) to 36V I2C 7Fh 5.0, 10.0, 50.0, 100.0 75 255 256 1.8V to 5.5V 10V (4) to 36V MCP41HV31(5) 1 Potentiometer SPI 3Fh 5.0, 10.0, 50.0, 100.0 75 127 128 1.8V to 5.5V 10V (4) to 36V MCP41HV51(5) 1 Potentiometer (5) SPI 7Fh 5.0, 10.0, 50.0, 100.0 75 255 256 1.8V to 5.5V 10V (4) to 36V MCP45HV31 1 Potentiometer (1) I2C™ MCP45HV51 1 Potentiometer (1) Note 1: 2: 3: 4: 5: RS Taps POR Wiper Setting Wiper Configuration Control Interface Device # of POTs Device Features V+ (3) Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor). This is relative to the DGND signal. There is a separate requirement for the V+/V- voltages. VL V- + 2.7V. Relative to V-, the VL and DGND signals must be between (inclusive) V- and V+. Analog operation will continue while the V+ voltage is above the device’s analog Power-On Reset (POR)/ Brown-out Reset (BOR) voltage. Operational characteristics may exceed specified limits while the V+ voltage is below the specified minimum voltage. For additional information on these devices, refer to DS20005207. DS20005304A-page 2 2014 Microchip Technology Inc. MCP45HVX1 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Voltage on V- with respect to DGND ......................................................................................... DGND + 0.6V to -40.0V Voltage on V+ with respect to DGND ........................................................................................... DGND - 0.3V to 40.0V Voltage on V+ with respect to V- .................................................................................................. DGND - 0.3V to 40.0V Voltage on VL with respect to V+ ............................................................................................................ -0.6V to -40.0V Voltage on VL with respect to V- ............................................................................................................. -0.6V to +40.0V Voltage on VL with respect to DGND ....................................................................................................... -0.6V to +7.0V Voltage on SCL, SDA, A0, A1, WLAT, and SHDN with respect to DGND .......................................... -0.6V to VL + 0.6V Voltage on all other pins (PxA, PxW, and PxB) with respect to V- ......................................................-0.3V to V+ + 0.3V Input clamp current, IIK (VI < 0, VI > VL, VI > VPP on HV pins) ............................................................................ ±20 mA Output clamp current, IOK (VO < 0 or VO > VL) ................................................................................................... ±20 mA Maximum current out of DGND pin ...................................................................................................................... 100 mA Maximum current into VL pin................................................................................................................................ 100 mA Maximum current out of V- pin ............................................................................................................................. 100 mA Maximum current into V+ pin ................................................................................................................................100 mA Maximum current into PXA, PXW, and PXB pins (Continuous) RAB = 5 k ............................................................................................................................. ±25 mA RAB = 10 k ........................................................................................................................ ±12.5 mA RAB = 50 k .......................................................................................................................... ±6.5 mA RAB = 100 k ........................................................................................................................ ±6.5 mA Maximum current into PXA, PXW, and PXB pins (Pulsed) FPULSE > 10 kHz ......................................................................................................... (Max IContinuous) / (Duty Cycle) FPULSE 10 kHz ...................................................................................................... (Max IContinuous) / (Duty Cycle) Maximum output current sunk by any Output pin .................................................................................................. 25 mA Maximum output current sourced by any Output pin ............................................................................................ 25 mA Package Power Dissipation (TA = + 50°C, TJ = +150°C) TSSOP-14 ............................................................................................................................................. 1000 mW QFN-20 (5 x 5) ...................................................................................................................................... 2800 mW Soldering temperature of leads (10 seconds) ..................................................................................................... +300°C ESD protection on all pins Human Body Model (HBM) ...................................................................................................................... ±5 kV Machine Model (MM) ±400V Maximum Junction Temperature (TJ) ..................................................................................................................... 150°C Storage temperature ............................................................................................................................. -65°C to +150°C Ambient temperature with power applied .............................................................................................. -40°C to +125°C † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2014 Microchip Technology Inc. DS20005304A-page 3 MCP45HVX1 AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) All parameters apply across the specified operating ranges unless noted. V+ = 10V to 36V (referenced to V-); V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V), VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VL = 5.5V, TA = +25°C. DC Characteristics Parameters Sym. Digital Positive Supply Voltage (VL) VL Analog Positive Supply Voltage (V+) V+ VDGND Min. Typ. Max. Units Conditions 2.7 — 5.5 V With respect to DGND (Note 4) 1.8 — 5.5 V VL V- + 2.7V (Note 1, Note 4) — — 0 V With respect to V+ VL (16) — 36.0 V With respect to V- (Note 4) V- — V+ - VL V With respect to V- (Note 4, Note 5) V- -36.0 + VL — 0 V With respect to DGND and with VL = 1.8V VRN — — 36.0 V Delta voltage between V+ and V- (Note 4) VL Start Voltage to ensure Wiper Reset VDPOR — — 1.8 V With respect to DGND, V+ > 6.0V RAM retention voltage (VRAM) < VDBOR V+ Voltage to ensure Wiper Reset VAPOR — — 6.0 V With respect to V-, VL = 0V RAM retention voltage (VRAM) < VBOR Digital to Analog Level Shifter Operational Voltage VLS — — 2.3 V VL to V- voltage. DGND = V- Power Rail Voltages during Power-Up (Note 1) VLPOR — — 5.5 V Digital Powers (VL/DGND) up 1st: V+ and V- floating or as V+/V- powers-up (V+ must be to DGND) (Note 18) V+POR — — 36 V Analog Powers (V+/V-) up 1st: VL and DGND floating or as VL/DGND powers-up (DGND must be between V- and V+) (Note 18) Digital Ground Voltage (DGND) Analog Negative Supply Voltage (V-) Resistor Network Supply Voltage VL Rise Rate to ensure Power-On Reset VLRR (Note 6) V/ms With respect to DGND Note 1: This specification by design. Note 4: V+ voltage is dependent on V- voltage. The maximum delta voltage between V+ and V- is 36V. The digital logic DGND potential can be anywhere between V+ and V-, the VL potential must be DGND and V+. Note 5: Minimum value determined by maximum V- to V+ potential equals 36V and minimum VL = 1.8V for operation. So 36V - 1.8V = 34.2V. Note 6: POR/BOR is not rate dependent. Note 16: For specified analog performance, V+ must be 20V or greater (unless otherwise noted). Note 18: During the power-up sequence, to ensure expected analog POR operation, the two power systems (analog and digital) should have a common reference to ensure that the driven DGND voltage is not at a higher potential than the driven V+ voltage. DS20005304A-page 4 2014 Microchip Technology Inc. MCP45HVX1 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) All parameters apply across the specified operating ranges unless noted. V+ = 10V to 36V (referenced to V-); V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V), VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VL = 5.5V, TA = +25°C. DC Characteristics Parameters Sym. Min. Typ. Max. Units Delay after device exits the Reset state (VL > VBOR) TBORD — 10 20 µs Supply Current (Note 7) IDDD — 45 650 µA Serial Interface Active, Write all 0’s to Volatile Wiper 0 (address 0h) VL = 5.5V, FSCL = 3.4 MHz, V- = DGND — 4 7 µA Serial Interface Inactive, VL = 5.5V, SCL = VIH, Wiper = 0, V- = DGND IDDA — — 5 µA Current V+ to V-, PxA = PxB = PxW, DGND = V- +(V+/2) RAB 4.0 5 6.0 k -502 devices, V+/V- = 10V to 36V 8.0 10 12.0 k -103 devices, V+/V- = 10V to 36V Resistance (± 20%)(Note 8) RAB Current Resolution Step Resistance (see Appendix B.4) Conditions 40.0 50 60.0 k -503 devices, V+/V- = 10V to 36V 80.0 100 120.0 k -104 devices, V+/V- = 10V to 36V IAB — — 9.00 mA — — 4.50 mA — — 0.90 mA -502 devices 36V / RAB(MIN), -103 devices V- = -18V, V+ = +18V, (Note 9) -503 devices — — 0.45 mA -104 devices 256 Taps 8-bit No Missing Codes 128 Taps 7-bit No Missing Codes N RS — RAB/(255) — 8-bit Note 1 — RAB/(127) — 7-bit Note 1 Note 1: This specification by design. Note 7: Supply current (IDDD and IDDA) is independent of current through the resistor network. Note 8: Resistance (RAB) is defined as the resistance between Terminal A to Terminal B. Note 9: Ensured by the RAB specification and Ohm’s Law. 2014 Microchip Technology Inc. DS20005304A-page 5 MCP45HVX1 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) All parameters apply across the specified operating ranges unless noted. V+ = 10V to 36V (referenced to V-); V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V), VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VL = 5.5V, TA = +25°C. DC Characteristics Parameters Wiper Resistance (see Appendix B.5) Sym. Min. Typ. Max. Units RW — 75 170 IW = 1 mA V+ = +18V, V- = -18V, code = 00h, PxA = floating, PxB = V-. — 145 200 IW = 1 mA V+ = +5.0V, V- = -5.0V, code = 00h, PxA = floating, PxB = V-. (Note 2) Nominal Resistance Tempco (see Appendix B.23) RAB/T Ratiometeric Tempco (see Appendix B.22) Conditions — 50 — ppm/°C TA = -40°C to +85°C — 100 — ppm/°C TA = -40°C to +125°C VBW/T — 15 — ppm/°C Code = Mid scale (7Fh or 3Fh) Resistor Terminal Input VA,VW,VB Voltage Range (Terminals A, B and W) V- — V+ V Current through Terminals (A, B, and Wiper) (Note 1) — — 25 mA — — 12.5 mA — — 6.5 mA — — 6.5 mA -503 devices IBW(W ≠ ZS) and IAW(W ≠ FS) -104 devices IBW(W ≠ ZS) and IAW(W ≠ FS) — — 36 mA IBW(W = ZS), or IAW(W = FS) — 5 — nA A = W = B = V- Leakage current into A, W or B IT, IW ITL Note 1, Note 11 -502 devices IBW(W ≠ ZS) and IAW(W ≠ FS) -103 devices IBW(W ≠ ZS) and IAW(W ≠ FS) Note 1: This specification by design. Note 2: This parameter is not tested, but specified by characterization. Note 11: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. DS20005304A-page 6 2014 Microchip Technology Inc. MCP45HVX1 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) All parameters apply across the specified operating ranges unless noted. V+ = 10V to 36V (referenced to V-); V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V), VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VL = 5.5V, TA = +25°C. DC Characteristics Parameters Full Scale Error (Potentiometer) (8-bit code = FFh, 7-bit code = 7Fh) (Note 10, Note 17) (VA = V+, VB = V- ) (see Appendix B.10) Note 2: Sym. Min. Typ. Max. Units VWFSE -10.5 — — LSb -8.5 — — LSb -14.0 — — LSb -5.5 — — LSb -4.5 — — LSb -7.5 — — LSb -4.5 — — LSb -6.0 — — LSb -2.65 — — LSb -2.25 — — LSb -3.5 — — LSb -1.0 — — LSb -1.4 — — LSb -1.0 — — LSb -1.2 — — LSb -0.7 — — LSb -0.95 — — LSb -0.85 — — LSb -0.975 — — LSb Conditions VAB = 20V to 36V 5 k 8-bit VAB = 20V to 36V –40°C TA +85°C (Note 2) VAB = 10V to 36V VAB = 20V to 36V 7-bit VAB = 20V to 36V –40°C TA +85°C (Note 2) VAB = 10V to 36V 10 k 8-bit VAB = 20V to 36V VAB = 10V to 36V VAB = 20V to 36V 7-bit 50 k 8-bit 7-bit 100 k 8-bit 7-bit VAB = 20V to 36V –40°C TA +85°C (Note 2) VAB = 10V to 36V VAB = 20V to 36V VAB = 10V to 36V VAB = 20V to 36V VAB = 10V to 36V VAB = 20V to 36V VAB = 10V to 36V VAB = 20V to 36V VAB = 10V to 36V This parameter is not tested, but specified by characterization. Note 10: Measured at VW with VA = V+ and VB = V-. Note 17: Analog switch leakage affects this specification. Higher temperatures increase the switch leakage. 2014 Microchip Technology Inc. DS20005304A-page 7 MCP45HVX1 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) All parameters apply across the specified operating ranges unless noted. V+ = 10V to 36V (referenced to V-); V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V), VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VL = 5.5V, TA = +25°C. DC Characteristics Parameters Zero Scale Error (Potentiometer) (8-bit code = 00h, 7-bit code = 00h) (Note 10, Note 17) (VA = V+, VB = V- ) (see Appendix B.11) Note 2: Sym. Min. Typ. Max. Units VWZSE — — +9.5 LSb — — +8.5 LSb — — +14.5 LSb — — +4.5 LSb — — +7.0 LSb — — +4.25 LSb — — +6.5 LSb — — +2.125 LSb — — +3.25 LSb — — +0.9 LSb — — +1.3 LSb — — +0.5 LSb — — +0.7 LSb — — +0.6 LSb — — +0.95 LSb — — +0.3 LSb — — +0.475 LSb Conditions VAB = 20V to 36V 5 k 8-bit 7-bit 10 k 8-bit 7-bit 50 k 8-bit 7-bit 100 k 8-bit 7-bit VAB = 20V to 36V –40°C TA +85°C (Note 2) VAB = 10V to 36V VAB = 20V to 36V VAB = 10V to 36V VAB = 20V to 36V VAB = 10V to 36V VAB = 20V to 36V VAB = 10V to 36V VAB = 20V to 36V VAB = 10V to 36V VAB = 20V to 36V VAB = 10V to 36V VAB = 20V to 36V VAB = 10V to 36V VAB = 20V to 36V VAB = 10V to 36V This parameter is not tested, but specified by characterization. Note 10: Measured at VW with VA = V+ and VB = V-. Note 17: Analog switch leakage affects this specification. Higher temperatures increase the switch leakage. DS20005304A-page 8 2014 Microchip Technology Inc. MCP45HVX1 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) All parameters apply across the specified operating ranges unless noted. V+ = 10V to 36V (referenced to V-); V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V), VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VL = 5.5V, TA = +25°C. DC Characteristics Parameters Sym. Potentiometer Integral Nonlinearity (Note 10, Note 17) (see Appendix B.12) P-INL Potentiometer Differential Nonlinearity (Note 10, Note 17) (see Appendix B.13) Note 2: P-DNL Min. Typ. Max. Units -1 ±0.5 +1 LSb -0.5 ±0.25 +0.5 LSb Conditions 5 k VAB = 10V to 36V VAB = 10V to 36V 8-bit VAB = 10V to 36V 7-bit VAB = 10V to 36V 8-bit VAB = 10V to 36V -1 ±0.5 +1 LSb -0.5 ±0.25 +0.5 LSb -1.1 ±0.5 +1.1 LSb -1 ±0.5 +1 LSb VAB = 20V to 36V, (Note 2) -1 ±0.5 +1 LSb -0.6 ±0.25 +0.6 LSb 7-bit VAB = 10V to 36V, –40°C TA +85°C (Note 2) VAB = 10V to 36V -1.85 ±0.5 +1.85 LSb 8-bit VAB = 10V to 36V -1.2 ±0.5 +1.2 LSb VAB = 20V to 36V, (Note 2) -1 ±0.5 +1 LSb 7-bit VAB = 10V to 36V, –40°C TA +85°C (Note 2) VAB = 10V to 36V 8-bit VAB = 10V to 36V 7-bit VAB = 20V to 36V (Note 2) VAB = 10V to 36V 8-bit VAB = 10V to 36V 7-bit VAB = 10V to 36V -1 ±0.5 +1 LSb -0.7 ±0.25 +0.7 LSb -0.5 ±0.25 +0.5 LSb -0.25 ±0.125 +0.25 LSb -0.375 ±0.125 +0.375 LSb -0.25 ±0.1 +0.25 LSb -0.25 ±0.125 +0.25 LSb -0.125 ±0.1 +0.125 LSb -0.25 ±0.125 +0.25 LSb -0.125 ±0.1 +0.125 LSb 10 k 8-bit 7-bit 50 k 100 k 5 k 10 k 50 k 100 k 8-bit VAB = 10V to 36V 7-bit VAB = 10V to 36V 8-bit VAB = 10V to 36V 7-bit VAB = 10V to 36V This parameter is not tested, but specified by characterization. Note 10: Measured at VW with VA = V+ and VB = V-. Note 17: Analog switch leakage affects this specification. Higher temperatures increase the switch leakage. 2014 Microchip Technology Inc. DS20005304A-page 9 MCP45HVX1 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) All parameters apply across the specified operating ranges unless noted. V+ = 10V to 36V (referenced to V-); V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V), VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VL = 5.5V, TA = +25°C. DC Characteristics Parameters Bandwidth -3 dB (load = 30 pF) VW Settling Time (VA = 10V, VB = 0V, ±1LSb error band, CL = 50 pF) (see Appendix B.17) DS20005304A-page 10 Sym. BW tS Min. Typ. Max. Units — 480 — kHz — 480 — kHz — 240 — kHz — 240 — kHz Conditions 5 k 10 k 50 k 8-bit Code = 7Fh 7-bit Code = 3Fh 8-bit Code = 7Fh 7-bit Code = 3Fh — 48 — kHz — 48 — kHz — 24 — kHz — 24 — kHz — 1 — µs 5 k Code = 00h -> FFh (7Fh); FFh (7Fh) -> 00h — 1 — µs 10 k Code = 00h -> FFh (7Fh); FFh (7Fh) -> 00h — 2.5 — µs 50 k Code = 00h -> FFh (7Fh); FFh (7Fh) -> 00h — 5 — µs 100 k Code = 00h -> FFh (7Fh); FFh (7Fh) -> 00h 100 k 8-bit Code = 7Fh 7-bit Code = 3Fh 8-bit Code = 7Fh 7-bit Code = 3Fh 2014 Microchip Technology Inc. MCP45HVX1 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) All parameters apply across the specified operating ranges unless noted. V+ = 10V to 36V (referenced to V-); V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V), VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VL = 5.5V, TA = +25°C. DC Characteristics Parameters Sym. Min. Typ. Max. Units Rheostat Integral Nonlinearity (Note 12, Note 13, Note 14, Note 17) (see Appendix B.5) R-INL -2.0. — +2.0 LSb -2.5 — +2.5 LSb Note 2: Conditions 5 k 8-bit IW = 6.0 mA, (V+ - V-) = 36V (Note 2) IW = 3.3 mA, (V+ - V-) = 20V (Note 2) -4.5 — +4.5 LSb -1.0 — +1.0 LSb -1.5 — +1.5 LSb IW = 3.3 mA, (V+ - V-) = 20V (Note 2) -2.0 — +2.0 LSb IW = 1.7 mA, (V+ - V-) = 10V -1.2 — +1.2 LSb -1.75 — +1.75 LSb IW = 1.7 mA, (V+ - V-) = 10V 7-bit 10 k 8-bit IW = 6.0 mA, (V+ - V-) = 36V (Note 2) IW = 3.0 mA, (V+ - V-) = 36V (Note 2) IW = 1.7 mA, (V+ - V-) = 20V (Note 2) -2.0 — +2.0 LSb -0.6 — +0.6 LSb -0.8 — +0.8 LSb IW = 1.7 mA, (V+ - V-) = 20V (Note 2) -1.1 — +1.1 LSb IW = 830 µA, (V+ - V-) = 10V -1.0 — +1.0 LSb -1.0 — +1.0 LSb IW = 830 µA, (V+ - V-) = 10V 7-bit 50 k 8-bit IW = 3.0 mA, (V+ - V-) = 36V (Note 2) IW = 600 µA, (V+ - V-) = 36V (Note 2) IW = 330 µA, (V+ - V-) = 20V (Note 2) -1.2 — +1.2 LSb -0.5 — +0.5 LSb -0.5 — +0.5 LSb IW = 330 µA, (V+ - V-) = 20V (Note 2) -0.6 — +0.6 LSb IW = 170 µA, (V+ - V-) = 10V -1.0 — +1.0 LSb -1.0 — +1.0 LSb IW = 170 µA, (V+ - V-) = 10V 7-bit 100 k 8-bit IW = 600 µA, (V+ - V-) = 36V (Note 2) IW = 300 µA, (V+ - V-) = 36V (Note 2) IW = 170 µA, (V+ - V-) = 20V(Note 2) -1.2 — +1.2 LSb -0.5 — +0.5 LSb IW = 83 µA, (V+ - V-) = 10V -0.5 — +0.5 LSb IW = 170 µA, (V+ - V-) = 20V (Note 2) -0.6 — +0.6 LSb IW = 83 µA, (V+ - V-) = 10V 7-bit IW = 300 µA, (V+ - V-) = 36V (Note 2) This parameter is not tested, but specified by characterization. Note 12: Nonlinearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. Note 13: Externally connected to a Rheostat configuration (RBW), and then tested. Note 14: Wiper current (IW) condition determined by RAB(max) and Voltage Condition, the delta voltage between V+ and V- (voltages are 36V, 20V, and 10V). Note 17: Analog switch leakage affects this specification. Higher temperatures increase the switch leakage. 2014 Microchip Technology Inc. DS20005304A-page 11 MCP45HVX1 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) All parameters apply across the specified operating ranges unless noted. V+ = 10V to 36V (referenced to V-); V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V), VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VL = 5.5V, TA = +25°C. DC Characteristics Parameters Sym. Rheostat R-DNL Differential Nonlinearity (Note 12, Note 13, Note 14, Note 17) (see Appendix B.5) Note 2: Min. Typ. Max. Units -0.5 — +0.5 LSb -0.5 — +0.5 LSb Conditions 5 k 8-bit IW = 6.0 mA, (V+ - V-) = 36V (Note 2) IW = 3.3 mA, (V+ - V-) = 20V (Note 2) -0.8 — +0.8 LSb -0.25 — +0.25 LSb IW = 1.7 mA, (V+ - V-) = 10V -0.25 — +0.25 LSb IW = 3.3 mA, (V+ - V-) = 20V (Note 2) -0.4 — +0.4 LSb IW = 1.7 mA, (V+ - V-) = 10V -0.5 — +0.5 LSb -0.5 — +0.5 LSb 7-bit 10 k 8-bit IW = 6.0 mA, (V+ - V-) = 36V (Note 2) IW = 3.0 mA, (V+ - V-) = 36V (Note 2) IW = 1.7 mA, (V+ - V-) = 20V (Note 2) -0.5 — +0.5 LSb -0.25 — +0.25 LSb IW = 830 µA, (V+ - V-) = 10V -0.25 — +0.25 LSb IW = 1.7 mA, (V+ - V-) = 20V (Note 2) -0.25 — +0.25 LSb IW = 830 µA, (V+ - V-) = 10V -0.5 — +0.5 LSb -0.5 — +0.5 LSb 7-bit 50 k 8-bit IW = 3.0 mA, (V+ - V-) = 36V (Note 2) IW = 600 µA, (V+ - V-) = 36V (Note 2) IW = 330 µA, (V+ - V-) = 20V (Note 2) -0.5 — +0.5 LSb -0.25 — +0.25 LSb IW = 170 µA, (V+ - V-) = 10V -0.25 — +0.25 LSb IW = 330 µA, (V+ - V-) = 20V (Note 2) -0.25 — +0.25 LSb IW = 170 µA, (V+ - V-) = 10V -0.5 — +0.5 LSb -0.5 — +0.5 LSb 7-bit 100 k 8-bit IW = 600 µA, (V+ - V-) = 36V (Note 2) IW = 300 µA, (V+ - V-) = 36V (Note 2) IW = 170 µA, (V+ - V-) = 20V (Note 2) -0.5 — +0.5 LSb -0.25 — +0.25 LSb IW = 83 µA, (V+ - V-) = 10V -0.25 — +0.25 LSb IW = 170 µA, (V+ - V-) = 20V (Note 2) -0.25 — +0.25 LSb IW = 83 µA, (V+ - V-) = 10V 7-bit IW = 300 µA, (V+ - V-) = 36V (Note 2) This parameter is not tested, but specified by characterization. Note 12: Nonlinearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. Note 13: Externally connected to a Rheostat configuration (RBW), and then tested. Note 14: Wiper current (IW) condition determined by RAB(max) and Voltage Condition, the delta voltage between V+ and V- (voltages are 36V, 20V, and 10V). Note 17: Analog switch leakage affects this specification. Higher temperatures increase the switch leakage. DS20005304A-page 12 2014 Microchip Technology Inc. MCP45HVX1 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) All parameters apply across the specified operating ranges unless noted. V+ = 10V to 36V (referenced to V-); V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V), VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VL = 5.5V, TA = +25°C. DC Characteristics Parameters Sym. Min. Typ. Max. Units Capacitance (PA) CA — 75 — pF Measured to V-, f =1 MHz, Wiper code = Mid Scale Capacitance (Pw) CW — 120 — pF Measured to V-, f =1 MHz, Wiper code = Mid Scale Capacitance (PB) CB — 75 — pF Measured to V-, f =1 MHz, Wiper code = Mid Scale Common-Mode Leakage ICM — 5 — nA VA = VB = VW CIN, COUT — 10 — pF fC = 400 kHz 1.8V VL 5.5V Digital Interface Pin Capacitance Conditions Digital Inputs/Outputs (SDA, SCL, A0, A1, SHDN, WLAT) Schmitt Trigger HighInput Threshold VIH 0.7 VL — VL + 0.3V V Schmitt Trigger LowInput Threshold VIL DGND - 0.5V — 0.3 VL V Hysteresis of Schmitt Trigger Inputs VHYS — 0.1 VL — V Output Low Voltage (SDA) VOL DGND — 0.2 VL V VL = 5.5V, IOL = 5 mA 0.2 VL V VL = 1.8V, IOL = 800 µA Input Leakage Current IIL 1 uA VIN = VL and VIN = DGND DGND 2014 Microchip Technology Inc. -1 — DS20005304A-page 13 MCP45HVX1 AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) All parameters apply across the specified operating ranges unless noted. V+ = 10V to 36V (referenced to V-); V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V), VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VL = 5.5V, TA = +25°C. DC Characteristics Parameters Sym. Min. Typ. Max. Units Conditions N 0h — FFh hex 8-bit — 7Fh hex 7-bit hex 8-bit hex 7-bit RAM (Wiper, TCON) Value Wiper Value Range 0h Wiper POR/BOR Value 7Fh NPOR/BOR 3Fh TCON Value Range TCON POR/BOR Value N 0h — FFh FF NTCON hex hex All Terminals connected Power Requirements Power Supply Sensitivity (see Appendix B.20) Power Dissipation PSS PDISS — 0.0015 0.0035 %/% 8-bit VL = 2.7V to 5.5V, V+ = 18V, V- = -18V, Code = 7Fh — 0.0015 0.0035 %/% 7-bit VL = 2.7V to 5.5V, V+ = 18V, V- = -18V, Code = 3Fh VL = 5.5V, V+ = 18V, V- = -18V (Note 15) — 260 — mW 5 k — 130 — mW 10 k — 26 — mW 50 k — 13 — mW 100 k Note 15: PDISS = I * V, or ( (IDDD * 5.5V) + (IDDA * 36V) + (IAB * 36V) ). DS20005304A-page 14 2014 Microchip Technology Inc. MCP45HVX1 DC Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. This specification by design. This parameter is not tested, but specified by characterization. See Absolute Maximum Ratings. V+ voltage is dependent on V- voltage. The maximum delta voltage between V+ and V- is 36V. The digital logic DGND potential can be anywhere between V+ and V-, the VL potential must be DGND and V+. Minimum value determined by maximum V- to V+ potential equals 36V and minimum VL = 1.8V for operation. So 36V - 1.8V = 34.2V. POR/BOR is not rate dependent. Supply current (IDDD and IDDA) is independent of current through the resistor network. Resistance (RAB) is defined as the resistance between Terminal A to Terminal B. Ensured by the RAB specification and Ohm’s Law. Measured at VW with VA = V+ and VB = V-. Resistor terminals A, W and B’s polarity with respect to each other is not restricted. Nonlinearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. Externally connected to a Rheostat configuration (RBW), and then tested. Wiper current (IW) condition determined by RAB(max) and Voltage Condition, the delta voltage between V+ and V(voltages are 36V, 20V, and 10V). PDISS = I * V, or ( (IDDD * 5.5V) + (IDDA * 36V) + (IAB * 36V) ). For specified analog performance, V+ must be 20V or greater (unless otherwise noted). Analog switch leakage affects this specification. Higher temperatures increase the switch leakage. During the power-up sequence, to ensure expected analog POR operation, the two power systems (analog and digital) should have a common reference to ensure that the driven DGND voltage is not at a higher potential than the driven V+ voltage. 2014 Microchip Technology Inc. DS20005304A-page 15 MCP45HVX1 1.1 Timing Waveforms and Requirements ± 1 LSb W New Value Old Value FIGURE 1-1: TABLE 1-1: Settling Time Waveforms. WIPER SETTLING TIMING Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C TA +125°C (extended) Timing Characteristics Parameters Sym. VW Settling Time (VA = 10V, VB = 0V, ±1LSb error band, CL = 50 pF ) tS DS20005304A-page 16 All parameters apply across the specified operating ranges unless noted. V+ = 10V to 36V (referenced to V-); V+ = +5V to +18V and V- = -5.0V to -18V (referenced to DGND -> ±5V to ±18V), VL = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VL = 5.5V, TA = +25°C. Min. Typ. Max. Units Conditions — 1 — µs 5 k Code = 00h -> FFh (7Fh); FFh (7Fh) -> 00h — 1 — µs 10 k Code = 00h -> FFh (7Fh); FFh (7Fh) -> 00h — 2.5 — µs 50 k Code = 00h -> FFh (7Fh); FFh (7Fh) -> 00h — 5 — µs 100 k Code = 00h -> FFh (7Fh); FFh (7Fh) -> 00h 2014 Microchip Technology Inc. MCP45HVX1 SCL 91 90 93 92 SDA START Condition 94 95 96 ACK/ACK Pulse STOP Condition 96 WLAT I2C Bus Start/Stop Bits Timing Waveforms. FIGURE 1-2: TABLE 1-2: I2C BUS START/STOP BITS AND WLAT REQUIREMENTS I2C™ AC Characteristics Param. No. Symbol Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C TA +125C (Extended) 2.7V VL 5.5V; DGND = V- (Note 1) Characteristic FSCL D102 Cb Bus capacitive loading Standard mode Fast mode High Speed 1.7 High Speed 3.4 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode 100 kHz mode 400 kHz mode 1.7 MHz mode 3.4 MHz mode Min. Max. Units Conditions 0 0 0 0 — — — — 4700 600 160 160 4000 600 160 160 4000 600 160 160 4000 600 160 160 100 400 1.7 3.4 400 400 400 100 — — — — — — — — — — — — — — — — kHz kHz MHz MHz pF pF pF pF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Cb = 400 pF, 1.8V VL 5.5V Cb = 400 pF, 2.7V VL 5.5V Cb = 400 pF, 4.5V VL 5.5V Cb = 100 pF, 4.5V VL 5.5V 90 TSU:STA Start condition Setup time 91 THD:STA Start condition Hold time 92 TSU:STO Stop condition Setup time 93 THD:STO Stop condition Hold time 94 TWLSU WLAT ↑ to SCL↑ (write data ACK bit) Setup time 10 — ns Write Data delayed, Note 9 95 TWLHD SCL ↑ to WLAT↑ (write data ACK bit) Hold time 250 — ns Write Data delayed, Note 9 96 TWLATL WLAT High or Low Time 2 — µs Only relevant for repeated Start condition After this period the first clock pulse is generated Note 1: Serial Interface has equal performance when DGND V- + 0.9V. Note 9: The transition of the WLAT signal between 10 ns before the rising edge (Spec 94) and 200 ns after the rising edge (Spec 95) of the SCL signal is indeterminant if the Write Data is delayed or not. 2014 Microchip Technology Inc. DS20005304A-page 17 MCP45HVX1 103 102 100 101 SCL 90 106 91 92 107 SDA In 110 109 109 SDA Out I2C Bus Timing Waveforms. FIGURE 1-3: TABLE 1-3: I2C BUS REQUIREMENTS (SLAVE MODE) I2C™ AC Characteristics Param. No. 100 101 102A (6) 102B (6) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C TA +125C (Extended) 2.7V VL 5.5V; DGND = V- (Note 1) Symbol Characteristic THIGH TLOW TRSCL TRSDA Clock high time Clock low time SCL rise time SDA rise time Min. Max. Units 100 kHz mode 4000 — ns 1.8V-5.5V 400 kHz mode 600 — ns 2.7V-5.5V 1.7 MHz mode 120 — ns 4.5V-5.5V 3.4 MHz mode 60 — ns 4.5V-5.5V 100 kHz mode 4700 — ns 1.8V-5.5V 400 kHz mode 1300 — ns 2.7V-5.5V 1.7 MHz mode 320 — ns 4.5V-5.5V 3.4 MHz mode 160 — ns 4.5V-5.5V Cb is specified to be from 10 to 400 pF (100 pF maximum for 3.4 MHz mode) 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 80 ns 1.7 MHz mode 20 160 ns After a Repeated Start condition or an Acknowledge bit 3.4 MHz mode 10 40 ns 3.4 MHz mode 10 80 ns After a Repeated Start condition or an Acknowledge bit 100 kHz mode — 1000 ns Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode) 400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 160 ns 3.4 MHz mode 10 80 ns Note 1: Serial Interface has equal performance when DGND V- + 0.9V. Note 6: Not tested. DS20005304A-page 18 Conditions 2014 Microchip Technology Inc. MCP45HVX1 TABLE 1-4: I2C BUS REQUIREMENTS (SLAVE MODE) (CONTINUED) I2C™ AC Characteristics Param. No. 103A 103B (5) (5) 106 Sym. Characteristic TFSCL SCL fall time TFSDA THD:DA T 107 109 SDA fall time Data input hold time Data input setup time TSU:DAT Output valid from clock TAA Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C TA +125C (Extended) 2.7V VL 5.5V; DGND = V- (Note 1) Min. TBUF TSP Bus free time Input filter spike suppression (SDA and SCL) Units Conditions Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode) 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 80 ns 3.4 MHz mode 10 40 ns 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb (4) 300 ns 1.7 MHz mode 20 160 ns 3.4 MHz mode 10 80 ns Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode) 100 kHz mode 0 — ns 1.8V-5.5V, Note 7 400 kHz mode 0 — ns 2.7V-5.5V, Note 7 1.7 MHz mode 0 — ns 4.5V-5.5V, Note 7 3.4 MHz mode 0 — ns 4.5V-5.5V, Note 7 Note 3 100 kHz mode 250 — ns 400 kHz mode 100 — ns 1.7 MHz mode 10 — ns 3.4 MHz mode 10 — ns 100 kHz mode — 3450 ns 400 kHz mode — 900 ns 1.7 MHz mode — 150 ns Cb = 100 pF, Note 2, Note 8 — 310 ns Cb = 400 pF, Note 2, Note 6 — 150 ns Cb = 100 pF, Note 2 Time the bus must be free before a new transmission can start 3.4 MHz mode 110 Max. Note 2 100 kHz mode 4700 — ns 400 kHz mode 1300 — ns 1.7 MHz mode N.A. — ns 3.4 MHz mode N.A. — ns 100 kHz mode — 50 ns 400 kHz mode — 50 ns 1.7 MHz mode — 10 ns Spike suppression 3.4 MHz mode — 10 ns Spike suppression NXP Spec states N.A. Note 1: Serial Interface has equal performance when DGND V- + 0.9V. Note 2: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. Note 3: A fast-mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit to the SDA line TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released. Note 6: Not tested. Note 7: A master transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. Note 8: Ensured by the TAA 3.4 MHz specification test. 2014 Microchip Technology Inc. DS20005304A-page 19 MCP45HVX1 Timing Table Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. Serial Interface has equal performance when DGND V- + 0.9V. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A fast-mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit to the SDA line TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released. The MCP45HVX1 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not tested. A master transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. Ensured by the TAA 3.4 MHz specification test. The transition of the WLAT signal between 10 ns before the rising edge (Spec 94) and 200 ns after the rising edge (Spec 95) of the SCL signal is indeterminant if the Write Data is delayed or not. DS20005304A-page 20 2014 Microchip Technology Inc. MCP45HVX1 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VL = +2.7V to +5.5V, V+ = +10V to +36V, V- = DGND = GND. Parameters Sym. Min. Typ. Max. Units Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 14L-TSSOP (ST) JA — 100 — °C/W Thermal Resistance, 20L-QFN (MQ) JA — 36.1 — °C/W Conditions Temperature Ranges Thermal Package Resistances 2014 Microchip Technology Inc. DS20005304A-page 21 MCP45HVX1 2.0 Note: TYPICAL PERFORMANCE CURVES The device Performance Curves are available in a separate document. This is done to keep the file size of this PDF document less than the 10MB file attachment limit of many mail servers. The MCP45HVX1 Performance Curves document is literature number DS20005307, and can be found on the Microchip web site. Look at the MCP45HVX1 Product Page under Documentation and Software, in the Data Sheets category. DS20005304A-page 22 2014 Microchip Technology Inc. MCP45HVX1 NOTES: 2014 Microchip Technology Inc. DS20005304A-page 23 MCP45HVX1 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follows. TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP45HVX1 Pin TSSOP QFN Symbol Type Buffer Type Function 14L 20L 1 1 VL P — Positive Digital Power Supply Input 2 2 SCL I ST I2C™ Serial Clock pin 3 3 A1 I ST I2C Address 1 4 4 SDA I/O ST I2C Serial Data pin 5 5 A0 I ST I2C Address 0 6 6 WLAT I ST Wiper Latch Enable 0 = Received I2C Shift Register Buffer (SPBUF) value is transfered to Wiper register. 1 = Received I2C data value is held in I2C Shift Register Buffer (SPBUF). 7 8, 9, 10, 17, 18, 19, 20 NC — — Pin not internally connected to die. To reduce noise coupling, connect pin either to DGND or VL. 8 7 SHDN I ST Shutdown 9 11 DGND P — Ground 10 12 V- P — Analog Negative Potential Supply 11 13 P0B I/O A Potentiometer 0 Terminal B 12 14 P0W I/O A Potentiometer 0 Wiper Terminal 13 15 P0A I/O A Potentiometer 0 Terminal A 14 16 V+ P — Analog Positive Potential Supply — 21 EP P — Exposed Pad, connect to V- signal or Not Connected (floating). (Note 1) Legend: Note 1: A = Analog I = Input ST = Schmitt Trigger O = Output I/O = Input/Output P = Power The QFN package has a contact on the bottom of the package. This contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device’s V- pin. DS20005304A-page 24 2014 Microchip Technology Inc. MCP45HVX1 3.1 Positive Power Supply Input (VL) The VL pin is the device’s positive power supply input. The input power supply is relative to DGND and can range from 1.8V to 5.5V. A decoupling capacitor on VL (to DGND) is recommended to achieve maximum performance. 3.2 Digital Ground (DGND) The DGND pin is the device’s digital ground reference. 3.3 Analog Positive Voltage (V+) Analog circuitry positive supply voltage. Must have a higher potential than the V- pin. 3.4 Analog Negative Voltage (V-) Analog circuitry negative supply voltage. The Vpotential must be lower than or equal to the DGND pin potential. 3.5 Serial Clock (SCL) The SCL pin is the serial interface's Serial Clock pin. This pin is connected to the Host Controller’s SCL pin. The MCP45HVX1 is an I2C slave device, so its SCL pin is an input-only pin. 3.6 Serial Data (SDA) The SDA pin is the serial interface’s Serial Data In/Out pin. This pin is connected to the Host Controller’s SDA pin. The SDA pin is an open-drain N-Channel driver. This pin allows the host controller to read and write the digital potentiometer registers (Wiper and TCON). 3.7 Address 0 (A0) The A0 pin is the Address 0 input for the I2C interface. At the device’s POR/BOR the value of the A0 address bit is latched. This input along with the A1 pin completes the device address. This allows up to four MCP45HVXX devices to be on a single I2C bus. 3.8 Address 1 (A1) The A1 pin is the I2C interface’s Address 1 pin. Along with the A0 pins, up to four MCP45HVXX devices can be on a single I2C bus. 3.9 Wiper Latch (WLAT) The WLAT pin is used to hold off the transfer of the received wiper value (in the Shift register) to the Wiper register. This allows this transfer to be synchronized to an external event (such as zero crossing). See Section 4.3.2. 3.10 Shutdown (SHDN) 3.11 Potentiometer Terminal B The Terminal B pin is connected to the internal potentiometer’s Terminal B. The potentiometer’s Terminal B is the fixed connection to the zero-scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x00 for both 7-bit and 8-bit devices. The Terminal B pin does not have a polarity relative to the Terminal W or A pins. The Terminal B pin can support both positive and negative current. The voltage on Terminal B must be between V+ and V-. 3.12 Potentiometer Wiper (W) Terminal The Terminal W pin is connected to the internal potentiometer’s Terminal W (the wiper). The wiper terminal is the adjustable terminal of the digital potentiometer. The Terminal W pin does not have a polarity relative to Terminal’s A or B pins. The Terminal W pin can support both positive and negative current. The voltage on Terminal W must be between V+ and V-. If the V+ voltage powers-up before the VL voltage, the wiper is forced to mid scale once the analog POR voltage is crossed. If the V+ voltage powers-up after the VL voltage is greater than the digital POR voltage, the wiper is forced to the value in the Wiper register once the analog POR voltage is crossed. 3.13 Potentiometer Terminal A The Terminal A pin is connected to the internal potentiometer’s Terminal A. The potentiometer’s Terminal A is the fixed connection to the full scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0xFF for 8-bit devices or 0x7F for 7-bit devices. The Terminal A pin does not have a polarity relative to the Terminal W or B pins. The Terminal A pin can support both positive and negative current. The voltage on Terminal A must be between V+ and V-. 3.14 Exposed Pad (EP) This pad is only on the bottom of the QFN packages. This pad is conductively connected to the device substrate. The EP pin must be connected to the Vsignal or left floating. This pad could be connected to a PCB heat sink to assist as a heat sink for the device. 3.15 Not Connected (NC) This pin is not internally connected to the die. To reduce noise coupling, these pins should be connected to either VL or DGND. The SHDN pin is used to force the resistor network terminals into the hardware shutdown state. See Section 4.3.1. 2014 Microchip Technology Inc. DS20005304A-page 25 MCP45HVX1 4.0 FUNCTIONAL OVERVIEW This data sheet covers a family of two volatile digital potentiometer devices that will be referred to as MCP45HVX1. These devices are: • MCP45HV31 (7-bit resolution) • MCP45HV51 (8-bit resolution) As the Device Block Diagram shows, there are six main functional blocks. These are: • • • • • • Operating Voltage Range POR/BOR Operation Memory Map Control Module Resistor Network Serial Interface (I2C) The POR/BOR operation and the Memory Map are discussed in this section and the Resistor Network and I2C operation are described in their own sections. The Device Commands are discussed in Section 7.0. 4.1 Operating Voltage Range The MCP45HVX1 devices have four voltage signals. These are: • • • • V+ VL DGND V- – Analog Power – Digital Power – Digital Ground – Analog Ground Figure 4-1 shows the two possible power-up sequences; analog power rails power-up first, or digital power rails power-up first. The device has been designed so that either power rail may power-up first. The device has a POR circuit for both digital power circuitry and analog power circuitry. If the V+ voltage powers-up before the VL voltage, the wiper is forced to mid scale once the analog POR voltage is crossed. If the V+ voltage powers-up after the VL voltage is greater than the digital POR voltage, the wiper is forced to the value in the Wiper register, once the analog POR voltage is crossed. Figure 4-2 shows the three cases of the digital power signals (VL/DGND) with respect to the analog power signals (V+/V-). The device implements level shifts between the digital and analog power systems, which allows the digital interface voltage to be anywhere in the V+/V- voltage window. Analog Voltage Powers-Up First Referenced to V- Referenced to DGND FIGURE 4-1: DS20005304A-page 26 V+ Digital Voltage Powers-Up First Referenced to V- V+ VL VL DGND V- DGND V- V+ Referenced to DGND V+ VL VL DGND DGND V- V- Power-On Sequences. 2014 Microchip Technology Inc. MCP45HVX1 Case 1 V+ HighVoltage Range HighVoltage Range V+ Case 2 Anywhere between V+ and V(VL DGND) VL DGND V+ and VL Case 3 DGND HighVoltage Range VL V- and DGND FIGURE 4-2: V- V- Voltage Ranges. 2014 Microchip Technology Inc. DS20005304A-page 27 MCP45HVX1 4.2 4.2.1.1 POR/BOR Operation Digital Circuitry The resistor network’s devices are powered by the analog power signals (V+/V-), but the digital logic (including the wiper registers) is powered by the digital power signals (VL/DGND). So, both the digital circuitry and analog circuitry have independent POR/BOR circuits. The Digital Power-On Reset (DPOR) is the case where the device’s VL signal has power applied (referenced from DGND) and the voltage rises above the trip point. The Brown-out Reset (BOR) occurs when a device had power applied to it, and the voltage drops below the trip point. The wiper position will be forced to the default state when the V+ voltage (relative to V-) is above the analog POR/BOR trip point. The Wiper register will be in the default state when the VL voltage (relative to DGND) is above the digital POR/BOR trip point. The device’s RAM retention voltage (VRAM) is lower than the POR/BOR voltage trip point (VPOR/VBOR). The maximum VPOR/VBOR voltage is less than 1.8V. 4.2.1 POWER-ON RESET Each power system has its own independent Power-On Reset circuitry. This is done so that regardless of the power-up sequencing of the analog and digital power rails, the wiper output will be forced to a default value after minimum conditions are met for either power supply. Table 4-1 shows the interaction between the analog and digital PORs for the V+ and VL voltages on the wiper pin state. TABLE 4-1: WIPER PIN STATE BASED ON POR CONDITIONS • Volatile wiper registers are loaded with the POR/ BOR value • The TCON registers are loaded with the default values • The device is capable of digital operation Table 4-2 shows the default POR/BOR Wiper Register Setting Selection. When VPOR/VBOR < VL < 2.7V, the electrical performance may not meet the data sheet specifications. In this region, the device is capable of incrementing, decrementing, reading and writing to its volatile memory if the proper serial command is executed. TABLE 4-2: Typical RAB Value 5.0 k Package Code The digital-signal-to-analog-signal voltage level shifters require a minimum voltage between the VL and Vsignals. This voltage requirement is below the operating supply voltage specifications. The wiper output may fluctuate while the VL voltage is less than the level shifter operating voltage, since the analog values may not reflect the digital value. Output issues may be reduced by powering-up the digital supply voltages to their operating voltage, before powering the analog supply voltage. When the device powers-up, the device VL will cross the VPOR/VBOR voltage. Once the VL voltage crosses the VPOR/VBOR voltage, the following happens: -502 DEFAULT POR/BOR WIPER REGISTER SETTING (DIGITAL) Default POR Wiper Device Wiper Register Resolution Code Setting(1) Mid scale V+ Voltage VL Voltage V+ < VAPOR V+ VAPOR VL < VDPOR Unknown Mid Scale VL VDPOR Unknown Wiper Register Value (1) Note 1: Comments 50.0 k Wiper register can be updated Default POR state of the Wiper register value is the mid-scale value. DS20005304A-page 28 10.0 k -103 -503 100.0 k -104 Note 1: Mid scale Mid scale Mid scale 8-bit 7Fh 7-bit 3Fh 8-bit 7Fh 7-bit 3Fh 8-bit 7Fh 7-bit 3Fh 8-bit 7Fh 7-bit 3Fh Register setting independent of analog power voltage. 2014 Microchip Technology Inc. MCP45HVX1 TABLE 4-3: The Analog Power-On Reset (APOR) is the case where the device’s V+ pin voltage has power applied (referenced from V-) and the V+ pin voltage rises above the trip point. Once the VL pin voltage exceeds the digital POR trip point voltage, the Wiper register will control the wiper setting. Table 4-3 shows the default POR/BOR wiper setting for when the VL pin is not powered (< digital POR trip point). Typical RAB Value 5.0 k 10.0 k 50.0 k -502 -103 -503 100.0 k -104 Note 1: DEFAULT POR/BOR WIPER SETTING (ANALOG) Default POR Wiper Setting(1) Analog Output Position Mid scale Mid scale Mid scale Mid scale Wiper Register Code (hex) Device Resolution Analog Circuitry Package Code 4.2.1.2 0x7F 8-bit 0x3F 7-bit 0x7F 8-bit 0x3F 7-bit 0x7F 8-bit 0x3F 7-bit 0x7F 8-bit 0x3F 7-bit Wiper setting is dependent on the Wiper register value if the VL voltage is greater than the digital POR voltage. Referenced to DGND V+ VL VPOR/VBOR DGND V- Digital logic has been reset (POR). This Brown-out Digital logic has been includes the Wiper register. condition, reset (POR). This Wiper value Analog Power includes the Wiper register. unknown is recovering (still Low) and VL Brown-out condition rail/pin no longer sources current Analog Power Wiper value unknown to V+ is Low Digital logic has been reset (POR). This includes the Wiper register. Note: When VL is above V+ (floating), the VL pin ESD clamping diode will cause the V+ level to be pulled up. FIGURE 4-3: DGND, VL, V+, and V- Signal Waveform Examples. 2014 Microchip Technology Inc. DS20005304A-page 29 MCP45HVX1 4.2.2 BROWN-OUT RESET Each power system has its own independent BrownOut Reset circuitry. This is done so that regardless of the power-down sequencing of the analog and digital power rails, the wiper output will be forced to a default value after the low-voltage conditions are met for either power supply. Whenever VL transitions from VL < VDBOR to VL > VDBOR, (a POR event) the wiper’s POR/BOR value is latched into the Wiper register and the volatile TCON register is forced to the POR/BOR state. When 1.8V VL, the device is capable of digital operation. Table 4-4 shows the interaction between the analog and digital BORs for the V+ and VL voltages on the wiper pin state. Table 4-5 shows the digital potentiometer’s level of functionality across the entire VL range, while Figure 4-4 illustrates the Power-Up and Brown-Out functionality. TABLE 4-4: 4.2.2.2 WIPER PIN STATE BASED ON BOR CONDITIONS V+ Voltage VL Voltage VL < VDBOR V+ < VABOR Unknown 4.2.2.1 Comments The Analog Brown-Out-Reset (ABOR) is the case where the device’s V+ pin has power applied (referenced from V-) and the V+ pin voltage drops below the trip point. In this case, the resistor network terminal’s pins can become an unknown state. Unknown Mid Scale VL VDBOR Note 1: V+ VABOR Analog Circuitry Wiper Register Value (1) Wiper register can be updated Default POR state of the Wiper register value is the mid-scale value. Digital Circuitry When the device’s digital power supply powers-down, the device VL pin voltage will cross the digital VDPOR/ VDBOR voltage. Once the VL voltage decreases below the VDPOR/ VDBOR voltage, the following happens: • Serial Interface is disabled If the VL voltage decreases below the VRAM voltage, the following happens: • Volatile wiper registers may become corrupted • TCON registers may become corrupted Section 4.2.1, Power-on Reset describes what occurs as the voltage recovers above the VDPOR/ VDBOR voltage. Serial commands not completed due to a brown-out condition may cause the memory location to become corrupted. The brown-out circuit establishes a minimum VDBOR threshold for operation (VDBOR < 1.8V). The digital BOR voltage (VDBOR) is higher than the RAM retention voltage (VRAM) so that as the device voltage crosses the digital BOR threshold, the value that is loaded into the volatile Wiper register is not corrupted due to RAM retention issues. When VL < VDBOR, all communications are ignored and potentiometer terminals are forced to the analog BOR state. DS20005304A-page 30 2014 Microchip Technology Inc. MCP45HVX1 TABLE 4-5: DEVICE FUNCTIONALITY AT EACH VL REGION Wiper VL Level V+/V- Level Serial Interface Potentiometer Terminals (2) VL < VDBOR < 1.8V Valid range Invalid range VDBOR VL < 1.8V Valid range Invalid range Ignored Ignored “Unknown” “Unknown” “Unknown” “Unknown” Connected Connected 1.8V VL 5.5V Accepted Accepted Connected Connected Note 1: 2: Valid range Invalid range Register Setting Comment Output (2) Unknown Unknown Volatile Wiper Register initialized Invalid Invalid Valid Invalid The volatile registers are forced to the POR/BOR state when VL transitions above the VDPOR trip point Volatile Valid Wiper Regis- Invalid ter determines Wiper Setting For system voltages below the minimum operating voltage, it is recommended to use a voltage supervisor to hold the system in Reset. This ensures that MCP45HVX1 commands are not attempted out of the operating range of the device. Assumes that V+ > VAPOR. Normal Operation Range VL Outside Specified AC/DC Range Normal Operation Range 1.8V VPOR/BOR VRAM DGND Device’s Device’s Serial Serial Interface is Interface is “Not Operational” “Not Specified” FIGURE 4-4: VBOR Delay Wiper Forced to Default POR/BOR setting Power-Up and Brown Out - V+/V- at Normal Operating Voltage. 2014 Microchip Technology Inc. DS20005304A-page 31 MCP45HVX1 4.3 4.3.1.2 Control Module The control module controls the following functionality: • Shutdown • Wiper Latch 4.3.1 SHUTDOWN The MCP45HVX1 has two methods to disconnect the terminal’s pins (P0A, P0W, and P0B) from the resistor network. These are: • Hardware Shutdown pin (SHDN) • Terminal Control Register (TCON) 4.3.1.1 Hardware Shutdown Pin Operation The SHDN pin has the same functionality as Microchip’s family of standard voltage devices. When the SHDN pin is Low, the P0A terminal will disconnect (become open) while the P0W terminal simultaneously connects to the P0B terminal (see Figure 4-5). Note: When the SHDN pin is Active (VIL), the state of the TCON register bits is overridden (ignored). When the state of the SHDN pin returns to the Inactive state (VIH), the TCON register bits return to controlling the terminal connection state. That is, the value in the TCON register is not corrupted. The Hardware Shutdown Pin mode does not corrupt the volatile Wiper register. When Shutdown is exited, the device returns to the wiper setting specified by the volatile wiper value. See Section 5.7 for additional description details. Note: When the SHDN pin is active, the serial interface is not disabled, and serial interface activity is executed. Terminal Control Register The Terminal Control (TCON) register allows the device’s terminal pins to be independently removed from the application circuit. These terminal control settings do not modify the wiper setting values. Also, this has no effect on the serial interface and the memory/wipers are still under full user control. The resistor network has four TCON bits associated with it. One bit for each terminal (A, W, and B) and one to have a software configuration that matches the configuration of the SHDN pin. These bits are named R0A, R0W, R0B, and R0HW. Register 4-1 describes the operation of the R0HW, R0A, R0B, and R0W bits. Note: When the R0HW bit forces the resistor network into the hardware SHDN state, the state of the TCON register R0A, R0W, and R0B bits is overridden (ignored). When the state of the R0HW bit no longer forces the resistor network into the hardware SHDN state, the TCON register R0A, R0W, and R0B bits return to controlling the terminal connection state. That is, the R0HW bit does not corrupt the state of the R0A, R0W, and R0B bits. Figure 4-6 shows how the SHDN pin signal and the R0HW bit signal interact to control the hardware shutdown of each resistor network (independently). SHDN (from pin) R0HW (from TCON register) FIGURE 4-6: Interaction. To Pot 0 Hardware Shutdown Control R0HW bit and SHDN pin Resistor Network A W B FIGURE 4-5: Hardware Shutdown Resistor Network Configuration. DS20005304A-page 32 2014 Microchip Technology Inc. MCP45HVX1 4.3.2 WIPER LATCH The wiper latch pin is used to control when the new wiper value in the Wiper register is transferred to the wiper. This is useful for applications that need to synchronize the wiper updates. This may be for synchronization to an external event, such as zero crossing, or to synchronize the update of multiple digital potentiometers. When the WLAT pin is High, transfers from the Wiper register to the wiper are inhibited. When the WLAT pin is Low, transfers may occur from the Wiper register to the wiper. Figure 4-7 shows the interaction of the WLAT pin during an I2C command and the loading of the wiper. 4.3.3 DEVICE CURRENT MODES There are two current modes for volatile devices. These are: • Serial Interface Inactive (static operation) • Serial Interface Active For the I2C interface, static operation occurs when the SDA and the SCL pins are static (High or Low). If the external event crossing time is long, then the wiper could be updated the entire time that the WLAT signal is Low. Once the WLAT signal goes High, the transfer from the Wiper register is disabled. The Wiper register can continue to be updated. If the application does not require synchronized Wiper register updates, then the WLAT pin should be tied Low. Note 1: This feature only inhibits the data transfer from the Wiper register to the wiper. 2: When the WLAT pin becomes active, data transferred to the wiper will not be corrupted due to the Wiper Register Buffer getting loaded from an active I2C command. 2014 Microchip Technology Inc. DS20005304A-page 33 MCP45HVX1 I2C™ Slave Address + Write Command + Data (less ACK bit) or I2C Slave Address + Inc/Dec Command (less ACK bit) SDA ACK bit Stop bit ACK bit SCL WLAT state lock range (for WLAT rising edge) Case 1a Case 1b Case 1c Case 2a Case 2b Case 3a Case 3b FIGURE 4-7: DS20005304A-page 34 WLAT Wiper Latch D[7:0] Wiper D[7:0] D[7:0]’ WLAT Wiper Latch D[7:0] D[7:0]’ Wiper D[7:0] D[7:0]’ Wiper Latch D[7:0] D[7:0]’ Wiper D[7:0] D[7:0]’ Wiper Latch D[7:0] D[7:0]’ Wiper D[7:0] D[7:0]’ Wiper Latch D[7:0] D[7:0]’ Wiper D[7:0] WLAT WLAT WLAT D[7:0]’ WLAT Wiper Latch D[7:0] D[7:0]’ Wiper D[7:0] D[7:0]’ Wiper Latch D[7:0] D[7:0]’ Wiper D[7:0] D[7:0]’ WLAT WLAT Interaction with I2C ACK Pulse 2014 Microchip Technology Inc. MCP45HVX1 4.4 Memory Map TABLE 4-6: WIPER REGISTER POR STANDARD SETTINGS (DIGITAL) The device memory supports 16 locations that are 8bits wide (16x8 bits). This memory space contains only volatile locations (see Table 4-7). 4.4.1 Resistance Typical Code RAB Value VOLATILE MEMORY (RAM) There are two volatile memory locations. These are: Wiper Default Code POR Wiper Setting 8-bit 7-bit • Volatile Wiper 0 • Terminal Control (TCON0) Register 0 -502 5.0 k Mid scale 7Fh 3Fh -103 10.0 k Mid scale 7Fh 3Fh The volatile memory starts functioning at the RAM retention voltage (VRAM). The POR/BOR wiper code is shown in Table 4-6. -503 50.0 k Mid scale 7Fh 3Fh -104 100.0 k Mid scale 7Fh 3Fh Table 4-7 shows this memory map and which serial commands operate (and do not) on each of these locations. Accessing an “invalid” address (for that device) or an invalid command for that address will cause an error condition on the serial interface. A Start bit is required to clear this error condition. TABLE 4-7: 4.4.1.1 Write to Invalid (Reserved) Addresses Any write to a reserved address will be ignored and will generate an error condition. A Start bit is required to clear this error condition. MEMORY MAP AND THE SUPPORTED COMMANDS Function Allowed Commands Disallowed Commands (1) Memory Type 00h Volatile Wiper 0 — RAM 01h-03h Reserved Read, Write, Increment, Decrement none — 04h Volatile TCON Register Reserved Read, Write, Increment, Decrement Increment, Decrement Address 05h-0Fh Read, Write RAM Read, Write, — Increment, Decrement Note 1: This command on this address will generate an error condition. A Start bit is required to clear this error condition. 2014 Microchip Technology Inc. none DS20005304A-page 35 MCP45HVX1 4.4.1.2 Terminal Control (TCON) Registers The value that is written to this register will appear on the resistor network terminals when the serial command has completed. The Terminal Control (TCON) Register contains four control bits for wiper 0. Register 4-1 describes each bit of the TCON register. On a POR/BOR, the registers are loaded with FFh, for all terminals connected. The host controller needs to detect the POR/BOR event and then update the volatile TCON register values. The state of each resistor network terminal connection is individually controlled. That is, each terminal connection (A, B and W) can be individually connected/ disconnected from the resistor network. This allows the system to minimize the currents through the digital potentiometer. TCON0 BITS (1, 2) REGISTER 4-1: R-1 R-1 R-1 R-1 R/W-1 R/W-1 R/W-1 R/W-1 D7 D6 D5 D4 R0HW R0A R0W R0B bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7:4 D7-D4: Reserved. Forced to “1” bit 3 R0HW: Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin 1 = Resistor 0 is NOT forced to the hardware pin “shutdown” configuration 0 = Resistor 0 is forced to the hardware pin “shutdown” configuration bit 2 R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network 1 = P0A pin is connected to the Resistor 0 Network 0 = P0A pin is disconnected from the Resistor 0 Network bit 1 R0W: Resistor 0 Wiper (P0W pin) Connect Control bit This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network 1 = P0W pin is connected to the Resistor 0 Network 0 = P0W pin is disconnected from the Resistor 0 Network bit 0 R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network 1 = P0B pin is connected to the Resistor 0 Network 0 = P0B pin is disconnected from the Resistor 0 Network Note 1: 2: These bits do not affect the Wiper register values. The hardware SHDN pin (when active) overrides the state of these bits. When the SHDN pin returns to the inactive state, the TCON register will control the state of the terminals. The SHDN pin does not modify the state of the TCON bits. DS20005304A-page 36 2014 Microchip Technology Inc. MCP45HVX1 NOTES: 2014 Microchip Technology Inc. DS20005304A-page 37 MCP45HVX1 5.0 RESISTOR NETWORK 5.1 Resistor Ladder Module The resistor network has either 7-bit or 8-bit resolution. Each resistor network allows zero-scale to full-scale connections. Figure 5-1 shows a block diagram for the resistive network of a device. The resistor network has up to three external connections. These are referred to as Terminal A, Terminal B, and the wiper (or Terminal W). The RAB resistor ladder is composed of the series of equal value Step resistors (RS) and the Full-Scale (RFS) and Zero-Scale (RZS) resistances: RAB = RZS + n * RS + RFS The resistor network is made up of several parts. These include: • Resistor Ladder Module • Wiper • Shutdown Control (terminal connections) There is a connection point (tap) between each RS resistor. Each tap point is a connection point for an analog switch. The opposite side of the analog switch is connected to a common signal which is connected to the Terminal W (wiper) pin (see Section 5.2). Terminal A and B as well as the wiper W do not have a polarity. These terminals can support both positive and negative current. Figure 5-1 shows a block diagram of the Resistor Network. The RAB (and RS) resistance has small variations over voltage and temperature. The end points of the resistor ladder are connected to analog switches, which are connected to the device Terminal A and Terminal B pins. In the ideal case, these switches would have 0 of resistance, that is RFS = RZS = 0. This will also be referred to as the Simplified model. A 8-Bit N= 255 (1) (FFh) 7-Bit N= 127 (7Fh) RW (1) 254 (FEh) 126 (7Eh) RW (1) 253 (FDh) 125 (7Dh) RFS RW RS RS R RAB S For an 8-bit device, there are 255 resistors in a string between Terminal A and Terminal B. The wiper can be set to tap onto any of these 255 resistors, thus providing 256 possible settings (including Terminal A and Terminal B). A wiper setting of 00h connects Terminal W (wiper) to Terminal B (zero scale). A wiper setting of 7Fh is the mid-scale setting. A wiper setting of FFh connects Terminal W (wiper) to Terminal A (full scale). Table 5-2 illustrates the full wiper setting map. W RW RS RW RZS (1) 1 (01h) 1 (01h) (1) 0 (00h) 0 (00h) Analog MUX B Note 1: The wiper resistance is dependent on several factors including wiper code, device V+ voltage, terminal voltages (on A, B and W), and temperature. Also for the same conditions, each tap selection resistance has a small variation. This RW variation has greater effect on some specifications (such as INL) for the smaller resistance devices (5.0 k) compared to larger resistance devices (100.0 k). FIGURE 5-1: DS20005304A-page 38 Where “n” is determined by the resolution of the device. The RFS and RZS resistances are discussed in Section 5.1.3. For a 7-bit device, there are 127 resistors in a string between Terminal A and Terminal B. The wiper can be set to tap onto any of these 127 resistors, thus providing 128 possible settings (including Terminal A and Terminal B). A wiper setting of 00h connects Terminal W (wiper) to Terminal B (zero scale). A wiper setting of 3Fh is the mid-scale setting. A wiper setting of 7Fh connects the wiper to Terminal A (full scale). Table 5-2 illustrates the full wiper setting map. 5.1.1 RAB CURRENT (IRAB) The current through the RAB resistor (A pin to B pin) is dependent on the voltage on the VA and VB pins and the RAB resistance. EQUATION 5-1: RAB RAB = RZS + ( n * RS ) + RFS = | (VA - VB) | (IRAB) VA is the voltage on the VA pin. VB is the voltage on the VB pin. IRAB is the current from the P0A pin to the P0B pin. Resistor Block Diagram. 2014 Microchip Technology Inc. MCP45HVX1 5.1.2 STEP RESISTANCE (RS) EQUATION 5-2: Step resistance (RS) is the resistance from one tap setting to the next. This value will be dependent on the RAB value that has been selected (and the full-scale and zero-scale resistances). The RS resistors are manufactured so that they should be very consistent with each other, and track each other’s values as voltage and/or temperature change. Equation 5-2 shows the simplified and detailed equations for calculating the RS value. The simplified equation assumes RFS = RZS = 0. Table 5-1 shows example step resistance calculations for each device, and the variation of the detailed model (RFS 0; RZS 0) from the simplified model (RFS = RZS = 0). As the RAB resistance option increases, the effects of the RZS and RFS resistance decreases. The total resistance of the device has minimal variation due to operating voltage (see device characterization graphs). Equation 5-2 resistance. TABLE 5-1: shows calculations for the step RS CALCULATION Simplified Model (assumes RFS = RZS = 0) RAB = ( n * RS ) RS = RAB RS = n 8-bit RAB 255 RS = 7-bit RAB 127 Detailed Model RAB = RFS + ( n * RS ) + RZS RS = RAB - RFS - RZS n or (VFS - VZS) n RS = IAB Where: “n” = 255 (8-bit) or 127 (7-bit) VFS is the wiper voltage at full-scale code VZS is the wiper voltage at zero-scale code IAB is the current between Terminal A and Terminal B EXAMPLE STEP RESISTANCES (RS) CALCULATIONS Example Resistance () RAB 5,000 10,000 50,000 100,000 Note 1: 2: 3: RZS (3) RFS (3) Variation Resolution % (1) RS Equation Value 0 0 5,000 / 127 39.37 0 80 60 4,860 / 127 38.27 -2.80 0 0 5,000 / 255 19.61 0 80 60 4,860 / 255 19.06 -2.80 0 0 10,000 / 127 78.74 0 80 60 9,860 / 127 77.64 -1.40 0 0 10,000 / 255 39.22 0 80 60 9,860 / 255 38.67 -1.40 0 0 50,000 / 127 393.70 0 80 60 49,860 / 127 392.60 -0.28 0 0 50,000 / 255 196.08 0 80 60 49,860 / 255 195.53 -0.28 0 0 100,000 / 127 787.40 0 80 60 99,860 / 127 786.30 -0.14 0 0 100,000 / 255 392.16 0 80 60 99,860 / 255 391.61 -0.14 Comment 7-bit (127 RS) Simplified Model (2) 8-bit (255 RS) Simplified Model (2) 7-bit (127 RS) Simplified Model (2) 8-bit (255 RS) Simplified Model (2) 7-bit (127 RS) Simplified Model (2) 8-bit (255 RS) Simplified Model (2) 7-bit (127 RS) Simplified Model (2) 8-bit (255 RS) Simplified Model (2) Delta % from Simplified Model RS calculation value: Assumes RFS = RZS = 0. Zero-Scale (RZS) and Full-Scale (RFS) resistances are dependent on many operational characteristics of the device, including the V+/V- voltage, the voltages on the A, B and W terminals, the wiper code selected, the RAB resistance, and the temperature of the device. 2014 Microchip Technology Inc. DS20005304A-page 39 MCP45HVX1 5.1.3 RFS AND RZS RESISTORS The RFS and RZS resistances are artifacts of the RAB resistor network implementation. In the ideal model, the RFS and RZS resistances would be 0. These resistors are included in the block diagram to help better model the actual device operation. Equation 5-3 shows how to estimate the RS, RFS, and RZS resistances, based on the measured voltages of VAB, VFS, and VZS and the measured current IAB. EQUATION 5-3: ESTIMATING RS, RFS, AND RZS (IRAB) | ( VZS - VB) | RZS = RS = Where: VS = VS = (IRAB) VS (IRAB) ( VFS - VZS ) 255 ( VFS - VZS ) 127 Wiper The Wiper terminal is connected to an analog switch MUX, where one side of all the analog switches are connected together, the W terminal. The other side of each analog switch is connected to one of the taps of the RAB resistor string (see Figure 5-1). The value in the volatile Wiper register selects which analog switch to close, connecting the W terminal to the selected node of the resistor ladder. The Wiper register is 8-bits wide, and Table 5-2 shows the wiper value state for both 7-bit and 8-bit devices. The wiper resistance (RW) is the resistance of the selected analog switch in the analog MUX. This resistance is dependent on many operational characteristics of the device, including the V+/V- voltage, the voltages on the A, B and W terminals, the wiper code selected, the RAB resistance, and the temperature of the device. | ( VA - VFS ) | RFS = 5.2 (8-bit device) (7-bit device) VFS is the VW voltage when the wiper code is at full scale. VZS is the VW voltage when the wiper code is at zero scale. When the wiper value is at zero scale (00h), the wiper is connected closest to the B terminal. When the wiper value is at full scale (FFh for 8-bit, 7Fh for 7-bit), the wiper is connected closest to the A terminal. A zero-scale wiper value connects the W terminal (wiper) to the B terminal (wiper = 00h). A full-scale wiper value connects the W terminal (wiper) to the A terminal (wiper = FFh (8-bit), or wiper = 7Fh (7-bit)). In these configurations, the only resistance between the Terminal W and the other terminal (A or B) is that of the analog switches. TABLE 5-2: VOLATILE WIPER VALUE VS. WIPER POSITION Wiper Setting Properties DS20005304A-page 40 7-bit 8-bit 7Fh FFh 7Eh-40h FEh-80h 3Fh 7Fh 3Eh-01h 7Eh-01h 00h 00h Full Scale (W = A), Increment commands ignored W=N W = N (Mid Scale) W=N Zero Scale (W = B) Decrement command ignored 2014 Microchip Technology Inc. MCP45HVX1 5.2.1 WIPER RESISTANCE (RW) 5.2.2 Wiper resistance is significantly dependent on: In a potentiometer configuration, the wiper resistance variation does not affect the output voltage seen on the W pin and therefore is not a significant source of error. • The Resistor Network’s Supply Voltage (VRN) • The Resistor Network’s Terminal (A, B, and W) Voltages • Switch leakage (occurs at higher temperatures) • IW current 5.2.3 Figure 5-2 show the wiper resistance characterization data for all four RAB resistances and temperatures. Each RAB resistance determined the maximum wiper current based on worst-case conditions RAB = RAB maximum and at full-scale code, VBW ~= V+ (but not exceeding V+). The V+ targets were 10V, 20V, and 36V. What this graph shows is that at higher RAB resistances (50 k and 100 k) and at the highest temperature (+125°C), the analog switch leakage causes an increase in the measured result of RW, where RW is measured in a rheostat configuration with RW = (VBW VBA) / IBW. 2400 Ͳ40C5kIW=1.7mA Ͳ40C5kIW=3.3mA Ͳ40C5kIW=6.0mA Ͳ40C10kIW=830uA Ͳ40C10kIW=1.7mA Ͳ40C10kIW=3.0mA Ͳ40C50kIW=170uA Ͳ40C50kIW=330uA Ͳ40C50kIW=600uA Ͳ40C100kIW=83uA Ͳ40C100kIW=170uA Ͳ40C100kIW=300uA 2200 2000 Wiper Re esistance RW (:) 1800 1600 1400 +25C5kIW=1.7mA +25C5kIW=3.3mA +25C5kIW=6.0mA +25C10kIW=830uA +25C10kIW=1.7mA +25C10kIW=3.0mA +25C50kIW=170uA +25C50kIW=330uA +25C50kIW=600uA +25C100kIW=83uA +25C100kIW=170uA +25C100kIW=300uA +85C5kIW=1.7mA +85C5kIW=3.3mA +85C5kIW=6.0mA +85C10kIW=830uA +85C10kIW=1.7mA +85C10kIW=3.0mA +85C50kIW=170uA +85C50kIW=330uA +85C50kIW=600uA +85C100kIW=83uA +85C100kIW=170uA +85C100kIW=300uA POTENTIOMETER CONFIGURATION +125C5kIW=1.7mA +125C5kIW=3.3mA +125C5kIW=6.0mA +125C10kIW=830uA +125C10kIW=1.7mA +125C10kIW=3.0mA +125C50kIW=170uA +125C50kIW=330uA +125C50kIW=600uA +125C100kIW=83uA +125C100kIW=170uA +125C100kIW=300uA RHEOSTAT CONFIGURATION In a rheostat configuration, the wiper resistance variation creates nonlinearity in the RBW (or RAW) value. The lower the nominal resistance (RAB), the greater the possible relative error. Also, a change in voltage needs to be taken into account. For the 5.0 k device, the maximum wiper resistance at 5.5V is approximately 6% of the total resistance, while at 2.7V it is approximately 6.5% of the total resistance. 5.2.4 LEVEL SHIFTERS (DIGITAL TO ANALOG) Since the digital logic may operate anywhere within the analog power range, level shifters are present so that the digital signals control the analog circuitry. This level shifter logic is relative to the V- and VL voltages. A delta voltage of 2.7V between VL and V- is required for the serial interface to operate at the maximum specified frequency. 1200 IW =83uA,+125C(100k:) 1000 800 IW =170uA,+125C(100k:) IW =170uA,+125C(50k:) 600 Increasedwiperresistance(RW)occurs duetoincreasedanalog switchleakage at highertemperatures(suchas+125C)and larger RAB resistances. largerR resistances IW =300uA,+125C(100k:) 400 200 0 0 32 64 96 128 160 DAC Wiper Code 192 224 256 FIGURE 5-2: RW Resistance vs RAB, Wiper Current (IW), Temperature and Wiper Code. Since there is minimal variation of the total device resistance (RAB) over voltage, at a constant temperature (see device characterization graphs), the change in wiper resistance over voltage can have a significant impact on the RINL and RDNL errors. 2014 Microchip Technology Inc. DS20005304A-page 41 MCP45HVX1 ues, without violating the maximum terminal current specification. Table 5-3 shows resistance and current calculations based on the RAB resistance (RS resistance) for a system that supports ± 18V ( 36V). In Rheostat configuration, the minimum wiper code value is shown (for VBW = 36V). As the VBW voltage decreases, the minimum wiper code value also decreases. Using a wiper code less then this value will cause the maximum terminal current (IT) specification to be violated. Terminal Currents The terminal currents are limited by several factors, including the RAB resistance (RS resistance). The maximum current occurs when the wiper is at either the zero-scale (IBW) or full-scale (IAW) code. In this case, the current is only going through the analog switches (see IT specification in Electrical Characteristics). When the current passes through at least one RS resistive element, then the maximum terminal current (IT) has a different limit. The current through the RAB resistor is limited by the RAB resistance. The worst case (max current) occurs when the resistance is at the minimum RAB value. Note: Higher current capabilities allow a greater delta voltage between the desired terminals for a given resistance. This also allows a more usable range of wiper code val- TERMINAL (WIPER) CURRENT AND WIPER SETTINGS (RW = RFS = RZS = 0) 4,000 6,000 15.686 31.496 9.00 25.0 1,440 91 45 0.392 0.787 10,000 8,000 12,000 31.373 62.992 4.50 12.5 2,880 91 45 0.392 0.787 Typical Min Max RS(MIN) () 8-bit 7-bit Rheostat Min ‘N’ when VBW = 36V N * RS(MIN) * 36V IT (mA) (3) RBW () (= 36V / IT(MAX) ) (2) 5,000 RAB Resistance () IAB(MAX) (mA) (= 36V / RAB(MIN) ) (1) IT (A, B, or W (IW) ) (mA) (IBW(W = ZS), IAW(W = FS) (1) TABLE 5-3: For high terminal-current applications, it is recommended that proper PCB layout techniques be used to address the thermal implications of this high current. The QFN package has better thermal properties than the TSSOP package. Rheostat VBW(MAX) When Wiper = 01h (V) (= IT(MAX) * RS(MIN) ) 5.3 8-bit 7-bit 8-bit 7-bit 50,000 40,000 60,000 156.863 314.961 0.90 6.5 5539 35 17 1.020 2.047 100,000 80,000 120,000 313.725 629.9 0.45 6.5 5539 17 8 2.039 4.094 Note 1: IBW or IAW currents can be much higher than this depending on voltage differential between Terminal B and Terminal W or Terminal A and Terminal W. 2: Any RBW resistance greater than this limits the current. 3: If VBW = 36V, then the wiper code value must be greater than or equal to Min ‘N’. Wiper codes less than Min ‘N’ will cause the wiper current (IW) to exceed the specification. Wiper codes greater than Min ‘N’ will cause the wiper current to be less than the maximum. The Min ‘N’ number has been rounded up from the calculated number to ensure that the wiper current does not exceed the maximum specification. DS20005304A-page 42 2014 Microchip Technology Inc. MCP45HVX1 Figure 5-3 through Figure 5-6 show a graph of the calculated currents (minimum, typical, and maximum) for each resistor option. These graphs are based on 25 mA (5 k), 12.5 mA (10 k), and 6.5 mA (50 k and 100 k) specifications. RAB = 5k: 30.0E-3 RAB(TYP) 4.0E-3 3.0E-3 2.0E-3 2 0E 3 RAB(MAX) 1.0E-3 000.0E+0 0 32 64 FIGURE 5-5: Code - 50 k . 96 128 160 Wiper Code 192 224 256 Maximum IBW vs Wiper RAB = 100k: 7.0E-3 6.0E-3 RAB(MIN) 5.0E-3 5 0E 3 RAB(TYP) 4.0E-3 3.0E-3 2.0E-3 2 0E 3 25.0E-3 1.0E-3 RAB(TYP) IBW(MAX) (A) RAB(MIN) 5.0E-3 5 0E 3 IBW(MAX) AX) (A) Looking at the 50 k device, the maximum terminal current is 6.5 mA. That means that any wiper code value greater than 36 ensures that the terminal current is less than 6.5 mA. This is ~14% of the full-scale value. If the application could change to the 100 k device, which has the same maximum terminal current specification, any wiper code value greater than 18 ensures that the terminal current is less than 6.5 mA. This is ~7% of the full-scale value. Supporting higher terminal current allows a greater wiper code range for a given VBW voltage. 6.0E-3 IBW(MAX) AX) (A) To ensure no damage to the resistor network (including long-term reliability) the maximum terminal current must not be exceeded. This means that the application must assume that the RAB resistance is the minimum RAB value (RAB(MIN), see blue lines in graphs). RAB = 50k: 7.0E-3 20.0E-3 RAB(MAX) 000.0E+0 RAB(MIN) 0 15.0E-3 32 64 96 128 160 Wiper Code RAB(MAX) 10.0E-3 FIGURE 5-6: Code - 100 k . 5.0E-3 000.0E+0 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE 5-3: Code - 5 k . Maximum IBW vs Wiper RAB = 10k: 192 224 256 Maximum IBW vs Wiper Figure 5-7 shows a graph of the maximum VBW voltage vs wiper code (for 5 k and 10 k devices). To ensure that no damage is done to the resistor network, the RAB(MIN) resistance (blue line) should be used to determine VBW voltages for the circuit. Devices where the RAB resistance is greater than the RAB(MIN) resistance will naturally support a higher voltage limit. 14.0E-3 40.0 12.0E-3 RAB(TYP) 35.0 RAB(MIN) 8.0E-3 30.0 RAB(MAX) 6.0E-3 VBW(MAX) (V) IBW(MAX) (A) 10.0E-3 4.0E-3 2.0E-3 RAB(MAX) RAB(TYP) 25.0 20.0 RAB(MIN) 15.0 10.0 000.0E+0 0 32 64 96 128 160 192 224 Wiper Code FIGURE 5-4: Code - 10 k . Maximum IBW vs Wiper 2014 Microchip Technology Inc. 256 5.0 0.0 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE 5-7: Maximum VBW vs Wiper Code (5 k and 10 k devices). DS20005304A-page 43 MCP45HVX1 Table 5-4 shows the maximum VBW voltage that can be applied across the Terminal B to Terminal W pins for a given wiper code value (for the 5 k and 10 k devices). These calculations assume the ideal model (RW = RFS = RZS = 0) and show the calculations based on RS(MIN) and RS(MAX). Table 5-5 shows the same calculations for the 50 k devices, and Table 5-6 shows the calculations for the 100 k devices. These tables are supplied as a quick reference. TABLE 5-4: MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V, 5 K AND 10 K DEVICES Code Hex VBW(MAX) Dec RS(MIN) RS(MAX) 00h 0 0.000 0.000 01h 1 0.392 0.588 02h 2 0.784 03h 3 1.176 04h 4 05h Code Dec RS(MIN) RS(MAX) 20h 32 12.549 18.824 21h 33 12.941 19.412 1.176 22h 34 13.333 1.765 23h 35 13.725 1.569 2.353 24h 36 5 1.961 2.941 25h 37 06h 6 2.353 3.529 26h 07h 7 2.745 4.118 27h 08h 8 3.137 4.706 09h 9 3.529 0Ah 10 3.922 0Bh 11 0Ch 0Dh Code Hex VBW(MAX) Dec RS(MIN) 40h 64 25.098 41h 65 25.490 20.000 42h 66 25.882 20.588 43h 67 25.275 14.118 21.176 44h 68 26.667 14.510 21.765 45h 69 27.059 38 14.902 22.353 46h 70 27.451 39 15.294 22.941 47h 71 27.843 28h 40 15.686 23.529 48h 72 28.235 5.294 29h 41 16.078 24.118 49h 73 28.627 5.882 2Ah 42 16.471 24.706 4Ah 74 29.020 4.314 6.471 2Bh 43 16.863 25.294 4Bh 75 29.412 12 4.706 7.059 2Ch 44 17.255 25.882 4Ch 76 29.804 13 5.098 7.647 2Dh 45 17.647 26.471 4Dh 77 30.196 0Eh 14 5.490 8.235 2Eh 46 18.039 27.059 4Eh 78 30.588 0Fh 15 5.882 8.824 2Fh 47 18.431 27.647 4Fh 79 30.980 10h 16 5.275 9.412 30h 48 18.824 28.235 50h 80 31.373 11h 17 6.667 10.000 31h 49 19.216 28.824 51h 81 31.765 12h 18 7.059 10.588 32h 50 19.608 29.412 52h 82 32.157 13h 19 7.451 11.176 33h 51 20.000 30.000 53h 83 32.549 14h 20 7.843 11.765 34h 52 20.392 30.588 54h 84 32.941 15h 21 8.235 12.353 35h 53 20.784 31.176 55h 85 33.333 16h 22 8.627 12.941 36h 54 21.176 31.765 56h 86 33.725 17h 23 9.020 13.529 37h 55 21.569 32.353 57h 87 34.118 18h 24 9.412 14.118 38h 56 21.961 32.941 58h 88 34.510 19h 25 9.804 14.706 39h 57 22.353 33.529 59h 89 34.902 1Ah 26 10.196 15.294 3Ah 58 22.745 34.118 5Ah 90 35.294 1Bh 27 10.588 15.882 3Bh 59 23.137 34.706 5Bh 91 35.686 1Ch 28 10.980 16.471 3Ch 60 23.529 35.294 5Ch 92 - 255 36.0 (1, 2) 1Dh 29 11.373 17.059 3Dh 61 23.922 35.882 1Eh 30 11.765 17.647 3Eh 62 24.314 36.0 (1, 2) 1Fh 31 12.157 18.235 3Fh 63 24.706 Note 1: Calculated RBW voltage is greater than 36V (highlighted in color), must be limited to 36V (V+ - V-). 2: Hex VBW(MAX) RS(MAX) This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT). DS20005304A-page 44 2014 Microchip Technology Inc. MCP45HVX1 TABLE 5-5: Code Hex MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V, 50 K DEVICES VBW(MAX) Dec RS(MIN) RS(MAX) Code Hex VBW(MAX) Dec Code RS(MIN) RS(MAX) Hex VBW(MAX) Dec RS(MIN) 00h 0 0.000 0.000 10h 16 16.314 24,471 20h 32 01h 1 1.020 1.529 11h 17 17.333 26.000 21h 33 33.647 02h 2 2.039 3.059 12h 18 18.353 27.529 22h 34 34.667 03h 3 3.059 4.588 13h 19 19.373 29.059 23h 35 04h 4 4.078 6.118 14h 20 20.392 30.588 24h - FFh 36 - 255 05h 5 5.098 7.647 15h 21 21.412 32.118 06h 6 6.118 9.176 16h 22 22.431 33.647 07h 7 7.137 10.706 17h 23 23.451 35.176 08h 8 8.157 12.235 18h 24 24.471 36.0 (1, 2) 09h 9 9.176 13.765 19h 25 25.490 0Ah 10 10.196 15.294 1Ah 26 26.510 0Bh 11 11.216 16.824 1Bh 27 27.529 0Ch 12 12.235 18.353 1Ch 28 28.549 0Dh 13 13.255 19.882 1Dh 29 29.569 0Eh 14 14.275 21.412 1Eh 30 30.588 0Fh 15 15.294 22.941 1Fh 31 31.608 Note 1: 2: Code Code VBW(MAX) RS(MIN) RS(MAX) 00h 0 0.000 0.000 01h 1 2.039 3.059 02h 2 4.078 6.118 12h - FFh 03h 3 6.118 9.176 04h 4 8.157 12.235 05h 5 10.196 15.294 06h 6 12.235 18.353 07h 7 14.275 21.412 08h 8 16.314 24.471 09h 9 18.353 27.529 0Ah 10 20.392 30.588 0Bh 11 22.431 33.647 0Ch 12 24.471 36.0 (1, 2) 0Dh 13 26.510 0Eh 14 28.549 15 30.588 Note 1: 2: 32.627 35.686 36.0 (1, 2) MAX VBW AT EACH WIPER CODE (RW = RFS = RZS = 0) FOR V+ - V- = 36V, 100 K DEVICES Dec 0Fh X) Calculated RBW voltage is greater than 36V (highlighted in color), must be limited to 36V (V+ - V-). This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT). TABLE 5-6: Hex RS(MA Hex VBW(MAX) Dec RS(MIN) 10h 16 32.627 11h 17 34.667 18 - 255 36.0 (1, 2) RS(MAX) Calculated RBW voltage is greater than 36V (highlighted in color), must be limited to 36V (V+ - V-). This wiper code and greater will limit the IBW current to less than the maximum supported terminal current (IT). 2014 Microchip Technology Inc. DS20005304A-page 45 MCP45HVX1 5.4 Variable Resistor (Rheostat) 5.5 A variable resistor is created using Terminal W and either Terminal A or Terminal B. Since the wiper code value of 0 connects the wiper to the Terminal B, the RBW resistance increases with increasing wiper code value. Conversely, the RAW resistance will decrease with increasing wiper code value. Figure 5-8 shows the connections from a potentiometer to create a rheostat configuration. A This device has two power supplies. One is for the digital interface (VL and DGND) and the other is for the high-voltage analog circuitry (V+ and V-). The maximum delta voltage between V+ and V- is 36V. The digital power signals must be between V+ and V-. If the digital ground (DGND) pin is at half the potential of V+ (relative to V-), then the terminal pins potentials can be ±(V+/2) relative to DGND. Figure 5-9 shows the relationship of the four power signals. This shows that the V+/V- signals do not need to be symmetric around the DGND signal. RAW RAW or W RBW RBW B To ensure that the Wiper register has been properly loaded with the POR/BOR value, the VL voltage must be at the minimum specified operating voltage (referenced to DGND). Rheostat Configuration. Equation 5-4 shows the RBW and RAW calculations. The RBW calculation is for the resistance between the wiper and Terminal B. The RAW calculation is for the resistance between the wiper and Terminal A. EQUATION 5-4: RBW AND RAW CALCULATION Simplified Model (assumes RFS = RZS = 0) RBW = ( n * RS ) RAW = ( ( FSV - n ) * RS ) Where: RS = RAB 8-bit RAB RS = RS = Resolution 255 n = wiper code FSV = The full-scale value (255 for 8-bit or 127 for 7-bit) Detailed Model RBW = RZS + ( n * RS ) RAW = RFS + ( ( FSV - n ) * RS ) Where: n = wiper code FSV = The full-scale value (255 for 8-bit or 127 for 7-bit) DS20005304A-page 46 Voltages Relative to DGND Resistor FIGURE 5-8: Analog Circuitry Power Requirements V+ VL DGND V+ – V- Voltage +36V max +10V min VThis can be anywhere between V- and V+. 7-bit RAB 127 FIGURE 5-9: Ranges. 5.6 5.6.1 Analog Circuitry Voltage Resistor Characteristics V+/V- LOW VOLTAGE OPERATION The resistor network is specified from 20V to 36V. At voltages below 20V, the resistor network will function, but the operational characteristics may be outside the specified limits. Please refer to Section 2.0 “Typical Performance Curves” for additional information. 5.6.2 RESISTOR TEMPCO Biasing the ends (Terminal A and Terminal B) near midsupply ((V+ - |V-|) / 2) will give the worst switch resistance temperature coefficient (tempco). 2014 Microchip Technology Inc. MCP45HVX1 5.7 Shutdown Control Note: Shutdown is used to minimize the device’s current consumption. The MCP45HVX1 has two methods to achieve this: • Hardware Shutdown Pin (SHDN) • Terminal Control Register (TCON) The Hardware Shutdown pin is backwards compatible with the MCP42X1 devices. 5.7.1 HARDWARE SHUTDOWN PIN (SHDN) The SHDN pin is available on the potentiometer devices. When the SHDN pin is forced active (VIL): • The P0A terminal is disconnected • The P0W terminal is connected to the P0B terminal (see Figure 4-5) • The Serial Interface is NOT disabled, and all Serial Interface activity is executed The R0HW bit does NOT corrupt the values in the volatile wiper registers nor the TCON register. When the Shutdown mode is exited (R0HW bit = 1): • The device returns to the wiper setting specified by the volatile wiper value • The TCON register bits return to controlling the terminal connection state The Hardware Shutdown Pin mode does NOT corrupt the values in the volatile wiper registers nor the TCON register. When the Shutdown mode is exited (SHDN pin is inactive (VIH)): Resistor Network A • The device returns to the wiper setting specified by the volatile wiper value • The TCON register bits return to controlling the terminal connection state Resistor Network W B FIGURE 5-11: Resistor Network Shutdown State (R0HW = 0). A W B FIGURE 5-10: Hardware Shutdown Resistor Network Configuration. 5.7.2 When the R0HW bit forces the resistor network into the hardware SHDN state, the state of the TCON0 register’s R0A, R0W and R0B bits is overridden (ignored). When the state of the R0HW bit no longer forces the resistor network into the hardware SHDN state, the TCON0 register’s R0A, R0W and R0B bits return to controlling the terminal connection state. In other words, the R0HW bit does not corrupt the state of the R0A, R0W and R0B bits. TERMINAL CONTROL REGISTER (TCON) The Terminal Control (TCON) register is a volatile register used to configure the connection of each resistor network terminal pin (A, B and W) to the Resistor Network. This register is shown in Register 4-1. 5.7.3 INTERACTION OF SHDN PIN AND TCON REGISTER Figure 5-12 shows how the SHDN pin signal and the R0HW bit signal interact to control the hardware shutdown of the resistor network. SHDN (from pin) R0HW (from TCON register) FIGURE 5-12: Interaction. To Pot 0 Hardware Shutdown Control R0HW bit and SHDN pin The R0HW bit forces the selected resistor network into the same state as the SHDN pin. Alternate low-power configurations may be achieved with the R0A, R0W and R0B bits. When the R0HW bit is “0”: • The P0A terminal is disconnected • The P0W terminal is simultaneously connected to the P0B terminal (see Figure 5-11) 2014 Microchip Technology Inc. DS20005304A-page 47 MCP45HVX1 6.0 SERIAL INTERFACE (I2C) The MCP45HVX1 devices support the I2C serial protocol. The MCP45HVX1 I2C module operates in Slave mode (does not generate the serial clock). Figure 6-1 shows a typical I2C interface connection. The MCP45HVX1 devices use the two-wire I2C serial interface. This interface can operate in Standard, Fast or High-Speed mode. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access and generates the Start and Stop conditions. The MCP45HVX1 device works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. Communication is initiated by the master (microcontroller) which sends the Start bit, followed by the slave address byte. The first byte transmitted is always the slave address byte, which contains the device code, the address bits, and the R/W bit. Refer to the NXP I2C document for more details of the I2C specifications (UM10204, Ver. 05 Oct 2012). Typical I2C™ Interface Connections MCP4XXX Host Controller SCL SCL SDA SDA (1) A0 (1) I/O (1) A1 (1) I/O Note 1: This pin could be tied High, Low, or connected to an I/O pin of the Host Controller. FIGURE 6-1: Diagram. DS20005304A-page 48 Typical I2C Interface Block 6.1 Signal Descriptions The I2C interface uses up to four pins (signals). These are: • • • • SDA (Serial Data) SCL (Serial Clock) A0 (Address 0 bit) A1 (Address 1 bit) 6.1.1 SERIAL DATA (SDA) The Serial Data (SDA) signal is the data signal of the device. The value on this pin is latched on the rising edge of the SCL signal when the signal is an input. With the exception of the Start and Stop conditions, the High or Low state of the SDA pin can only change when the clock signal on the SCL pin is Low. During the High period of the clock, the SDA pin’s value (High or Low) must be stable. Changes in the SDA pin’s value while the SCL pin is High will be interpreted as a Start or a Stop condition. 6.1.2 SERIAL CLOCK (SCL) The Serial Clock (SCL) signal is the clock signal of the device. The rising edge of the SCL signal latches the value on the SDA pin. The MCP45HVX1 supports three I2C interface clock modes: • Standard mode: clock rates up to 100 kHz • Fast mode: clock rates up to 400 kHz • High-Speed mode (HS mode): clock rates up to 3.4 MHz The MCP45HVX1 will not stretch the clock signal (SCL) since memory read access occurs fast enough. Depending on the clock rate mode, the interface will display different characteristics. 6.1.3 THE ADDRESS BITS (A1:A0) There are up to two hardware pins used to specify the device address. The number of address pins is determined by the part number. The state of the A0 and A1 pins should be static, that is they should be tied High or tied Low. 2014 Microchip Technology Inc. MCP45HVX1 6.2 I2C Operation 6.2.1.3 The MCP45HVX1 I2C module is compatible with the NXP I2C specification. The following lists some of the module’s features: • 7-bit slave addressing • Supports three clock rate modes: - Standard mode, clock rates up to 100 kHz - Fast mode, clock rates up to 400 kHz - High-Speed mode (HS mode), clock rates up to 3.4 MHz • Support Multi-Master Applications • General call addressing Acknowledge (A) Bit The A bit (see Figure 6-4) is typically a response from the receiving device to the transmitting device. Depending on the context of the transfer sequence, the A bit may indicate different things. Typically, the slave device will supply an A response after the Start bit and 8 “data” bits have been received. an A bit has the SDA signal Low. SDA SCL The I2C 10-bit addressing mode is not supported. The NXP I2C specification only defines the field types, field lengths, timings, etc. of a frame. The frame content defines the behavior of the device. The frame content for the MCP45HVX1 is defined in Section 7.0. 6.2.1 I2C BIT STATES AND SEQUENCE Figure 6-8 shows the I2C transfer sequence. The serial clock is generated by the master. The following definitions are used for the bit states: • Start bit (S) • Data bit • Acknowledge (A) bit (driven Low)/ No Acknowledge (A) bit (not driven Low) • Repeated Start bit (Sr) • Stop bit (P) 6.2.1.1 1st Bit 2nd Bit SCL S FIGURE 6-2: 6.2.1.2 Start Bit. Data Bit The SDA signal may change state while the SCL signal is Low. While the SCL signal is High, the SDA signal MUST be stable (see Figure 6-3). 1st Bit SDA 2nd Bit 8 9 Acknowledge Waveform. The A bit has the SDA signal High. Table 6-1 shows some of the conditions where the slave device will issue a Not A (A). If an error condition occurs (such as an A instead of A), then a Start bit must be issued to reset the command state machine. Event The Start bit (see Figure 6-2) indicates the beginning of a data transfer sequence. The Start bit is defined as the SDA signal falling when the SCL signal is “High”. A Not A (A) Response TABLE 6-1: Start Bit SDA FIGURE 6-4: D0 MCP45HVX1 A/A RESPONSES Acknowledge Bit Response Comment General Call A Slave Address valid A Slave Address not valid A Device Memory Address and specified command (AD3:AD0 and C1:C0) are an invalid combination A After device has received address and command N.A. I2C™ module resets, or a “don’t care” if the collision occurs on the master’s “Start bit” Bus Collision Only if GCEN bit is set SCL Data Bit FIGURE 6-3: Data Bit. 2014 Microchip Technology Inc. DS20005304A-page 49 MCP45HVX1 6.2.1.4 6.2.1.5 Repeated Start Bit The Repeated Start bit (see Figure 6-5) indicates the current master device will attempt to continue communicating with the current slave device without releasing the I2C bus. The Repeated Start condition is the same as the Start condition, except that the Repeated Start bit follows a Start bit (with the Data bits + A bit) and not a Stop bit. The Stop bit (see Figure 6-6) indicates the end of the I2C Data Transfer Sequence. The Stop bit is defined as the SDA signal rising when the SCL signal is “High”. A Stop bit resets the I2C interface of all MCP45HVX1 devices. SDA A / A The Start bit is the beginning of a data transfer sequence and is defined as the SDA signal falling when the SCL signal is “High”. SCL P Note 1: A bus collision during the Repeated Start condition occurs if: FIGURE 6-6: Transmit Mode. • SDA is sampled Low when SCL goes from low-to-high. 6.2.2 • SCL goes Low before SDA is asserted Low. This may indicate that another master is attempting to transmit a data ‘1’. CLOCK STRETCHING The MCP45HVX1 will not stretch the clock signal (SCL) since memory read access occurs fast enough. 6.2.3 ABORTING A TRANSMISSION If any part of the I2C transmission does not meet the command format, it is aborted. This can be intentionally accomplished with a Start or Stop condition. This is done so that noisy transmissions (usually an extra Start or Stop condition) are aborted before they corrupt the device. SCL Sr = Repeated Start FIGURE 6-5: Waveform. Stop Condition Receive or “Clock Stretching” is something that the receiving device can do, to allow additional time to “respond” to the “data” that has been received. 1st Bit SDA Stop Bit Repeat Start Condition SDA SCL S FIGURE 6-7: 1st Bit 2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit A/A P Typical 8-Bit I2C Waveform Format. SDA SCL Start Condition FIGURE 6-8: DS20005304A-page 50 Data allowed to change Data or A valid Stop Condition I2C Data States and Bit Sequence. 2014 Microchip Technology Inc. MCP45HVX1 6.2.4 ADDRESSING The address byte is the first byte received following the Start condition from the master device. The address contains four (or more) fixed bits and (up to) three userdefined hardware address bits (pins A1 and A0). These 7-bits address the desired I2C device. The A6:A2 address bits are fixed to ‘01111’ and the device appends the value of following two address pins (A1 and A0). Since there are address bits controlled by hardware pins, there may be up to four MCP45HVX1 devices on the same I2C bus. Figure 6-9 shows the slave address byte format, which contains the seven address bits. There is also a read/ write (R/W) bit. Table 6-2 shows the fixed address for device. Hardware Address Pins The hardware address bits (A1, and A0) correspond to the logic level on the associated address pins. This allows up to four devices on the bus. Slave Address S A6 A5 A4 A3 A2 A1 A0 R/W “0” “1” “1” “1” “1” See Table 6-2 Start bit A/A R/W bit R/W = 0 = write R/W = 1 = read A bit (controlled by slave device) A = 0 = Slave device Acknowledges byte A = 1 = Slave device does not Acknowledge byte FIGURE 6-9: I2C Control Byte. TABLE 6-2: Slave Address Bits in the DEVICE SLAVE ADDRESSES Device MCP45HVX1 Note 1: 6.2.5 Address Comment ‘0111 1’b + A1:A0 Supports up to 4 devices. (Note 1) The fixed portion of the I2C address is different than the MCP44XX/MCP45XX/ MCP46XX family (‘0101 11’, ‘0101 1’, or ‘0101’). This allows the maximum number of both standard and high-voltage devices on the single I2C bus. SLOPE CONTROL The MCP45HVX1 implements slope control on the SDA output. As the device transitions from HS mode to FS mode, the slope control parameter will change from the HS specification to the FS specification. For Fast (FS) and High-Speed (HS) modes, the device has a spike suppression and a Schmitt trigger at SDA and SCL inputs. 2014 Microchip Technology Inc. DS20005304A-page 51 MCP45HVX1 6.2.6 HS MODE After switching to the High-Speed mode, the next transferred byte is the I2C control byte, which specifies the device to communicate with, and any number of data bytes plus acknowledgments. The master device can then issue either a Repeated Start bit to address a different device (at high speed) or a Stop bit to return to Fast/Standard bus speed. After the Stop bit, any other master device (in a multi-master system) can arbitrate for the I2C bus. 2 The I C specification requires that a High-Speed mode device must be ‘activated’ to operate in High-Speed (3.4 Mbit/s) mode. This is done by the master sending a special address byte following the Start bit. This byte is referred to as the High-Speed Master Mode Code (HSMMC). The MCP45HVX1 device does not acknowledge this byte. However, upon receiving this command, the device switches to HS mode. The device can now communicate at up to 3.4 Mbit/s on SDA and SCL lines. The device will switch out of the HS mode on the next Stop condition. See Figure 6-10 for illustration of HS mode command sequence. For more information on the HS mode, or other I2C modes, please refer to the Phillips I2C specification. The master code is sent as follows: 1. 2. 3. 6.2.6.1 Start condition (S) High-Speed Master Mode Code (0000 1XXX), The XXX bits are unique to the High-Speed (HS) mode master. No Acknowledge (A) Slope Control The slope control on the SDA output is different between the Fast/Standard Speed and the High-Speed Clock modes of the interface. 6.2.6.2 Pulse Gobbler The pulse gobbler on the SCL pin is automatically adjusted to suppress spikes < 10 ns during HS mode. F/S mode HS mode S ‘0 0 0 0 1 X X X’b HS Select Byte P A Sr ‘Slave Address’ R/W A Control Byte “Data” Command/Data Byte(s) S = Start bit Sr = Repeated Start bit A = Acknowledge bit A = Not Acknowledge bit R/W = Read/Write bit P = Stop bit (Stop condition terminates HS mode) FIGURE 6-10: DS20005304A-page 52 A/A F/S mode HS mode continues Sr ‘Slave Address’ R/W A Control Byte HS Mode Sequence. 2014 Microchip Technology Inc. MCP45HVX1 6.2.7 GENERAL CALL The General Call is a method that the “master” device can communicate with all other “slave” devices. In a multi-master application, the other master devices are operating in Slave mode. The General Call address has two documented formats. These are shown in Figure 6-11. We have added an MCP45HVX1 format in this figure as well. This will allow customers to have multiple I2C digital potentiometers on the bus and have them operate in a synchronous fashion (analogous to the DAC Sync pin functionality). If these MCP45HVX1 7-bit commands conflict with other I2C devices on the bus, then the customer will need two I2C buses and ensure that the devices are on the correct bus for their desired application functionality. Dual Pot devices can not update both Pot0 and Pot1 from a single command. To address this, there are General Call commands for the Wiper 0, Wiper 1, and the TCON registers. Table 6-3 shows the General Call commands. Three commands are specified by the I2C specification and are not applicable to the MCP45HVX1 (so command is Not Acknowledged) The MCP45HVX1 General Call commands are Acknowledged. Any other command is Not Acknowledged. Note: Only one General Call command per issue of the General Call control byte. Any additional General Call commands are ignored and Not Acknowledged. 2014 Microchip Technology Inc. TABLE 6-3: 7-bit Command GENERAL CALL COMMANDS Comment (1, 2, 3) ‘1000 000’b or ‘1000 001’b Write next byte (third byte) to volatile Wiper 0 register ‘1100 000’b or ‘1100 001’b Write Next Byte (Third Byte) to TCON Register ‘1000 010’b or ‘1000 011’b Increment Wiper 0 Register ‘1000 100’b or ‘1000 101’b Decrement Wiper 0 Register Note 1: 2: Any other code is Not Acknowledged. These codes may be used by other devices on the I2C bus. The 7-bit command always appends a “0” to form 8-bits. DS20005304A-page 53 MCP45HVX1 Second Byte S 0 0 0 0 0 0 0 0 A X X X X X X X 0 A P General Call Address “7-bit Command” Reserved 7-bit Commands (By I2C™ Specification - NXP UM10204, Ver. 05 October 2012) ‘0000 011’b – Reset and write programmable part of slave address by hardware. ‘0000 010’b – Write programmable part of slave address by hardware. ‘0000 000’b – NOT Allowed MCP45HVX1 7-bit Commands ‘1000 01x’b – Increment Wiper 0 Register. ‘1000 10x’b – Decrement Wiper 0 Register. The Following is a Microchip Extension to this General Call Format Second Byte S 0 0 0 0 Third Byte 0 0 0 0 A X X X X X X X 0 A d General Call Address “7-bit Command” d d d d d d d A P “0” for General Call Command MCP45HVX1 7-bit Commands ‘1000 00x’b – Write Next Byte (Third Byte) to Volatile Wiper 0 Register. ‘1100 00x’b – Write Next Byte (Third Byte) to TCON Register. The Following is a “Hardware General Call” Format Second Byte S 0 0 0 0 0 0 0 0 A X X X X General Call Address FIGURE 6-11: DS20005304A-page 54 “7-bit Command” n occurrences of (Data + A) X X 1 A X X X X X X X X A P This indicates a “Hardware General Call” MCP45HVX1 will ignore this byte and all following bytes (and A), until a Stop bit (P) is encountered. General Call Formats. 2014 Microchip Technology Inc. MCP45HVX1 NOTES: 2014 Microchip Technology Inc. DS20005304A-page 55 MCP45HVX1 7.0 DEVICE COMMANDS 7.1 The MCP45HVX1’s I2C command formats are specified in this section. The I2C protocol does not specify how commands are formatted. The MCP45HVX1 supports four basic commands. The location accessed determines the commands that are supported. For the volatile wiper registers, these commands are: • • • • Write Data Read Data Increment Data Decrement Data These commands have formats for both a single command or continuous commands. These commands are shown in Table 7-1. TABLE 7-1: I2C COMMANDS Command Operation Write Data Mode Single Continuous Read Data Single Random Continuous Increment Single Continuous Decrement Single Continuous Note 1: 2: Operates # of Bit on Volatile/ Clocks (1, 2) Nonvolatile memory 29 18n + 11 29 Both Command Byte The MCP45HVX1 command byte has three fields: the address, the command operation, and two data bits (see Figure 7-1). Currently only one of the data bits is defined (D8). The device memory is accessed when the master sends a proper command byte to select the desired operation. The memory location getting accessed is contained in the command byte’s AD3:AD0 bits. The action desired is contained in the command byte’s C1:C0 bits, see Figure 7-1. C1:C0 determines if the desired memory location will be read, written, incremented (wiper setting +1) or decremented (wiper setting -1). The Increment and Decrement commands are only valid on the volatile Wiper register. If the address bits and command bits are not a valid combination, then the MCP45HVX1 will generate a Not Acknowledge pulse to indicate the invalid combination. The I2C master device must then force a Start condition to reset the MCP45HVX1 I2C module. D9 and D8 are unused data bits. These bits maintain code compatibility with the MCP44XX, MCP45XX, and MCP46XX devices. Volatile Only COMMAND BYTE Both 48 Both 18n + 11 Both 20 Volatile Only 9n + 11 Volatile Only 20 Volatile Only 9n + 11 Volatile Only “n” indicates the number of times the command operation is to be repeated. These clock counts are for “standard” and “fast” I2C communication. Table 7-2 shows the supported commands for each memory location. A A A A A C C D D A D D D D 1 0 9 8 3 2 1 0 MSbits (Data) MCP45HVXXX Memory Address Command Operation bits 00 = Write Data 01 = Increment 10 = Decrement 11 = Read Data FIGURE 7-1: Command Byte Format. Table 7-3 shows an overview of all the device commands and their interaction with other device features. DS20005304A-page 56 2014 Microchip Technology Inc. MCP45HVX1 TABLE 7-2: Value 00h MEMORY MAP AND THE SUPPORTED COMMANDS Address Function Volatile Wiper 0 Command Data (10-bits) (1) Comment Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn Increment Wiper — Decrement Wiper — 01h-03h Reserved — — 04h (2) Volatile Write Data nn nnnn nnnn TCON 0 Register nn nnnn nnnn Read Data (3) 05h-FFh Reserved — — Note 1: The data memory is 8-bits wide, so the two MSbs are ignored by the device. This is for compatibility with the MCP44XX, MCP45XX, and MCP46XX command formats. 2: Increment or Decrement commands are invalid for these addresses. 3: I2C read operation will read two bytes, of which the 8 bits of data are contained within the Least Significant Byte (LSB). This is for compatibility with the MCP44XX, MCP45XX, and MCP46XX command formats. 2014 Microchip Technology Inc. DS20005304A-page 57 MCP45HVX1 7.2 Data Byte Only the Read command and the Write command have data byte(s). Even though only one byte of data is required for the commands, the supported commands will be formatted for compatibility with the MCP44XX, MCP45XX, and MCP46XX command formats with support of 10 bits of data. 7.3 Error Condition If the four address bits received (AD3:AD0) and the two command bits received (C1:C0) are a valid combination, the MCP45HVX1 will Acknowledge the I2C bus. If the address bits and command bits are an invalid combination, then the MCP45HVX1 will Not Acknowledge the I2C bus. Once an error condition has occurred, any following commands are ignored until the I2C bus is reset with a Start condition. 7.3.1 ABORTING A TRANSMISSION A Restart or Stop condition in the expected data bit position will abort the current command sequence and data will not be written to the MCP45HVX1. TABLE 7-3: COMMANDS # of Bit Clocks Command Name Single Continuous (1) Write Data 29 18n + 11 Read Data 29 (2) 18n + 11 Increment Wiper 20 9n + 11 Decrement Wiper 20 9n + 11 Note 1: 2: “n” indicates the number of times the command operation is to be repeated. For a random read (read from any memory location), 40 bit clocks are required. DS20005304A-page 58 2014 Microchip Technology Inc. MCP45HVX1 7.4 7.4.1 Write Data The Write command format, see Figure 7-2, includes the I2C control byte, an A bit, the MCP45HVX1 command byte, an A bit, the MCP45HVX1 data byte, an A bit, and a Stop (or Restart) condition. The MCP45HVX1 generates the A / A bits. SINGLE WRITE TO VOLATILE MEMORY Data is written to the MCP45HVX1 after every byte transfer (during the Acknowledge). If a Stop or Restart condition is generated during a data transfer (before the A), the data will not be written to the MCP45HVX1. After the A bit, the master can initiate the next sequence with a Stop or Restart condition. A Write command to a volatile memory location changes that location after a properly formatted Write command and the A/A clock have been received. Refer to Figure 7-2 for the byte write sequence. 7.4.2 CONTINUOUS WRITES TO VOLATILE MEMORY A Continuous Write mode of operation is possible when writing to the volatile memory registers (address 00h and 04h). This Continuous Write mode allows writes without a Stop or Restart condition or repeated transmissions of the I2C Control Byte. Figure 7-3 shows the sequence for three continuous writes. The writes do not need to be to the same volatile memory address. The sequence ends with the master sending a Stop or Restart condition. Write bit Variable Address Fixed Address S 0 1 1 1 1 A1 A0 0 A Control Byte FIGURE 7-2: I2C Device Memory Address Write “Data” bits Command AD AD AD AD 3 2 1 0 0 Write command 0 x x A D7 D6 D5 D4 D3 D2 D1 D0 A P Reserved Write Data bits Write Sequence. 2014 Microchip Technology Inc. DS20005304A-page 59 MCP45HVX1 Write bit Variable Address Fixed Address S 0 1 1 1 1 A1 A0 0 A Device Memory Address AD AD AD AD 3 2 1 0 0 AD AD AD AD 3 2 1 0 0 Write command 0 x x A D7 D6 D5 D4 D3 D2 D1 D0 A Reserved Write Data bits x A D7 D6 D5 D4 D3 D2 D1 D0 A Write Data bits Reserved AD AD AD AD 3 2 1 0 0 Write command Note: 0 x Write command Control Byte Write “Data” bits Command 0 x x Stop bit A D7 D6 D5 D4 D3 D2 D1 D0 A P Reserved Write Data bits Only functions when writing the volatile wiper registers (AD3:AD0 = 00h and 01h) or the TCON registers (AD3:AD0 = 04h) FIGURE 7-3: DS20005304A-page 60 I2C Continuous Volatile Wiper Write. 2014 Microchip Technology Inc. MCP45HVX1 7.5 7.5.1 Read Data SINGLE READ The Read command format, see Figure 7-4, includes the Start condition, I2C control byte (with R/W bit set to “0”), A bit, MCP45HVX1 command byte, A bit, followed by a Repeated Start bit, I2C control byte (with R/W bit set to “1”), and the MCP45HVX1 transmitting the requested data high byte, and A bit, the data low byte, the master generating the A, and Stop condition. Figure 7-4 shows the waveforms for a single read. The I2C control byte requires the R/W bit equal to a logic one (R/W = 1) to generate a read sequence. The memory location read will be the last address contained in a valid write MCP45HVX1 command byte or address 00h if no write operations have occurred since the device was reset (Power-On Reset or BrownOut Reset). 7.5.2 Note: For single reads the master sends a Stop or Restart condition after the data byte is sent from the slave. 7.5.1.1 Random Read Figure 7-5 shows the sequence for a Random Read. CONTINUOUS READS Continuous reads allows the devices’ memory to be read quickly. Continuous reads are possible to all memory locations. Figure 7-6 shows the sequence for three continuous reads. For continuous reads, instead of transmitting a Stop or Restart condition after the data transfer, the master reads the next data byte. The sequence ends with the master Not Acknowledging and then sending a Stop or Restart. The MSB (Most Significant Byte) of the 16 read bits is all 0’s to maintain read command format compatibility with the MCP44XX/MCP45XX/MCP46XX families of devices. 7.5.3 IGNORING AN I2C TRANSMISSION AND “FALLING OFF” THE BUS The MCP45HVX1 expects to receive complete, valid I2C commands, and will assume any command not defined as valid is due to a bus corruption, and will enter a passive High condition on the SDA signal. All signals will be ignored until the next valid Start condition and control byte are received. Read bit Stop bit Variable Address Fixed Address S 0 1 1 1 1 A1 A0 1 A Control Byte Read Data bits 0 0 0 0 0 0 0 0 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2 P Read bits Note 1: Master device is responsible for A/A signal. If a A signal occurs, the MCP45HVX1 will abort this transfer and release the bus. 2: The master device will Not Acknowledge, and the MCP45HVX1 will release the bus so the master device can generate a Stop or Repeated Start condition. 3: The MCP45HVX1 retains the last “Device Memory Address” that it has received. That is, the MCP45HVX1 does not “corrupt” the “Device Memory Address” after Repeated Start or Stop conditions. 4: The Device Memory Address pointer defaults to 00h on POR and BOR conditions. FIGURE 7-4: I2C Read (Last Memory Address Accessed). 2014 Microchip Technology Inc. DS20005304A-page 61 MCP45HVX1 Write bit Variable Address Fixed Address S 0 1 1 1 Repeated Start bit Device Memory Address 1 A1 A0 0 A Command AD AD AD AD 3 2 1 0 1 x X A Sr 1 READ command Control Byte Stop bit Read bit 0 1 1 1 1 A1 A0 1 Read Data bits A 0 0 0 0 0 0 Control Byte 0 0 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2 P Read bits Note 1: Master device is responsible for A/A signal. If a A signal occurs, the MCP45HVX1 will abort this transfer and release the bus. 2: The master device will Not Acknowledge, and the MCP45HVX1 will release the bus so the master device can generate a Stop or Repeated Start condition. 3: The MCP45HVX1 retains the last “Device Memory Address” that it has received. This is, the MCP45HVX1 does not “corrupt” the “Device Memory Address” after Repeated Start or Stop conditions. I2C Random Read. FIGURE 7-5: Read bit Variable Address Fixed Address S 0 1 1 1 Read Data bits 1 A1 A0 1 A 0 0 0 0 0 0 0 0 A1 D7 D6 D5 D4 D3 D2 D1 D0 A1 Read bits Control Byte Read Data bits 0 0 0 0 0 0 0 0 A1 D7 D6 D5 D4 D3 D2 D1 D0 A1 Stop bit Read Data bits 0 0 0 0 0 0 0 0 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2 P Note 1: Master device is responsible for A/A signal. If a A signal occurs, the MCP45HVX1 will abort this transfer and release the bus. 2: The master device will Not Acknowledge, and the MCP45HVX1 will release the bus so the master device can generate a Stop or Repeated Start condition. FIGURE 7-6: DS20005304A-page 62 I2C Continuous Reads. 2014 Microchip Technology Inc. MCP45HVX1 7.6 Refer to Figure 7-7 for the Increment command sequence. The sequence is terminated by the Stop condition. So when executing a continuous command string, the Increment command can be followed by any other valid command. This means that writes do not need to be to the same volatile memory address. Increment Wiper The Increment command provides a quick and easy method to modify the potentiometer’s wiper by +1 with minimal overhead. The Increment command will only function on the volatile wiper setting memory locations 00h and 01h. The Increment command to nonvolatile addresses will be ignored and will generate an A. Note: Note: Table 7-4 shows the valid addresses for the Increment Wiper command. Other addresses are invalid. When executing an Increment command, the volatile wiper setting will be altered from n to n+1 for each Increment command received. The value will increment up to 100h max on 8-bit devices and 80h on 7-bit devices. If multiple Increment commands are received after the value has reached 100h (or 80h), the value will not be incremented further. Table 7-4 shows the Increment command versus the current volatile wiper value. The advantage of using an Increment command instead of a read-modify-write series of commands is speed and simplicity. The wiper will transition after each command acknowledge when accessing the volatile wiper registers. TABLE 7-4: The Increment command will most commonly be performed on the volatile wiper locations until a desired condition is met. The MCP45HVX1 is responsible for generating the A bits. Fixed Address S 0 1 1 1 Write bit Variable Address 1 A1 A0 0 Control Byte A Device Memory Address The command sequence can go from an increment to any other valid command for the specified address. Issuing an increment or decrement to a reserved location will cause an error condition (A will be generated). Current Wiper Setting INCREMENT OPERATION VS. VOLATILE WIPER VALUE Increment Command Operates? Wiper (W) Properties 7-bit Pot 8-bit Pot 7Fh FFh Full Scale (W = A) 07Eh 40h FEh 80 W=N 3Fh 7Fh W = N (Mid Scale) 3Eh 01h 7Eh 01 W=N 00h 00h Zero Scale (W = B) Yes No Yes Command AD AD AD AD 3 2 1 0 0 1 x x AD AD AD AD A 4 3 2 1 0 1 x x A P (2) INCR command (n+1) Reserved INCR command (n+2) Reserved Note 1: Increment command (INCR) only functions when accessing the volatile wiper registers (AD3:AD0 = 00h and 01h). 2: This command sequence does not need to terminate (using the Stop bit) and can change to any other desired command sequence (Increment, Read, or Write). FIGURE 7-7: I2C Increment Command Sequence. 2014 Microchip Technology Inc. DS20005304A-page 63 MCP45HVX1 7.7 Decrement Wiper The Decrement command provides a quick and easy method to modify the potentiometer’s wiper by -1 with minimal overhead. The Decrement command will only function on the volatile wiper setting memory locations 00h and 01h. The advantage of using a Decrement command instead of a read-modify-write series of commands is speed and simplicity. The wiper will transition after each command acknowledge when accessing the volatile wiper registers. TABLE 7-5: Table 7-5 shows the valid addresses for the Decrement Wiper command. Other addresses are invalid. When executing a Decrement command, the volatile wiper setting will be altered from n to n-1 for each Decrement command received. The value will decrement down to 000h min. If multiple Decrement commands are received after the value has reached 000h, the value will not be decremented further. Table 7-5 shows the Decrement command versus the current volatile wiper value. Note: Current Wiper Setting The Decrement command will most commonly be performed on the volatile wiper locations until a desired condition is met. DECREMENT OPERATION VS. VOLATILE WIPER VALUE Decrement Command Operates? Wiper (W) Properties 7-bit Pot 8-bit Pot 7Fh FFh Full Scale (W = A) 7Eh 40h FEh 80 W=N Yes 3Fh 7Fh W = N (Mid Scale) 3Eh 01h 7Eh 01 W=N Yes 00h 00h Zero Scale (W = B) No Refer to Figure 7-8 for the Decrement command sequence. The sequence is terminated by the Stop condition. So when executing a continuous command string, the Decrement command can be followed by any other valid command. This means that writes do not need to be to the same volatile memory address. Note: The command sequence can go from a decrement to any other valid command for the specified address. Fixed Address S 0 1 1 1 Write bit Variable Address 1 A1 A0 0 A Control Byte Device Memory Address Command AD AD AD AD 3 2 1 0 1 0 x x AD AD AD AD A 4 3 2 1 1 0 x x A P (2) DECR command (n-1) Reserved DECR command (n-2) Reserved Note 1: Decrement command (DECR) only functions when accessing the volatile wiper registers (AD3:AD0 = 00h and 01h). 2: This command sequence does not need to terminate (using the Stop bit) and can change to any other desired command sequence (DECR, Read, or Write). FIGURE 7-8: DS20005304A-page 64 I2C Decrement Command Sequence. 2014 Microchip Technology Inc. MCP45HVX1 NOTES: 2014 Microchip Technology Inc. DS20005304A-page 65 MCP45HVX1 8.0 APPLICATIONS EXAMPLES Digital potentiometers have a multitude of practical uses in modern electronic circuits. The most popular uses include precision calibration of set point thresholds, sensor trimming, LCD bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. 8.1 Using Shutdown Modes Figure 8-1 shows a possible application circuit where the independent terminals could be used. Disconnecting the wiper allows the transistor input to be taken to the bias voltage level (disconnecting A and or B may be desired to reduce system current). Disconnecting Terminal A modifies the transistor input by the RBW rheostat value to the Common B. Disconnecting Terminal B modifies the transistor input by the RAW rheostat value to the Common A. The Common A and Common B connections could be connected to V+ and V-. Common A Input A To base of Transistor (or Amplifier) W B Input Common B Balance Bias 8.2 Software Reset Sequence Note: This technique is documented in AN1028. At times, it may become necessary to perform a Software Reset Sequence to ensure the MCP45HVX1 device is in a correct and known I2C Interface state. This technique only resets the I2C state machine. This is useful if the MCP45HVX1 device powers-up in an incorrect state (due to excessive bus noise, etc), or if the master device is reset during communication. Figure 8-2 shows the communication sequence to software reset the device. S ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ S P Nine bits of ‘1’ Start bit Start bit Stop bit FIGURE 8-2: Format. Software Reset Sequence The first Start bit will cause the device to reset from a state in which it is expecting to receive data from the master device. In this mode, the device is monitoring the data bus in Receive mode and can detect the Start bit forces an internal Reset. The nine bits of ‘1’ are used to force a Reset of those devices that could not be reset by the previous Start bit. This occurs only if the MCP45HVX1 is driving an A bit on the I2C bus, or is in Output mode (from a Read command) and is driving a data bit of ‘0’ onto the I2C bus. In both of these cases, the previous Start bit could not be generated due to the MCP45HVX1 holding the bus Low. By sending out nine ‘1’ bits, it is ensured that the device will see an A bit (the master device does not drive the I2C bus Low to acknowledge the data sent by the MCP45HVX1), which also forces the MCP45HVX1 to reset. The second Start bit is sent to address the rare possibility of an erroneous write. This could occur if the master device was reset while sending a Write command to the MCP45HVX1, and then as the master device returns to normal operation and issues a Start condition while the MCP45HVX1 is issuing an Acknowledge. In this case, if the 2nd Start bit is not sent (and the Stop bit was sent) the MCP45HVX1 could initiate a write cycle. M FIGURE 8-1: Example Application Circuit using Terminal Disconnects. Note: The potential for this erroneous write only occurs if the master device is reset while sending a Write command to the MCP45HVX1. The Stop bit terminates the current I2C bus activity. The MCP45HVX1 waits to detect the next Start condition. This sequence does not effect any other I2C devices which may be on the bus, as they should disregard this as an invalid command. DS20005304A-page 66 2014 Microchip Technology Inc. MCP45HVX1 High-Voltage DAC 8.4 A high-voltage DAC can be implemented using the MCP45HVX1, with voltages as high as 36V. The circuit is shown in Figure 8-3. The equation to calculate the voltage output is shown in Equation 8-1. V+ High-Voltage DAC VD D1 V+ + OPA170 - Variable Gain Instrumentation Amplifier A variable gain instrumentation amplifier can be implemented using the MCP45HVX1 along with a highvoltage dual analog switch and a high-voltage instrumentation amplifier. Figure 8-3. The equation to calculate the voltage output is shown in Equation 8-2. MCP45HVX1 ADG1207 S1A DA A S8A B R1 R2 S1B DB V+ MCP45HVx1 8.3 B W AD8221 A VOUT S8B V+ + OPA170 - VOUT FIGURE 8-4: Variable Gain Instrumentation Amplifier for Data Acquisition System. EQUATION 8-2: FIGURE 8-3: High-Voltage DAC. 8-bit EQUATION 8-1: DAC OUTPUT VOLTAGE CALCULATION Gain(N) = 1 + 8-bit VOUT(N) = N 255 x ( VD x ( 1 + R1 )) R2 N = 0 to 255 (decimal) DAC OUTPUT VOLTAGE CALCULATION 49.4 k (N / 255) x RAB N = 0 to 255 (decimal) 7-bit Gain(N) = 1 + 49.4 k (N / 127) x RAB N = 0 to 127 (decimal) 7-bit VOUT(N) = R1 N x ( VD x ( 1 + )) R2 127 N = 0 to 127 (decimal) 2014 Microchip Technology Inc. DS20005304A-page 67 MCP45HVX1 8.5 Audio Volume Control 8.6 A digital volume control can be implemented with the MCP45HVX1. Figure 8-5 shows a simple audio volume control implementation. Figure 8-6 shows a circuit-referenced voltage detect circuit. The output of this circuit could be used to control the Wiper Latch of the MCP45HVX1 device in the Audio Volume control circuit to reduce zipper noise or to update the different channels at the same time. The op amp (U1) could be an MCP6001, while the general purpose comparators (U2 and U3) could be an MCP6541. U4 is a simple AND gate. U1 establishes the signal zero reference. The upper limit of the comparator is set above its offset. The WLAT pin is forced High whenever the voltage falls between 2.502V and 2.497V (a 0.005V window). The ADP1611 is a step-up DC-to-DC switching converter. Using the MCP45HVX1 device allows the power supply to be programmable up to 20V. Figure 8-7 shows a programmable power supply implementation. Equation 8-3 shows the equation to calculate the output voltage of the programmable power supply. This output is derived from the RBW resistance of the MCP45HVX1 device and the R2 resistor. The ADP1611 will adjust its output voltage to maintain 1.23V on the FB pin. When power is connected, L1 acts as a short, and VOUT is a diode drop below the +5V voltage. The VOUT voltage will ramp to the programmed value. The capacitor C1 AC couples the VIN signal into the circuit, before feeding into the windowed comparator (and MCP45HVX1 Terminal A pin). V+ MCP45HVX1 (100 k) V+ A W C1 0.1 µF MCP45HVX1 A VIN Programmable Power Supply IN RT FB B R1 8.5 k + SDA SCL B WLAT C2 10 µF ADP1611 V+ VL GND +5V VOUT - C3 22 nF V- SW SS COMP VOUT R2 220 k C5 10 µF Audio Volume Control. +5V VIN R3 100 k C1 1 µF FIGURE 8-7: Supply. Programmable Power EQUATION 8-3: POWER SUPPLY OUTPUT VOLTAGE CALCULATION +5V + R4 R1 200 k 90 k U2 8-bit U4 +5V R2 10 k +5V U1 D1 C4 150 pF V- FIGURE 8-5: L1 4.7 µF + - FIGURE 8-6: Crossing Detect. DS20005304A-page 68 + U3 R5 100 k WLAT VOUT(N) = 1.23V x ( 1 + ( N * RAB 255 R2 )) N = 0 to 255 (decimal) 7-bit VOUT(N) = 1.23V x ( 1 + ( N * RAB 127 R2 )) N = 0 to 127 (decimal) Referenced Voltage 2014 Microchip Technology Inc. MCP45HVX1 Programmable Bidirectional Current Source 8.8 A programmable bidirectional current source can be implemented with the MCP45HVX1. Figure 8-8 shows an implementation where U1 and U2 work together to deliver the desired current (dependent on selected device) in both directions. The circuit is symmetrical (R1A = R1B, R2A = R2B, R3A = R3B) in order to improve stability. If the resistors are matched, the load current (IL) calculation is shown below: EQUATION 8-4: The MCP45HVX1 can be used for LCD contrast control. Figure 8-9 shows a simple programmable LCD contrast control implementation. Some LCD panels support a fixed power supply of up to 28V. The high-voltage digital potentiometer's wiper can support contrast adjustments through the entire voltage range. D1 LOAD CURRENT (IL) (R2A + R3A) IL = LCD Contrast Control C1 10 µF x VW R1A * R3A uController SDA SCL R1B R2B 150 k 15 k VOUT (LCD Bias) MCP45HVXX 8.7 LCD Panel Fixed (up to +28V) A W +16V to +26V Contrast Adj. B C2 10 pF R3B 50 k +15V FIGURE 8-9: Control. Programmable Contrast U2 + -15V C1 MCP45HVX1 V+ A W B +15V + U1 -15V V- FIGURE 8-8: Current Source. 10 pF R1A R3A 50 k R2A 150 k 14.95 k R4 500 VL IL Programmable Bidirectional 2014 Microchip Technology Inc. DS20005304A-page 69 MCP45HVX1 8.9 Implementing Log Steps with a Linear Digital Potentiometer In audio volume control applications, the use of logarithmic steps is desirable since the human ear hears in a logarithmic manner. The use of a linear potentiometer can approximate a log potentiometer, but with fewer steps. An 8-bit potentiometer can achieve fourteen 3 dB log steps plus a 100% (0 dB) and a mute setting. Figure 8-10 shows a block diagram of one of the MCP45HVx1 resistor networks being used to attenuate an input signal. In this case, the attenuation will be ground referenced. Terminal B can be connected to a Common mode voltage, but the voltages on the A, B and wiper terminals must not exceed the MCP45HVx1’s V+/V- voltage limits. MCP45HVX1 P0A P0W EQUATION 8-5: dB CALCULATIONS (VOLTAGE) L = 20 * log10 (VOUT / VIN) dB -3 -2 -1 EQUATION 8-6: VOUT / VIN Ratio 0.70795 0.79433 0.89125 dB CALCULATIONS (RESISTANCE) – CASE 1 Terminal B connected to Ground (see Figure 8-10) L = 20 * log10 (RBW / RAB) EQUATION 8-7: dB CALCULATIONS (RESISTANCE) – CASE 2 Terminal B through RB2GND to Ground L = 20 * log10 ( (RBW + RB2GND) / (RAB + RB2GND) ) P0B FIGURE 8-10: Signal Attenuation Block Diagram – Ground Referenced. Equation 8-5 shows the equation to calculate voltage dB gain ratios for the digital potentiometer, while Equation 8-6 shows the equation to calculate resistance dB gain ratios. These two equations assume that the B terminal is connected to ground. If Terminal B is not directly resistively connected to ground, then this Terminal B to ground resistance (RB2GND) must be included into the calculation. Equation 8-7 shows this equation. DS20005304A-page 70 Table 8-1 shows the codes that can be used for 8-bit digital potentiometers to implement the log attenuation. The table shows the wiper codes for -3 dB, -2 dB, and -1 dB attenuation steps. This table also shows the calculated attenuation based on the wiper code’s linear step. Calculated attenuation values less than the desired attenuation are shown with red text. At lower wiper code values, the attenuation may skip a step. If this occurs, the next attenuation value is colored magenta to highlight that a skip occurred. For example, in the -3 dB column the -48 dB value is highlighted since the -45 dB step could not be implemented (there are no wiper codes between 2 and 1). 2014 Microchip Technology Inc. MCP45HVX1 TABLE 8-1: LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS -3 dB Steps # of Steps -2 dB Steps -1 dB Steps Calculated Calculated Calculated Desired Wiper Desired Wiper Desired Wiper Attenuation Attenuation Attenuation Attenuation Code Attenuation Code Attenuation Code (1) (1) (1) 0 0 dB 255 0 dB 0 dB 255 0 dB 0 dB 255 0 dB 1 -3 dB 180 -3.025 dB -2 dB 203 -1.981 dB -1 dB 227 -1.010 dB 2 -6 dB 128 -5.987 dB -4 dB 161 -3.994 dB -2 dB 203 -1.981 dB 3 -9dB 90 -9.046 dB -6 dB 128 -5.987 dB -3 dB 180 -3.025 dB 4 -12 dB 64 -12.007 dB -8 dB 101 -8.044 dB -4 dB 161 -3.994 dB 5 -15 dB 45 -15.067 dB -10 dB 81 -9.961 dB -5 dB 143 -5.024 dB 6 -18 dB 32 -18.028 dB -12 dB 64 -12.007 dB -6 dB 128 -5.987 dB 7 -21 dB 23 -20.896 dB -14 dB 51 -13.979 dB -7 dB 114 -6.993 dB 8 -24 dB 16 -24.048 dB -16 dB 40 -16.090 dB -8 dB 101 -8.044 dB 9 -27 dB 11 -27.303 dB -18 dB 32 -18.028 dB -9 dB 90 -9.046 dB 10 -30 dB 8 -30.069 dB -20 dB 25 -20.172 dB -10 dB 81 -9.961 dB 11 -33 dB 6 -32.568 dB -22 dB 20 -22.110 dB -11 dB 72 -10.984 dB 12 -36 dB 4 -36.090 dB -24 dB 16 -24.048 dB -12 dB 64 -12.007 dB 13 -39 dB 3 -38.588 dB -26 dB 13 -25.852 dB -13 dB 57 -13.013 dB 14 -42 dB 2 -42.110 dB -28 dB 10 -28.131 dB -14 dB 51 -13.979 dB 15 -48 dB 1 -48.131 dB -30 dB 8 -30.069 dB -15 dB 45 -15.067 dB 16 Mute 0 Mute -32 dB 6 -32.602 dB -16 dB 40 -16.090 dB 17 -34 dB 5 -34.151 dB -17 dB 36 -17.005 dB 18 -36 dB 4 -36.090 dB -18 dB 32 -18.028 dB 19 -38 dB 3 -38.588 dB -19 dB 29 -18.883 dB 20 -42 dB 2 -42.110 dB -20 dB 25 -20.172 dB 21 -48 dB 1 -48.131 dB -21 dB 23 -20.896 dB 22 Mute 0 Mute -22 dB 20 -22.110 dB 23 -23 dB 18 -23.025 dB 24 -24 dB 16 -24.048 dB 25 -25 dB 14 -25.208 dB 26 -26 dB 13 -25.852 dB 27 -27dB 11 -27.303 dB 28 -28 dB 10 -28.131 dB 29 -29 dB 9 -29.046 dB 30 -30 dB 8 -30.069 dB 31 -31 dB 7 -31.229 dB 32 -33 dB 6 -32.568 dB 33 -34 dB 5 -34.151 dB 34 -36 dB 4 -36.090 dB 35 -39 dB 3 -38.588 dB 36 -42 dB 2 -42.110 dB 37 -48 dB 1 -48.131 dB 38 Mute 0 Mute Legend: Calculated Attenuation Value Color Code: Black -> Above Target Value; Red -> Below Target Value Desired Attenuation Value Color Code: Magenta -> Skipped Desired Attenuation Value(s). Note 1: Attenuation values do not include errors from digital potentiometer errors, such as Full-Scale Error or ZeroScale Error. 2014 Microchip Technology Inc. DS20005304A-page 71 MCP45HVX1 8.10 Figure 8-11 shows two I2C bus configurations. In many cases, the single I2C bus configuration will be adequate. For applications that do not want all the MCP45HVX1 devices to do General Call support or have a conflict with General Call commands, the multiple I2C bus configuration would be used. Using the General Call Command The use of the General Call Address Increment, Decrement, or Write commands is analogous to the “Load” feature (LDAC pin) on some DACs (such as the MCP4921). This allows all the devices to “Update” the output level “at the same time”. For some applications, the ability to update the wiper values “at the same time” may be a requirement, since the delay from writing to one wiper value and then the next may cause application issues. A possible example would be a “tuned” circuit that uses several MCP45HVX1 in rheostat configuration. As the system condition changes (temperature, load, etc.) these devices need to be changed (incremented/decremented) to adjust for the system change. These changes will either be in the same direction or in opposite directions. With the Potentiometer device, the customer can either select the PxB terminals (same direction) or the PxA terminal(s) (opposite direction). Single I2C™ Bus Configuration Device 1 Host Controller Device 4 Device 2 Multiple I2C Bus Configuration Device 1a Device 3a Device na Host Bus a Controller Figure 8-12 shows that the update of six devices takes 6*TI2CDLY time in “normal” operation, but only 1*TI2CDLY time in “General Call” operation. Note: Device n Device 3 Device 4a Device 2a The application system may need to partition the I2C bus into multiple buses to ensure that the MCP45HVX1 General Call commands do not conflict with the General Call commands that the other I2C devices may have defined. Also, if only a portion of the MCP45HVX1 devices are to require this synchronous operation, then the devices that should not receive these commands should be on the second I2C bus. Device 1b Device 3b Device nb Bus b Device 4b Device 2b Device 1n Device 3n Device nn Bus n Device 2n FIGURE 8-11: Configurations. Device 4n Typical Application I2C Bus Normal Operation INC POT01 TI2CDLY INC POT02 TI2CDLY INC POT03 TI2CDLY INC POT04 TI2CDLY INC POT05 TI2CDLY INC POT06 TI2CDLY General Call Operation INC POTs 01-06 TI2CDLY INC POTs 01-06 TI2CDLY INC POTs 01-06 TI2CDLY INC POTs 01-06 TI2CDLY INC POTs 01-06 TI2CDLY INC POTs 01-06 TI2CDLY TI2CDLY = Time from one I2C command completed to completing the next I2C command. FIGURE 8-12: Updates. DS20005304A-page 72 Example Comparison of “Normal Operation” vs. “General Call Operation” Wiper 2014 Microchip Technology Inc. MCP45HVX1 8.11 8.11.2 Design Considerations LAYOUT CONSIDERATIONS In the design of a system with the MCP45HVX1 devices, the following considerations should be taken into account: In the design of a system with the MCP45HVX1 devices, the following layout considerations should be taken into account: • Power Supply Considerations • Layout Considerations • Noise • PCB Area Requirements • Power Dissipation 8.11.2.1 In this example, the recommended bypass capacitor value is 0.1 µF. This capacitor should be placed as close (within 4 mm) to the device power pin (VL) as possible. The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, V+ and Vshould reside on the analog plane. VDD 0.1 µF VL V+ DGND FIGURE 8-13: Connections. PCB Area Requirements In some applications, PCB area is a criteria for device selection. Table 8-2 shows the package dimensions and area for the different package options. The table also shows the relative area factor compared to the smallest area. For space critical applications, the QFN package would be the suggested package. PACKAGE FOOTPRINT (1) Package SDA SCL V- PIC® Microcontroller MCP45HVXX B 8.11.2.2 TABLE 8-2: V- W If low noise is desired, breadboards and wire-wrapped boards are not recommended. 0.1 µF 0.1 µF A Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP45HVX1’s performance. Careful board layout minimizes these effects and increases the Signal-to-Noise Ratio (SNR). Multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals. Package Footprint Dimensions (mm) Type Code X Y Relative Area The typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply’s traces. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 8-13 illustrates an appropriate bypass strategy. Noise Area (mm2) POWER SUPPLY CONSIDERATIONS Pins 8.11.1 14 TSSOP ST 5.10 6.40 32.64 1.31 20 QFN MQ 5.00 5.00 25.00 1 Note 1: Does not include recommended land pattern dimensions. VSS Typical Microcontroller 2014 Microchip Technology Inc. DS20005304A-page 73 MCP45HVX1 8.11.3 RESISTOR TEMPCO Characterization curves of the resistor temperature coefficient (tempco) are shown in the device characterization graphs. These curves show that the resistor network is designed to correct for the change in resistance as temperature increases. This technique reduces the end-to-end change in RAB resistance. 8.11.3.1 Power Dissipation The power dissipation of the high-voltage digital potentiometer will most likely be determined by the power dissipation through the resistor networks. Table 8-3 shows the power dissipation through the resistor ladder (RAB) when Terminal A = +18V and Terminal B = -18V. This is not the worst-case power dissipation based on the 25 mA terminal current specification. Table 8-3 shows the worst-case current (per resistor network), which is independent of the RAB value). DS20005304A-page 74 TABLE 8-3: RAB POWER DISSIPATION RAB Resistance () Typical Min Max | VA | + |VB | Power = (mW) (1) (V) 5,000 4,000 6,000 36 324 10,000 8,000 12,000 36 162 50,000 40,000 60,000 36 32.4 100,000 80,000 120,000 36 16.2 Note 1: Power = V * I = V2/RAB(MIN). TABLE 8-4: RAB () (Typical) RBW POWER DISSIPATION | VW | + |VB | = (V) IBW (2) (mA) Power (mW) (1) 5,000 36 25 900 10,000 36 12.5 450 50,000 36 6.5 234 100,000 36 6.5 234 Note 1: 2: Power = V * I. See Electrical Specifications (max IW). 2014 Microchip Technology Inc. MCP45HVX1 NOTES: 2014 Microchip Technology Inc. DS20005304A-page 75 MCP45HVX1 9.0 DEVICE OPTIONS 9.1 Standard Options 9.1.1 9.2 Custom options can be made available. 9.2.1 POR/BOR WIPER SETTING The default wiper setting (mid scale) is indicated by the customer in three digit suffix: -202, -502, -103 and -503. Table 9-1 indicates the device’s default settings. Typical RAB Value Package Code TABLE 9-1: DEFAULT POR/BOR WIPER SETTING SELECTION Default Device Wiper POR Wiper Resolution Code Setting 5.0 k -502 Mid scale 8-bit 7-bit 3Fh 10.0 k -103 Mid scale 8-bit 7Fh 7-bit 3Fh 50.0 k -503 Mid scale 8-bit 7Fh 7-bit 3Fh 100.0 k -104 Mid scale 8-bit 7Fh 7-bit 3Fh DS20005304A-page 76 Custom Options 7Fh CUSTOM WIPER VALUE ON POR/ BOR EVENT Customers can specify a custom wiper setting via the Non-Standard Customer Authorization Request (NSCAR) process. Note 1: Non-Recurring Engineering (NRE) charges and minimum ordering requirements for custom orders. Please contact Microchip sales for additional information. 2: A custom device will be assigned custom device marking. 2014 Microchip Technology Inc. MCP45HVX1 NOTES: 2014 Microchip Technology Inc. DS20005304A-page 77 MCP45HVX1 10.0 DEVELOPMENT SUPPORT 10.1 Development Tools 10.2 Several development tools are available to assist in your design and evaluation of the MCP45HVX1 devices. The currently available tools are shown in Table 10-1. Technical Documentation Several additional technical documents are available to assist you in your design and development. These technical documents include Application Notes, Technical Briefs and Design Guides. Table 10-2 shows some of these documents. Figure 10-1 shows how the TSSOP20EV bond-out PCB can be populated to easily evaluate the MCP45HVX1 devices. Evaluation can use the PICkit™ Serial Analyzer to control the position of the volatile wiper and state of the TCON register. Figure 10-2 shows how the SOIC14EV bond-out PCB can be populated to evaluate the MCP45HVX1 devices. The use of the PICkit Serial Analyzer would require blue wire since the header H1 is not compatibly connected. These boards may be purchased directly from the Microchip web site at www.microchip.com. TABLE 10-1: DEVELOPMENT TOOLS Board Name Part # Comment 20-pin TSSOP and SSOP Evaluation Board TSSOP20EV Can easily interface to PICkit™ Serial Analyzer (Order #: DV164122) 14-pin SOIC/TSSOP/DIP Evaluation Board SOIC14EV TABLE 10-2: TECHNICAL DOCUMENTATION Application Note Number Title Literature # TB3073 Implementing a 10-bit Digital Potentiometer with an 8-bit Digital Potentiometer DS93073 AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316 AN1080 Understanding Digital Potentiometers Resistor Variations DS01080 AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737 AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692 AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691 AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219 — Digital Potentiometer Design Guide DS22017 — Signal Chain Design Guide DS21825 — Analog Solutions for Automotive Applications Design Guide DS01005 DS20005304A-page 78 2014 Microchip Technology Inc. MCP45HVX1 MCP45HVX1-xxxE/ST installed in U3 (bottom 14 pins of TSSOP-20 footprint) Connected to Digital Ground (DGND) Plane Connected to Digital Power (VL) Plane 1.0 µF SCL A1 SDA A0 WLAT SHDN 0 V+ 4.7k 4.7k P0A 45HVx1 VL P0B 4.7k V- 4.7k 0 Four blue wire jumpers to connect PICkit™ Serial interface (I2C™) to device pins FIGURE 10-1: P0W 4.7k 4.7k P0A pin shorted (jumpered) to V+ pin Through-hole Test Point (Orange) Wiper 0 P0B pin shorted (jumpered) to V- pin DGND NC 1x6 male header, with 90° right angle Digital Potentiometer Evaluation Board Circuit Using TSSOP20EV. 2014 Microchip Technology Inc. DS20005304A-page 79 V+ 0 VL MCP45HVX1 1.0 µF P0A P0W 4.7k P0B MCP45HVX1 A1 4.7k SDA 4.7k SCL P0A pin shorted (jumpered) to V+ pin VDGND NC WLAT SHDN 0 4.7k DS20005304A-page 80 4.7k FIGURE 10-2: 4.7k A0 P0B pin shorted (jumpered) to V- pin Digital Potentiometer Evaluation Board Circuit Using SOIC14EV. 2014 Microchip Technology Inc. MCP45HVX1 NOTES: 2014 Microchip Technology Inc. DS20005304A-page 81 MCP45HVX1 11.0 PACKAGING INFORMATION 11.1 Package Marking Information Example 14-Lead TSSOP (4.4 mm) XXXXXXXX XYWW YYWW NNN 45H51502 E416 256 Part Number Code Part Number Code MCP45HV51-502E/ST 45H51502 MCP45HV31-502E/ST 45H31502 MCP45HV51-103E/ST 45H51103 MCP45HV31-103E/ST 45H31103 MCP45HV51-503E/ST 45H51503 MCP45HV31-503E/ST 45H31503 MCP45HV51-104E/ST 45H51104 MCP45HV31-104E/ST 45H31104 20-Lead QFN (5x5x0.9 mm) Example PIN 1 PIN 1 45HV31 502E/MQ e3 1416256 Part Number Code Part Number Code MCP45HV51-502E/MQ 502E/MQ MCP45HV31-502E/MQ 502E/MQ MCP45HV51-103E/MQ 103E/MQ MCP45HV31-103E/MQ 103E/MQ MCP45HV51-503E/MQ 503E/MQ MCP45HV31-503E/MQ 503E/MQ MCP45HV51-104E/MQ 104E/MQ MCP45HV31-104E/MQ 104E/MQ Legend: XX...X Y YY WW NNN e3 * Note: DS20005304A-page 82 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code RoHS Compliant JEDEC® designator for Matte Tin (Sn) This package is RoHS Compliant. The RoHS Compliant JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2014 Microchip Technology Inc. MCP45HVX1 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014 Microchip Technology Inc. DS20005304A-page 83 MCP45HVX1 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005304A-page 84 2014 Microchip Technology Inc. MCP45HVX1 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014 Microchip Technology Inc. DS20005304A-page 85 MCP45HVX1 20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-120A DS20005304A-page 86 2014 Microchip Technology Inc. MCP45HVX1 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2014 Microchip Technology Inc. DS20005304A-page 87 MCP45HVX1 DS20005304A-page 88 2014 Microchip Technology Inc. MCP45HVX1 APPENDIX A: REVISION HISTORY Revision A (June 2014) • Original Release of this Document. APPENDIX B: TERMINOLOGY This appendix discusses the terminology used in this document and it also describes how a parameter is measured. B.1 Potentiometer (Voltage Divider) The potentiometer configuration is when all three terminals of the device are tied to different nodes in the circuit. This allows the potentiometer to output a voltage proportional to the input voltage. This configuration is sometimes called Voltage Divider mode. The potentiometer is used to provide a variable voltage by adjusting the wiper position between the two endpoints as shown in Figure B-1. Reversing the polarity of the A and B terminals will not affect operation. V1 A V3 W B V2 FIGURE B-1: POTENTIOMETER CONFIGURATION. The temperature coefficient of the RAB resistors is minimal by design. In this configuration, the resistors all change uniformly, so minimal variation should be seen. B.2 Rheostat (Variable Resistor) The rheostat configuration is when two of the three digital potentiometer’s terminals are used as a resistive element in the circuit. With Terminal W (wiper) and either Terminal A or Terminal B, a variable resistor is created. The resistance will depend on the tap setting of the wiper (and the wiper’s resistance). The resistance is controlled by changing the wiper setting. Figure B-2 shows the two possible resistors that can be used. Reversing the polarity of the A and B terminals will not affect operation. A W RAW or RBW B Resistor FIGURE B-2: RHEOSTAT CONFIGURATION. 2014 Microchip Technology Inc. DS20005304A-page 89 MCP45HVX1 B.3 EQUATION B-2: Resolution The resolution is the number of wiper output states that divide the full-scale range. For the 8-bit digital potentiometer, the resolution is 28, meaning the digital potentiometer wiper code ranges from 0 to 255. B.4 Step Resistance (RS) The resistance Step size (RS) equates to one LSb of the resistor ladder. Equation B-1 shows the calculation for the step resistance (RS). EQUATION B-1: Ideal RS(Ideal) = RS CALCULATION RAB 2N -1 or (VA - VB) / IAB 2N -1 Measured RS(Measured) = (VW(@FS) - VW(@ZS)) / IAB 2N -1 where: 2N - 1 = 255 (MCP45HV51/61) = 127 (MCP45HV31/41) VA = Voltage on Terminal A pin VB = Voltage on Terminal B pin IAB = Measured Current through A and B pins VW(@FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh) VW(@ZS) = Measured Voltage on W pin at Zero-Scale code (00h) B.5 Wiper Resistance Wiper resistance is the series resistance of the analog switch that connects the selected resistor ladder node to the Wiper terminal common signal (see Figure 5-1). A value in the volatile Wiper register selects which analog switch to close, connecting the W terminal to the selected node of the resistor ladder. The resistance is dependent on the voltages on the analog switch source, gate, and drain nodes, as well as the device’s wiper code, temperature, and the current through the switch. As the device voltage decreases, the wiper resistance increases. The wiper resistance is measured by forcing a current through the W and B terminals (IWB) and measuring the voltage on the W and A terminals (VW and VA). Terminal A is not biased. Equation B-2 shows how to calculate this resistance. DS20005304A-page 90 RW(Measured) = RW CALCULATION (VW - VA) IWB where: VA = Voltage on Terminal A pin VW = Voltage on Terminal W pin IWB = Measured current through W and B pins The wiper resistance in potentiometer-generated voltage divider applications is not a significant source of error (it does not affect the output voltage seen on the W pin). The wiper resistance in rheostat applications can create significant nonlinearity as the wiper is moved toward zero scale (00h). The lower the nominal resistance, the greater the possible error. B.6 RZS Resistance The analog switch between the resistor ladder and the Terminal B pin introduces a resistance, which we call the Zero-Scale resistance (RZS). Equation B-3 shows how to calculate this resistance. EQUATION B-3: RZS(Measured) = RZS CALCULATION (VW(@ZS) - VB) IAB where: VW(@ZS) = Voltage on Terminal W pin at Zero-Scale wiper code VB = Voltage on Terminal B pin IWB = Measured Current through A and B pins B.7 RFS Resistance The analog switch between the resistor ladder and the Terminal A pin introduces a resistance, which we call the Full-Scale resistance (RFS). Equation B-4 shows how to calculate this resistance. EQUATION B-4: RFS(Measured) = RFS CALCULATION (VA - VW(@FS)) IAB where: VA = Voltage on Terminal A pin VW(@FS) = Voltage on Terminal W pin at Full-Scale wiper code IWB = Measured Current through A and B pins 2014 Microchip Technology Inc. MCP45HVX1 B.8 Least Significant Bit (LSb) This is the difference between two successive codes (either in resistance or voltage). For a given output range it is divided by the resolution of the device (Equation B-5). EQUATION B-5: B.9 Monotonic operation means that the device’s output (resistance (RBW) or voltage (VW)) increases with every one code step (LSb) increment of the Wiper register. LSb CALCULATION 2N -1 2N - 1 Measured LSb(Measured) = (VW(@FS) - VW(@ZS)) / IAB 2N - 1 0x3E VW(@FS) - VW(@ZS) VS3 0x03 VS1 0x02 0x01 VS0 0x00 2N - 1 where: 2N - 1 = 255 (MCP45HV51) = 127 (MCP45HV31) VA = Voltage on Terminal A pin VB = Voltage on Terminal B pin VAB = Measured Voltage between A and B pins IAB = Measured Current through A and B pins VW(@FS) = Measured Voltage on W pin at Full-Scale code (FFh or 7Fh) VW(@ZS) = Measured Voltage on W pin at Zero-Scale code (00h) VS63 0x3F Wiper Code LSb(Ideal) = In Voltage VA - VB VS64 0x40 Ideal In Resistance RAB Monotonic Operation VW (@ tap) n=? VW = VSn + VZS(@ Tap 0) n=0 Voltage (VW ~= VOUT) FIGURE B-3: THEORETICAL VW OUTPUT VS CODE (MONOTONIC OPERATION). RS63 0x3F RS62 Digital Input Code 0x3E 0x3D RS3 0x03 RS1 0x02 0x01 0x00 RS0 RW (@ tap) n=? RBW = RSn + RW(@ Tap n) n=0 Resistance (RBW) FIGURE B-4: THEORETICAL RBW OUTPUT VS CODE (MONOTONIC OPERATION). 2014 Microchip Technology Inc. DS20005304A-page 91 MCP45HVX1 B.10 Full-Scale Error (EFS) B.11 The Full-Scale Error (see Figure B-5) is the error of the VW pin relative to the expected VW voltage (theoretical) for the maximum device wiper register code (code FFh for 8-bit and code 7Fh for 7-bit), see Equation B-6. The error is defined with no resistive load on the P0W pin. The error in bits is determined by the theoretical voltage step size to give an error in LSb. Note: Analog switch leakage increases with temperature. This leakage increases substantially at higher temperatures (> ~100°C). As analog switch leakage increases, the full-scale output value decreases, which increases the FullScale Error. EQUATION B-6: The Zero-Scale Error (see Figure B-6) is the difference between the ideal and measured VOUT voltage with the Wiper register code equal to 00h (Equation B-7). The error is defined with no resistive load on the P0W pin. The error in bits is determined by the theoretical voltage step size to give an error in LSb. VLSb(IDEAL) Where: EFS is expressed in LSb VW@FS) is the VW voltage when the Wiper register code is at Full-scale. VIDEAL(@FS) is the ideal output voltage when the Wiper register code is at Full-scale. Analog switch leakage increases with temperature. This leakage increases substantially at higher temperatures (> ~100°C). As analog switch leakage increases the zero-scale output value decreases, which decreases the ZeroScale Error. Note: EQUATION B-7: FULL-SCALE ERROR VW(@FS) - VA EFS = Zero-Scale Error (EZS) EZS = ZERO SCALE ERROR VW@ZS) VLSb(IDEAL) Where: EFS is expressed in LSb VW@ZS) is the VW voltage when the Wiper register code is at Zero-scale. VLSb(IDEAL) is the theoretical voltage step size. VLSb(IDEAL) is the theoretical voltage step size. VW VA VFS VA VFS VW Actual Transfer Function VZS VB Full-Scale Error (EFS) Ideal Transfer Function 0 Full-Scale VZS VB 0 Zero-Scale Error (EZS) FIGURE B-6: EXAMPLE. Actual Transfer Function Ideal Transfer Function Full-Scale Wiper Code ZERO-SCALE ERROR Wiper Code FIGURE B-5: EXAMPLE. DS20005304A-page 92 FULL-SCALE ERROR 2014 Microchip Technology Inc. MCP45HVX1 B.12 Integral Nonlinearity (P-INL) Potentiometer Configuration The Potentiometer Integral nonlinearity (P-INL) error is the maximum deviation of an actual VW transfer function from an ideal transfer function (straight line). In the MCP45HVX1, P-INL is calculated using the zeroscale and full-scale wiper code end points. P-INL is expressed in LSb. P-INL is also called relative accuracy. Equation B-8 shows how to calculate the PINL error in LSb and Figure B-7 shows an example of P-INL accuracy. Positive P-INL means higher VW voltage than ideal. Negative P-INL means lower VW voltage than ideal. Note: Analog switch leakage increases with temperature. This leakage increases substantially at higher temperatures (> ~100°C). As analog switch leakage increases, the Wiper output voltage (VW) decreases, which affects the INL Error. EQUATION B-8: EINL = P-INL ERROR ( VW(@Code) - ( VLSb(Measured) * Code )) VLSb(Measured) Where: Differential Nonlinearity (P-DNL) Potentiometer Configuration The Potentiometer Differential nonlinearity (P-DNL) error (see Figure B-8) is the measure of VW step size between codes. The ideal step size between codes is 1 LSb. A P-DNL error of zero would imply that every code is exactly 1 LSb wide. If the P-DNL error is less than 1 LSb, the digital potentiometer guarantees monotonic output and no missing codes. The P-DNL error between any two adjacent codes is calculated in Equation B-9. P-DNL error is the measure of variations in code widths from the ideal code width. Note: Analog switch leakage increases with temperature. This leakage increases substantially at higher temperatures (> ~100°C). As analog switch leakage increases, the Wiper output voltage (VW) decreases, which affects the DNL Error. EQUATION B-9: P-DNL ERROR - VW(code = n) ) - VLSb(Measured) ) (V EDNL = W(code = n+1) VLSb(Measured) Where: INL is expressed in LSb. Code = Wiper Register Value VW(@Code) = The measured VW output voltage with a given Wiper register code VLSb = For Ideal: VAB / Resolution For Measured: (VW(@FS) - VW(@ZS)) / 255 INL < 0 110 DNL is expressed in LSb. VW(Code = n) = The measured VW output voltage with a given Wiper register code. VLSb = For Ideal: VAB / Resolution For Measured: (VW(@FS) - VW(@ZS)) / # of RS 111 111 Actual transfer function 110 101 101 Wiper Code B.13 Actual transfer function Wiper 100 Code 011 100 011 Ideal transfer function 010 010 Wide code, > 1 LSb 001 001 000 000 INL < 0 VW Output Voltage FIGURE B-7: Ideal transfer function P-INL ACCURACY. 2014 Microchip Technology Inc. Narrow code < 1 LSb VW Output Voltage FIGURE B-8: P-DNL ACCURACY. DS20005304A-page 93 MCP45HVX1 B.14 Integral Nonlinearity (R-INL) Rheostat Configuration The Rheostat Integral nonlinearity (R-INL) error is the maximum deviation of an actual RBW transfer function from an ideal transfer function (straight line). In the MCP45HVX1, INL is calculated using the ZeroScale and Full-Scale wiper code end points. R-INL is expressed in LSb. R-INL is also called relative accuracy. Equation B-10 shows how to calculate the RINL error in LSb and Figure B-9 shows an example of R-INL accuracy. Positive R-INL means higher VOUT voltage than ideal. Negative R-INL means lower VOUT voltage than ideal. EQUATION B-10: EINL = R-INL ERROR ( RBW(@code) - RBW(Ideal) ) RLSb(Ideal) B.15 Differential Nonlinearity (R-DNL) Rheostat Configuration The Rheostat Differential nonlinearity (R-DNL) error (see Figure B-10) is the measure of RBW step size between codes in actual transfer function. The ideal step size between codes is 1 LSb. A R-DNL error of zero would imply that every code is exactly 1 LSb wide. If the R-DNL error is less than 1 LSb, the RBW Resistance guarantees monotonic output and no missing codes. The R-DNL error between any two adjacent codes is calculated in Equation B-11. R-DNL error is the measure of variations in code widths from the ideal code width. A R-DNL error of zero would imply that every code is exactly 1 LSb wide. EQUATION B-11: R-DNL ERROR EDNL = ( RBW(code = n+1) - RBW(code = n) ) - RLSb(Measured) ) Where: INL is expressed in LSb. RBW(Code = n) = The measured RBW resistance with a given wiper register code RLSb = For Ideal: RAB / Resolution For Measured: RBW(@FS) / # of RS INL < 0 RLSb(Measured) Where: DNL is expressed in LSb. RBW(Code = n) = The measured RBW resistance with a given wiper register code RLSb = For Ideal: RAB / Resolution For Measured: RBW(@FS) / # of RS 111 110 Actual transfer function 111 101 Wiper Code 110 100 011 010 101 Ideal transfer function Actual transfer function Wiper 100 Code 011 010 001 INL < 0 000 RBW Resistance R-INL ACCURACY. Narrow code < 1 LSb RBW Resistance FIGURE B-10: DS20005304A-page 94 Wide code, > 1 LSb 001 000 FIGURE B-9: Ideal transfer function R-DNL ACCURACY. 2014 Microchip Technology Inc. MCP45HVX1 B.16 Total Unadjusted Error (ET) The Total Unadjusted Error (ET) is the difference between the ideal and measured VW voltage. Typically, calibration of the output voltage is implemented to improve system performance. The error in bits is determined by the theoretical voltage step size to give an error in LSb. Equation B-12 shows the Total Unadjusted Error calculation. Note: Analog switch leakage increases with temperature. This leakage increases substantially at higher temperatures (> ~100°C). As analog switch leakage increases, the Wiper output voltage (VW) decreases, which affects the Total Unadjusted Error. EQUATION B-12: ET = TOTAL UNADJUSTED ERROR CALCULATION ( VW_Actual(@code) - VW_Ideal(@Code) ) VLSb(Ideal) Where: ET is expressed in LSb. VW_Actual(@code) = The measured W pin output voltage at the specified code VW_Ideal(@code) = The calculated W pin output voltage at the specified code ( code * VLSb(Ideal) ) VLSb(Ideal) = VAB / # RS 8-bit = VAB / 255 7-bit = VAB / 127 B.17 Settling Time The settling time is the time delay required for the VW voltage to settle into its new output value. This time is measured from the start of code transition, to when the VW voltage is within the specified accuracy. It is related to the RC characteristics of the resistor ladder and wiper switches. In the MCP45HVX1, the settling time is a measure of the time delay until the VW voltage reaches within 0.5 LSb of its final value, when the volatile Wiper register changes from zero scale to full scale (or full scale to zero scale). 2014 Microchip Technology Inc. B.18 Major-Code Transition Glitch Major-code transition glitch is the impulse energy injected into the wiper pin when the code in the Wiper register changes state. It is normally specified as the area of the glitch in nV-Sec, and is measured when the digital code is changed by 1 LSb at the major carry transition (Example: 01111111 to 10000000, or 10000000 to 01111111). B.19 Digital Feedthrough The digital feedthrough is the glitch that appears at the analog output caused by coupling from the digital input pins of the device. The area of the glitch is expressed in nV-Sec, and is measured with a full-scale change (Example: all 0s to all 1s and vice versa) on the digital input pins. The digital feedthrough is measured when the digital potentiometer is not being written to the output register. B.20 Power-Supply Sensitivity (PSS) PSS indicates how the output (VW or RBW) of the digital potentiometer is affected by changes in the supply voltage. PSS is the ratio of the change in VW to a change in VL for mid-scale output of the digital potentiometer. The VW is measured while the VL is varied from 5.5V to 2.7V as a step, and expressed in %/%, which is the % change of the VW output voltage with respect to the % change of the VL voltage. EQUATION B-13: PSS = PSS CALCULATION ( VW(@5.5V) - VW(@2.7V) ) / VW(@5.5V) ) (5.5V - 2.7V) / 5.5V Where: PSS is expressed in %/%. VW(@5.5V) = The measured VW output voltage with VL = 5.5V VW(@2.7V) = The measured VW output voltage with VL = 2.7V B.21 Power-Supply Rejection Ratio (PSRR) PSRR indicates how the output of the digital potentiometer is affected by changes in the supply voltage. PSRR is the ratio of the change in VW to a change in VL for fullscale output of the digital potentiometer. The VW is measured while the VL is varied +/- 10% (VA and VB voltages held constant), and expressed in dB or µV/V. DS20005304A-page 95 MCP45HVX1 B.22 Ratiometric Temperature Coefficient B.24 -3dB Bandwidth The ratiometric temperature coefficient quantifies the error in the ratio RAW/RWB due to temperature drift. This is typically the critical error when using a digital potentiometer in a voltage divider configuration. This is the frequency of the signal at the A terminal, that causes the voltage at the W pin to be -3dB from its expected value, based on its wiper code. The expected value is determined by the static voltage value on the A terminal and the wiper code value. B.23 B.25 Absolute Temperature Coefficient The absolute temperature coefficient quantifies the error in the end-to-end resistance (Nominal resistance RAB) due to temperature drift. This is typically the critical error when using the device in an adjustable resistor configuration. Resistor Noise Density (eN_WB) This is the random noise generated by the device’s internal resistances. It is specified as a spectral density (voltage per square root Hertz). Characterization curves of the resistor temperature coefficient (tempco) are shown in Section 2.0 “Typical Performance Curves”. DS20005304A-page 96 2014 Microchip Technology Inc. MCP45HVX1 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) Device Tape and Reel Option Device: XXX X /XX Resistance Temperature Package Version Range Examples: a) MCP45HV51T-502E/ST 5 k, 8-bit, 14-LD TSSOP b) MCP45HV51T-103E/ST 10 k, 8-bit, 14-LD TSSOP MCP45HV31: Single Potentiometer (7-bit) with I2C™ Interface c) MCP45HV31T-503E/ST 50 k, 7-bit, 14-LD TSSOP MCP45HV51: Single Potentiometer (8-bit) with I2C Interface d) MCP45HV31T-104E/MQ 100 k, 7-bit, 20-LD QFN (5x5) a) MCP45HV51T-502E/MQ 5 k, 8-bit, 20-LD QFN (5x5) b) MCP45HV51T-103E/MQ 10 k, 8-bit, 20-LD QFN (5x5) c) MCP45HV31T-503E/MQ 50 k, 7-bit, 20-LD QFN (5x5) d) MCP45HV31T-104E/MQ 100 k, 7-bit, 20-LD QFN (5x5) Tape and Reel Option: T = Tape and Reel(1) “blank” = Tube Resistance Version: 502 = 5 k 103 = 10 k 503 = 50 k 104 = 100 k Temperature Range: E = -40°C to +125°C Package: ST = Plastic TSSOP-14, 14-lead MQ = Plastic QFN-20 (5x5), 20-lead 2014 Microchip Technology Inc. Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DS20005304A-page 97 MCP45HVX1 NOTES: DS20005304A-page 98 2014 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. 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