MCP453X/455X/463X/465X
7/8-Bit Single/Dual I2C Digital POT with
Volatile Memory
Features:
Description:
• Single or Dual Resistor Network Options
• Potentiometer or Rheostat Configuration Options
• Resistor Network Resolution
- 7-bit: 128 Resistors (129 Steps)
- 8-bit: 256 Resistors (257 Steps)
• RAB Resistances Options of:
- 5 k
- 10 k
- 50 k
- 100 k
• Zero-Scale to Full-Scale Wiper Operation
• Low Wiper Resistance: 75 (typical)
• Low Tempco:
- Absolute (Rheostat): 50 ppm typical
(0°C to 70°C)
- Ratiometric (Potentiometer): 15 ppm typical
• I2C Serial Interface
- 100 kHz, 400 kHz and 3.4 MHz Support
• Serial Protocol Allows:
- High-Speed Read/Write to Wiper
- Increment/Decrement of Wiper
• Resistor Network Terminal Disconnect Feature
via the Terminal Control (TCON) Register
• Brown-Out Reset Protection (1.5V typical)
• Serial Interface Inactive Current (2.5 uA typical)
• High-Voltage Tolerant Digital Inputs: up to 12.5V
• Wide Operating Voltage:
- 2.7V to 5.5V - Device Characteristics Specified
- 1.8V to 5.5V - Device Operation
• Wide Bandwidth (-3dB) Operation:
- 2 MHz (typical) for 5.0 k Device
• Extended Temperature Range (-40°C to +125°C)
The MCP45XX and MCP46XX devices offer a wide
range of product offerings using an I2C interface. This
family of devices support 7-bit and 8-bit resistor
networks, volatile memory configurations, and
Potentiometer and Rheostat pinouts.
Package Types (top view)
MCP45X1
Single Potentiometer
HVC / A0
SCL
SDA
VSS
1
2
3
4
8
7
6
5
VDD
P0B
P0W
P0A
MCP45X2
Single Rheostat
HVC / A0
SCL
SDA
VSS
1
2
3
4
MSOP
HVC / A0 1
SCL 2
SDA 3
VSS 4
VDD
A1
P0B
P0W
MSOP
8 VDD
7 P0B
6 P0W
5 P0A
EP
9
8
7
6
5
HVC / A0 1
SCL 2
SDA 3
VSS 4
8 VDD
EP
9
7 A1
6 P0B
5 P0W
DFN 3x3 (MF) *
DFN 3x3 (MF) *
HVC/A0
VDD
A1
A2
MCP46X1 Dual Potentiometers
1
2
3
4
5
6
7
14
13
12
11
10
9
8
TSSOP
VDD
A1
A2
NC
P0B
P0W
P0A
16 15 14 13
SCL
SDA
VSS
VSS
1
2
3
4
EP
17
12 NC
11 NC
10 P0B
9 P0W
5 6 7 8
P1B
P1W
P1A
P0A
HVC/A0
SCL
SDA
VSS
P1B
P1W
P1A
QFN-16 4x4 (ML) *
MCP46X2 Dual Rheostat
HVC/A0
SCL
SDA
VSS
P1B
1
2
3
4
5
10 VDD HVC / A0 1
9 A1
SCL 2
8 P0B
SDA
3
7 P0W
V
SS 4
6 P1W
P1B 5
MSOP
10 VDD
EP
11
9 A1
8 P0B
7 P0W
6 P1W
DFN 3x3 (MF) *
* Includes Exposed Thermal Pad (EP); see Table 3-1.
2008-2013 Microchip Technology Inc.
DS22096B-page 1
MCP453X/455X/463X/465X
Device Block Diagram
VDD
VSS
A2
A1
HVC/A0
SCL
I2C Interface SDA
Power-Up/
Brown-Out
Control
Resistor
Network 0
(Pot 0)
I2C Serial
Interface
Module &
Control
Logic
(WiperLock™
Technology)
Wiper 0
& TCON
Register
P0A
P0W
P0B
P1A
Resistor
Network 1
(Pot 1)
P1W
Wiper 1
& TCON
Register
Memory (16x9)
Wiper0 (V)
Wiper1 (V)
TCON
Reserved
P1B
For Dual Resistor Network
Devices Only
MCP4531
MCP4532
MCP4541
MCP4542
MCP4551
MCP4552
MCP4561
MCP4562
MCP4631
MCP4632
MCP4641
MCP4642
MCP4651
MCP4652
MCP4661
MCP4662
Note 1:
2:
Resistance (typical)
RAB Options (k)
Wiper RW ()
# of Steps
POR Wiper
Setting
WiperLock
Memory
Type
Wiper
Configuration
Control
Device
# of POTs
Device Features
VDD
Operating
Range (2)
Potentiometer(1)
I2 C
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
129 1.8V to 5.5V
1
Rheostat
I2 C
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
129 1.8V to 5.5V
1
Potentiometer(1)
I2 C
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
129 2.7V to 5.5V
1
Rheostat
I2 C
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
129 2.7V to 5.5V
1
Potentiometer(1)
I2 C
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
257 1.8V to 5.5V
I2
1
1
Rheostat
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
257 1.8V to 5.5V
1
Potentiometer(1)
I2 C
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
257 2.7V to 5.5V
1
Rheostat
I2 C
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
257 2.7V to 5.5V
2
Potentiometer(1)
I2 C
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
129 1.8V to 5.5V
2
Rheostat
2C
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
129 1.8V to 5.5V
2
Potentiometer(1)
I2 C
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
129 2.7V to 5.5V
Rheostat
I2 C
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
129 2.7V to 5.5V
I2 C
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
257 1.8V to 5.5V
I2 C
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
257 1.8V to 5.5V
2
I C
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
257 2.7V to 5.5V
I2 C
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
257 2.7V to 5.5V
2
2
2
2
2
Potentiometer
I
(1)
Rheostat
Potentiometer
Rheostat
(1)
C
Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor).
Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted.
DS22096B-page 2
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Voltage on VDD with respect to VSS .......................................................................................................... -0.6V to +7.0V
Voltage on HVC/A0, A1, A2, SCL, and SDA with respect to VSS ............................................................................. -0.6V to 12.5V
Voltage on all other pins (PxA, PxW, and PxB) with respect to VSS ............................................................. -0.3V to VDD + 0.3V
Input clamp current, IIK (VI < 0, VI > VDD, VI > VPP ON HV pins)........................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ...................................................................................................±20 mA
Maximum output current sunk by any Output pin....................................................................................................25 mA
Maximum output current sourced by any Output pin ..............................................................................................25 mA
Maximum current out of VSS pin ...........................................................................................................................100 mA
Maximum current into VDD pin ..............................................................................................................................100 mA
Maximum current into PXA, PXW & PXB pins ...................................................................................................... ±2.5 mA
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
Package power dissipation (TA = +50°C, TJ = +150°C)
MSSOP-8 .......................................................................................................................................................473 mW
MSSOP-8 .......................................................................................................................................................473 mW
MSSOP-10 .....................................................................................................................................................495 mW
DFN-8 (3x3) ......................................................................................................................................................1.76W
DFN-10 (3x3) ....................................................................................................................................................1.87W
TSSOP-14.........................................................................................................................................................1.00W
QFN-16 (4x4) ....................................................................................................................................................2.18W
Soldering temperature of leads (10 seconds) ....................................................................................................... +300°C
ESD protection on all pins 4 kV (HBM)
300V (MM)
Maximum Junction Temperature (TJ) ................................................................................................................... +150°C
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
2008-2013 Microchip Technology Inc.
DS22096B-page 3
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (extended)
DC Characteristics
Parameters
Supply Voltage
HVC pin Voltage Range
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
Typ
Max
Units
VDD
2.7
—
5.5
V
1.8
—
2.7
V
VSS
—
12.5V
V
VSS
—
VDD +
8.0V
V
1.65
V
VHV
—
Serial Interface only.
VDD The HVC pin will be at one
4.5V of three input levels
V < (VIL, VIH or VIHH). (Note 6)
DD
4.5V
VDD Start Voltage to
ensure Wiper Reset
VBOR
VDD Rise Rate to
ensure Power-on Reset
VDDRR
Delay after device exits
the reset state
(VDD > VBOR)
TBORD
—
10
20
µs
IDD
—
—
600
µA
Serial Interface Active,
HVC/A0 = VIH (or VIL) (Note 11)
Write all 0’s to Volatile Wiper 0
VDD = 5.5V, FSCL = 3.4 MHz
—
—
250
µA
Serial Interface Active,
HVC/A0 = VIH (or VIL) (Note 11)
Write all 0’s to Volatile Wiper 0
VDD = 5.5V, FSCL = 100 kHz
—
2.5
5
µA
Serial Interface Inactive,
(Stop condition, SCL = SDA = VIH),
Wiper = 0
VDD = 5.5V, HVC/A0 = VIH
Supply Current
(Note 10)
—
Conditions
(Note 9)
RAM retention voltage (VRAM) < VBOR
V/ms
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP4XX1 only.
MCP4XX2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
DS22096B-page 4
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (extended)
DC Characteristics
Parameters
Resistance
(± 20%)
Resolution
Step Resistance
Nominal
Resistance Match
Wiper Resistance
(Note 3, Note 4)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
Typ
Max
Units
Conditions
RAB
4.0
5
6.0
k
-502 devices(Note 1)
8.0
10
12.0
k
-103 devices(Note 1)
40.0
50
60.0
k
-503 devices(Note 1)
80.0
100
120.0
k
-104 devices(Note 1)
N
257
Taps 8-bit
No Missing Codes
129
Taps 7-bit
No Missing Codes
—
RAB/
(256)
—
8-bit
Note 6
—
RAB/
(128)
—
7-bit
Note 6
|RAB0-RAB1|
/RAB
—
0.2
1.25
%
MCP46X1 devices only
|RBW0-RBW1
| /RBW
—
0.25
1.5
%
MCP46X2 devices only,
Code = Full-Scale
RW
—
75
160
VDD = 5.5 V, IW = 2.0 mA, code = 00h
—
75
300
VDD = 2.7 V, IW = 2.0 mA, code = 00h
—
50
—
ppm/°C TA = -20°C to +70°C
—
100
—
ppm/°C TA = -40°C to +85°C
—
150
—
ppm/°C TA = -40°C to +125°C
ppm/°C Code = Midscale (80h or 40h)
RS
Nominal
Resistance
Tempco
RAB/T
Ratiometeric
Tempco
VWB/T
—
15
—
Resistor Terminal Input
Voltage Range
(Terminals A, B and W)
VA,VW,VB
Vss
—
VDD
V
Note 5, Note 6
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP4XX1 only.
MCP4XX2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
2008-2013 Microchip Technology Inc.
DS22096B-page 5
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Maximum current
through Terminal (A, W
or B)
Note 6
IT
—
—
2.5
mA
Terminal A
IAW,
W = Full-Scale (FS)
—
—
2.5
mA
Terminal B
IBW,
W = Zero Scale (ZS)
—
—
2.5
mA
Terminal W
IAW or IBW,
W = FS or ZS
—
—
1.38
mA
IAB, VB = 0V,
VA = 5.5V,
RAB(MIN) = 4000
—
—
0.688
mA
IAB, VB = 0V,
VA = 5.5V,
RAB(MIN) = 8000
Leakage current into A,
W or B
IWL
Conditions
Terminal A
and
Terminal B
—
—
0.138
mA
IAB, VB = 0V,
VA = 5.5V,
RAB(MIN) = 40000
—
—
0.069
mA
—
100
—
nA
MCP4XX1 PxA = PxW = PxB = VSS
—
100
—
nA
MCP4XX2 PxB = PxW = VSS
—
100
—
nA
Terminals Disconnected
(R1HW = R0HW = 0)
IAB, VB = 0V,
VA = 5.5V,
RAB(MIN) = 80000
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP4XX1 only.
MCP4XX2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
DS22096B-page 6
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (extended)
DC Characteristics
Parameters
Full-Scale Error
(MCP4XX1 only)
(8-bit code = 100h,
7-bit code = 80h)
Zero-Scale Error
(MCP4XX1 only)
(8-bit code = 00h,
7-bit code = 00h)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
Typ
Max
Units
VWFSE
-6.0
-0.1
—
LSb
-4.0
-0.1
—
LSb
-3.5
-0.1
—
LSb
-2.0
-0.1
—
LSb
-0.8
-0.1
—
LSb
8-bit
3.0V VDD 5.5V
-0.5
-0.1
—
LSb
7-bit
3.0V VDD 5.5V
-0.5
-0.1
—
LSb
100 k 8-bit
3.0V VDD 5.5V
-0.5
-0.1
—
LSb
7-bit
3.0V VDD 5.5V
—
+0.1
+6.0
LSb
8-bit
3.0V VDD 5.5V
7-bit
3.0V VDD 5.5V
8-bit
3.0V VDD 5.5V
7-bit
3.0V VDD 5.5V
8-bit
3.0V VDD 5.5V
VWZSE
Potentiometer Integral
Non-linearity
INL
Potentiometer
Differential Non-linearity
DNL
—
+0.1
+3.0
LSb
—
+0.1
+3.5
LSb
—
+0.1
+2.0
LSb
—
+0.1
+0.8
LSb
Conditions
5 k
10 k
50 k
5 k
10 k
50 k
8-bit
3.0V VDD 5.5V
7-bit
3.0V VDD 5.5V
8-bit
3.0V VDD 5.5V
7-bit
3.0V VDD 5.5V
—
+0.1
+0.5
LSb
7-bit
3.0V VDD 5.5V
—
+0.1
+0.5
LSb
100 k 8-bit
3.0V VDD 5.5V
—
+0.1
+0.5
LSb
7-bit
3.0V VDD 5.5V
-1
±0.5
+1
LSb
8-bit
-0.5
±0.25
+0.5
LSb
7-bit
-0.5
±0.25
+0.5
LSb
8-bit
-0.25
±0.125 +0.25
LSb
7-bit
3.0V VDD 5.5V
MCP4XX1 devices only (Note 2)
3.0V VDD 5.5V
MCP4XX1 devices only (Note 2)
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP4XX1 only.
MCP4XX2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
2008-2013 Microchip Technology Inc.
DS22096B-page 7
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (extended)
DC Characteristics
Parameters
Bandwidth -3 dB
(See Figure 2-65,
load = 30 pF)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
BW
Min
Typ
Max
Units
Conditions
—
2
—
MHz
—
2
—
MHz
5 k
—
1
—
MHz
—
1
—
MHz
—
200
—
kHz
8-bit
Code = 80h
—
200
—
kHz
7-bit
Code = 40h
—
100
—
kHz
100 k 8-bit
Code = 80h
—
100
—
kHz
7-bit
Code = 40h
10 k
50 k
8-bit
Code = 80h
7-bit
Code = 40h
8-bit
Code = 80h
7-bit
Code = 40h
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP4XX1 only.
MCP4XX2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
DS22096B-page 8
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Rheostat Integral
Non-linearity
MCP45X1
(Note 4, Note 8)
MCP4XX2 devices only
(Note 4)
R-INL
Min
Typ
Max
Units
-1.5
±0.5
+1.5
LSb
-8.25
+4.5
+8.25
LSb
-1.125
±0.5
+1.125
LSb
-6.0
+4.5
+6.0
LSb
-1.5
±0.5
+1.5
LSb
-5.5
+2.5
+5.5
LSb
-1.125
±0.5
+1.125
LSb
-4.0
+2.5
+4.0
LSb
-1.5
±0.5
+1.5
LSb
-2.0
+1
+2.0
LSb
-1.125
±0.5
+1.125
LSb
-1.5
+1
+1.5
LSb
-1.0
±0.5
+1.0
LSb
-1.5
+0.25
+1.5
LSb
±0.5
+0.8
-0.8
-1.125
+0.25 +1.125
LSb
LSb
Conditions
5 k
8-bit
5.5V, IW = 900 µA
3.0V, IW = 480 µA
(Note 7)
7-bit
5.5V, IW = 900 µA
3.0V, IW = 480 µA
(Note 7)
10 k
8-bit
5.5V, IW = 450 µA
3.0V, IW = 240 µA
(Note 7)
7-bit
5.5V, IW = 450 µA
3.0V, IW = 240 µA
(Note 7)
50 k
8-bit
5.5V, IW = 90 µA
3.0V, IW = 48 µA
(Note 7)
7-bit
5.5V, IW = 90 µA
3.0V, IW = 48 µA
(Note 7)
100 k 8-bit
5.5V, IW = 45 µA
3.0V, IW = 24 µA
(Note 7)
7-bit
5.5V, IW = 45 µA
3.0V, IW = 24 µA
(Note 7)
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP4XX1 only.
MCP4XX2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
2008-2013 Microchip Technology Inc.
DS22096B-page 9
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Rheostat
Differential Non-linearity
MCP45X1
(Note 4, Note 8)
MCP4XX2 devices only
(Note 4)
R-DNL
Min
Typ
Max
Units
-0.5
-1.0
±0.25
+0.5
LSb
+0.5
+1.0
LSb
-0.375
±0.25 +0.375
LSb
-0.75
+0.5
+0.75
LSb
-0.5
±0.25
+0.5
LSb
-1.0
+0.25
+1.0
LSb
-0.375
±0.25 +0.375
LSb
-0.75
+0.5
+0.75
LSb
-0.5
±0.25
+0.5
LSb
-0.5
±0.25
+0.5
LSb
-0.375
±0.25 +0.375
LSb
-0.375
±0.25 +0.375
LSb
-0.5
±0.25
+0.5
LSb
-0.5
±0.25
+0.5
LSb
-0.375
±0.25 +0.375
LSb
-0.375
±0.25 +0.375
LSb
Conditions
5 k
8-bit
5.5V, IW = 900 µA
3.0V, IW = 480 µA
(Note 7)
7-bit
5.5V, IW = 900 µA
3.0V, IW = 480 µA
(Note 7)
10 k
8-bit
5.5V, IW = 450 µA
3.0V, IW = 240 µA
(Note 7)
7-bit
5.5V, IW = 450 µA
3.0V, IW = 240 µA
(Note 7)
50 k
8-bit
5.5V, IW = 90 µA
3.0V, IW = 48 µA
(Note 7)
7-bit
5.5V, IW = 90 µA
3.0V, IW = 48 µA
(Note 7)
100 k 8-bit
5.5V, IW = 45 µA
3.0V, IW = 24 µA
(Note 7)
7-bit
5.5V, IW = 45 µA
3.0V, IW = 24 µA
(Note 7)
Capacitance (PA)
CAW
—
75
—
pF
f =1 MHz, Code = Full-Scale
Capacitance (Pw)
CW
—
120
—
pF
f =1 MHz, Code = Full-Scale
Capacitance (PB)
CBW
—
75
—
pF
f =1 MHz, Code = Full-Scale
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP4XX1 only.
MCP4XX2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
DS22096B-page 10
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (extended)
DC Characteristics
Parameters
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
Typ
Max
Units
Conditions
Digital Inputs/Outputs (SDA, SCK, HVC/A0, A1, A2, WP)
Schmitt Trigger High
Input Threshold
Schmitt Trigger Low
Input Threshold
Hysteresis of Schmitt
Trigger Inputs (Note 6)
High Voltage Limit
VIH
VIL
VHYS
0.45 VDD
—
—
V
0.5 VDD
—
—
V
0.7 VDD
—
VMAX
V
0.7 VDD
—
VMAX
V
0.7 VDD
—
VMAX
V
0.7 VDD
—
VMAX
V
—
—
0.2VDD
V
-0.5
—
0.3VDD
V
-0.5
—
0.3VDD
V
-0.5
—
0.3VDD
V
-0.5
—
0.3VDD
V
—
0.1VD
—
V
All
Inputs
except
SDA
and
SCL
2.7V VDD 5.5V
(Allows 2.7V Digital VDD with
5V Analog VDD)
1.8V VDD 2.7V
100 kHz
SDA
and
SCL
400 kHz
1.7 MHz
3.4 Mhz
All inputs except SDA and SCL
100 kHz
SDA
and
SCL
400 kHz
1.7 MHz
3.4 Mhz
All inputs except SDA and SCL
D
VMAX
N.A.
—
—
V
N.A.
—
—
V
0.1 VDD
—
—
V
0.05 VDD
—
—
V
0.1 VDD
—
—
V
0.1 VDD
—
—
V
—
—
12.5 (6)
V
100 kHz
SDA
and
SCL
400 kHz
VDD < 2.0V
VDD 2.0V
VDD < 2.0V
VDD 2.0V
1.7 MHz
3.4 Mhz
Pin can tolerate VMAX or less.
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP4XX1 only.
MCP4XX2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
2008-2013 Microchip Technology Inc.
DS22096B-page 11
MCP453X/455X/463X/465X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Output Low
Voltage (SDA)
VOL
Weak Pull-up /
Pull-down Current
IPU
HVC Pull-up /
Pull-down
Resistance
RHVC
Typ
Max
Units
Conditions
VSS
—
0.2VDD
V
VDD < 2.0V, IOL = 1 mA
VSS
—
0.4
V
VDD 2.0V, IOL = 3 mA
—
—
1.75
mA
Internal VDD pull-up, VIHH pull-down
VDD = 5.5V, VIHH = 12.5V
—
170
—
µA
HVC pin, VDD = 5.5V, VHVC = 3V
—
16
—
k
VDD = 5.5V, VHVC = 3V
IIL
-1
—
1
µA
VIN = VDD and VIN = VSS
CIN, COUT
—
10
—
pF
fC = 3.4 MHz
N
0h
—
1FFh
hex
8-bit device
—
1FFh
Input Leakage Current
Pin Capacitance
Min
RAM (Wiper) Value
Value Range
0h
TCON POR/BOR Value
hex
7-bit device
1FFh
hex
All Terminals connected
—
0.0015 0.0035
%/%
8-bit
VDD = 2.7V to 5.5V,
VA = 2.7V, Code = 80h
—
0.0015 0.0035
%/%
7-bit
VDD = 2.7V to 5.5V,
VA = 2.7V, Code = 40h
NTCON
Power Requirements
Power Supply
Sensitivity
(MCP45X2 and
MCP46X2 only)
PSS
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP4XX1 only.
MCP4XX2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly overvoltage and
temperature.
8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and
then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
SCL
93
91
90
92
SDA
START
Condition
FIGURE 1-1:
DS22096B-page 12
STOP
Condition
I2C Bus Start/Stop Bits Timing Waveforms.
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
I2C BUS START/STOP BITS REQUIREMENTS
TABLE 1-1:
I2C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40C TA +125C (Extended)
Operating Voltage VDD range is described in AC/DC Characteristics
Param.
Symbol
No.
Characteristic
FSCL
D102
Cb
Bus capacitive
loading
90
TSU:STA START condition
Setup time
91
THD:STA START condition
Hold time
92
TSU:STO STOP condition
Setup time
93
THD:STO STOP condition
Hold time
Standard Mode
Fast Mode
High-Speed 1.7
High-Speed 3.4
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
103
Min
Max
Units
0
0
0
0
—
—
—
—
4700
600
160
160
4000
600
160
160
4000
600
160
160
4000
600
160
160
100
400
1.7
3.4
400
400
400
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
kHz
kHz
MHz
MHz
pF
pF
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
Cb = 400 pF, 1.8V - 5.5V
Cb = 400 pF, 2.7V - 5.5V
Cb = 400 pF, 4.5V - 5.5V
Cb = 100 pF, 4.5V - 5.5V
Only relevant for repeated
START condition
After this period the first
clock pulse is generated
102
100
101
SCL
90
106
91
107
92
SDA
In
109
109
110
SDA
Out
FIGURE 1-2:
I2C Bus Data Timing.
2008-2013 Microchip Technology Inc.
DS22096B-page 13
MCP453X/455X/463X/465X
I2C BUS DATA REQUIREMENTS (SLAVE MODE)
TABLE 1-2:
I2C AC Characteristics
Param.
No.
100
101
102A
(Note 5)
102B
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40C TA +125C (Extended)
Operating Voltage VDD range is described in AC/DC Characteristics
Symbol Characteristic
THIGH
TLOW
TRSCL
TRSDA
Min
Max
Units
Clock high time 100 kHz mode
4000
—
ns
1.8V-5.5V
400 kHz mode
600
—
ns
2.7V-5.5V
1.7 MHz mode
120
ns
4.5V-5.5V
3.4 MHz mode
60
—
ns
4.5V-5.5V
100 kHz mode
4700
—
ns
1.8V-5.5V
400 kHz mode
1300
—
ns
2.7V-5.5V
1.7 MHz mode
320
ns
4.5V-5.5V
3.4 MHz mode
Clock low time
SCL rise time
SDA rise time
(Note 5)
103A
(Note 5)
Note 1:
2:
3:
4:
5:
6:
TFSCL
SCL fall time
Conditions
160
—
ns
4.5V-5.5V
100 kHz mode
—
1000
ns
Cb is specified to be from
10 to 400 pF (100 pF
maximum for 3.4 MHz
mode)
400 kHz mode
20 + 0.1Cb
300
ns
1.7 MHz mode
20
80
ns
1.7 MHz mode
20
160
ns
3.4 MHz mode
10
40
ns
3.4 MHz mode
10
80
ns
After a Repeated Start
condition or an
Acknowledge bit
Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1Cb
300
ns
1.7 MHz mode
20
160
ns
3.4 MHz mode
10
80
ns
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1Cb
300
ns
1.7 MHz mode
20
80
ns
3.4 MHz mode
10
40
ns
After a Repeated Start
condition or an
Acknowledge bit
Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line.
TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
Use Cb in pF for the calculations.
Not tested.
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
Ensured by the TAA 3.4 MHz specification test.
DS22096B-page 14
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
TABLE 1-2:
I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
I2C AC Characteristics
Param.
No.
103B
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40C TA +125C (Extended)
Operating Voltage VDD range is described in AC/DC Characteristics
Symbol Characteristic
TFSDA
SDA fall time
(Note 5)
106
107
109
110
THD:DAT
TSU:DAT Data input setup
time
TAA
TBUF
TSP
Note 1:
2:
3:
4:
5:
6:
Data input hold
time
Output valid
from clock
Bus free time
Input filter spike
suppression
(SDA and SCL)
Min
Max
Units
Conditions
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1Cb
(
Note 3)
300
ns
1.7 MHz mode
20
160
ns
3.4 MHz mode
10
80
ns
100 kHz mode
0
—
ns
1.8V-5.5V, Note 5
400 kHz mode
0
—
ns
2.7V-5.5V, Note 5
1.7 MHz mode
0
—
ns
4.5V-5.5V, Note 5
3.4 MHz mode
0
—
ns
4.5V-5.5V, Note 5
100 kHz mode
250
—
ns
Note 2
400 kHz mode
100
—
ns
1.7 MHz mode
10
—
ns
3.4 MHz mode
10
—
ns
100 kHz mode
—
3450
ns
400 kHz mode
—
900
ns
1.7 MHz mode
—
150
ns
Cb = 100 pF,
Note 1, Note 6
—
310
ns
Cb = 400 pF,
Note 1, Note 4
3.4 MHz mode
—
150
ns
Cb = 100 pF, Note 1
100 kHz mode
4700
—
ns
Time the bus must be free
before a new transmission
can start
400 kHz mode
1300
—
ns
1.7 MHz mode
N.A.
—
ns
3.4 MHz mode
N.A.
—
ns
100 kHz mode
—
50
ns
Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
Note 1
Philips Spec states N.A.
400 kHz mode
—
50
ns
1.7 MHz mode
—
10
ns
Spike suppression
3.4 MHz mode
—
10
ns
Spike suppression
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line.
TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
Use Cb in pF for the calculations.
Not tested.
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
Ensured by the TAA 3.4 MHz specification test.
2008-2013 Microchip Technology Inc.
DS22096B-page 15
MCP453X/455X/463X/465X
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 8L-DFN (3x3)
JA
—
56.7
—
°C/W
Thermal Resistance, 8L-MSOP
JA
—
211
—
°C/W
Thermal Resistance, 8L-SOIC
JA
—
149.5
—
°C/W
Thermal Resistance, 10L-DFN (3x3)
JA
—
57
—
°C/W
Thermal Resistance, 10L-MSOP
JA
—
202
—
°C/W
Thermal Resistance, 14L-MSOP
JA
—
N/A
—
°C/W
Thermal Resistance, 14L-SOIC
JA
—
95.3
—
°C/W
Thermal Resistance, 16L-QFN
JA
—
45.7
—
°C/W
Conditions
Temperature Ranges
Thermal Package Resistances
DS22096B-page 16
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
3.4 MHz, 5.5V
500
400
400 kHz, 5.5V
100 kHz, 5.5V
300
3.4 MHz, 4.5V
1.7 MHz, 4.5V
200
200
RHVC (kOhms)
IDD (µA)
600
150
200
0
-200
-400
IHVC
100
50
100
100 kHz, 2.7V
-600
-800
-1000
RHVC
400 kHz, 2.7V
0
0
-40
0
40
80
Temperature (°C)
120
FIGURE 2-1:
Device Current (IDD) vs. I2C
Frequency (fSCL) and Ambient Temperature
(VDD = 2.7V and 5.5V).
2
3
4
5
6
7
VHVC (V)
IHVC (µA)
1.7 MHz, 5.5V
700
8
9
10
FIGURE 2-4:
HVC Pull-up/Pull-down
Resistance (RHVC) and Current (IHVC) vs. HVC
Input Voltage (VHVC) (VDD = 5.5V).
12
HVC VPP Threshold (V)
3
2.5
Istandby (µA)
1000
800
600
400
250
800
5.5V
2
1.5
1
2.7V
10
5.5V Entry
8
2.7V Entry
5.5V Exit
6
4
2.7V Exit
2
0
0.5
-40
0
40
80
120
Temperature (°C)
FIGURE 2-2:
Device Current (ISHDN) and
VDD (HVC = VDD) vs. Ambient Temperature.
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
100
120
FIGURE 2-5:
HVC High Input Entry/Exit
Threshold vs. Ambient Temperature and VDD.
420
IWRITE (µA)
400
380
360
5.5V
340
320
300
-40
0
40
80
120
Temperature (°C)
FIGURE 2-3:
Write Current (IWRITE) vs.
Ambient Temperature.
2008-2013 Microchip Technology Inc.
DS22096B-page 17
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
0.1
80
0
60
-0.1
40
20
0
100
-0.2
RW
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
32
-40C Rw
-40C INL
-40C DNL
260
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
INL
220
0.1
180
0
140
-0.1
RW
100
125°C
60
-40°C
20
0
32
25°C
-0.2
85°C
2000
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
0.5
0.2
1500
0.1
0
1000
-0.1
DNL
-0.2
RW
0
Note:
64
128
192
Wiper Setting (decimal)
FIGURE 2-8:
5 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
-0.75
RW
-1.25
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
6
INL
4
2
140
RW
100
0
-40°C
60
125°C
20
0
32
85°C
25°C
DNL
-2
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-10:
5 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
118
98
INL
78
1500
58
1000
38
500
RW
DNL
0
256
Refer to Appendix B: “Characterization Data Analysis” for additional information on the characteristics of the
wiper resistance (RW) with respect to
device voltage and wiper setting value.
DS22096B-page 18
32
DNL
-40°C
180
-0.3
0
85°C 25°C
2000
0.3
INL
500
125°C
2500
0.4
Error (LSb)
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
2500
40
FIGURE 2-9:
5 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-7:
5 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
0.75
-0.25
220
DNL
1.25
60
260
0.2
125C Rw
125C INL
125C DNL
0.25
300
0.3
125C Rw
125C INL
125C DNL
Error (LSb)
Wiper Resistance (R W)
(ohms)
300
85C Rw
85C INL
85C DNL
80
0
FIGURE 2-6:
5 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
25C Rw
25C INL
25C DNL
INL
20
Wiper Resistance (R W )
(ohms)
125°C
-40°C 25°C
85°C
-40C Rw
-40C INL
-40C DNL
Error (LSb)
0.2
INL
DNL
120
Error (LSb)
0.3
125C Rw
125C INL
125C DNL
0
Note:
64
128
192
Wiper Setting (decimal)
Error (LSb)
85C Rw
85C INL
85C DNL
Wiper Resistance (RW)
(ohms)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (R W )
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (R W )
(ohms)
120
18
-2
256
Refer to Appendix B: “Characterization Data Analysis” for additional information on the characteristics of the
wiper resistance (RW) with respect to
device voltage and wiper setting value.
FIGURE 2-11:
5 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
5300
6000
5250
5000
RWB (Ohms)
Nominal Resistance (RAB)
(Ohms)
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
2.7V
5200
5150
5.5V
1.8V
5100
4000
3000
2000
-40°C
25°C
85°C
125°C
1000
0
5050
-40
0
40
80
Ambient Temperature (°C)
120
FIGURE 2-12:
5 k – Nominal Resistance
() vs. Ambient Temperature and VDD.
2008-2013 Microchip Technology Inc.
0
32
64
96
128 160 192
Wiper Setting (decimal)
224
256
FIGURE 2-13:
5 k – RWB () vs. Wiper
Setting and Ambient Temperature.
DS22096B-page 19
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-14:
5 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-17:
5 k – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-15:
5 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-18:
5 k – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-16:
5 k – Power-Up Wiper
Response Time (20 ms/Div).
DS22096B-page 20
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
0.2
INL
DNL
0.1
80
0
60
-0.1
25°C -40°C
125°C 85°C
-0.2
RW
20
-0.3
-40C Rw
-40C INL
-40C DNL
260
220
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
INL
DNL
0.1
180
0
140
100
-0.1
RW
60
25°C
125°C 85°C
20
0
32
-0.2
-40°C
125°C
3500
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
3000
125C Rw
125C INL
125C DNL
0.5
INL
0.3
2500
0.4
0.2
2000
DNL
0.1
1500
0
1000
-0.1
500
-0.2
RW
0
64
128
192
Wiper Setting (decimal)
FIGURE 2-21:
10 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
2008-2013 Microchip Technology Inc.
DNL
-0.5
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
4
3
INL
2
180
1
140
0
100
-40°C
60
DNL
RW
-1
-2
0
25 50 75 100 125 150 175 200 225 250
Wiper Setting (decimal)
FIGURE 2-23:
10 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
-40C Rw
-40C INL
-40C DNL
3500
3000
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
INL
2000
1500
1000
500
RW
DNL
0
0
Note:
98
88
78
68
58
48
38
28
18
8
-2
256
125C Rw
125C INL
125C DNL
2500
256
Refer to Appendix B: “Characterization Data Analysis” for additional information on the characteristics of the
wiper resistance (RW) with respect to
device voltage and wiper setting value.
25C Rw
25C INL
25C DNL
220
-0.3
0
RW
-40°C
-1
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
260
4000
Error (LSb)
-40C Rw
-40C INL
-40C DNL
32
85°C 25°C
20
0.6
4000
Wiper Resistance
(RW)(ohms)
40
125°C 85°C 25°C
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-20:
10 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
Note:
0
60
300
0.2
1
FIGURE 2-22:
10 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
0.3
125C Rw
125C INL
125C DNL
125C Rw
125C INL
125C DNL
80
0
Error (LSb)
Wiper Resistance (R W)
(ohms)
300
85C Rw
85C INL
85C DNL
0.5
20
FIGURE 2-19:
10 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
25C Rw
25C INL
25C DNL
INL
25 50 75 100 125 150 175 200 225 250
Wiper Setting (decimal)
Wiper Resistance (R W )
(ohms)
0
-40C Rw
-40C INL
-40C DNL
100
Wiper Resistance (RW)
(ohms)
40
120
Error (LSb)
0.3
125C Rw
125C INL
125C DNL
Error (LSb)
85C Rw
85C INL
85C DNL
64
128
192
Wiper Setting (decimal)
Error (LSb)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (R W )
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (R W )
(ohms)
120
Refer to Appendix B: “Characterization Data Analysis” for additional information on the characteristics of the
wiper resistance (RW) with respect to
device voltage and wiper setting value.
FIGURE 2-24:
10 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
DS22096B-page 21
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
12000
10250
10000
10200
10150
10100
RWB (Ohms)
Nominal Resistance (R AB)
(Ohms)
10300
2.7V
10050
10000
5.5V
9950
1.8V
8000
6000
4000
-40°C
25°C
85°C
125°C
2000
9900
9850
0
-40
0
40
80
Ambient Temperature (°C)
120
FIGURE 2-25:
10 k – Nominal Resistance
() vs. Ambient Temperature and VDD.
DS22096B-page 22
0
32
64
96 128 160 192
Wiper Setting (decimal)
224
256
FIGURE 2-26:
10 k – RWB () vs. Wiper
Setting and Ambient Temperature.
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-27:
10 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-30:
10 k – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-28:
10 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-31:
10 k – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-29:
10 k – Power-Up Wiper
Response Time (1 µs/Div).
2008-2013 Microchip Technology Inc.
DS22096B-page 23
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
0.1
80
0
60
-0.1
40
25°C
85°C
125°C
20
0
-40°C
100
-0.2
RW
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
32
260
220
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
0.1
180
0
140
-0.2
-40°C
60
32
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
Error (LSb)
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
INL
RW
64
128
192
Wiper Setting (decimal)
FIGURE 2-34:
50 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
DS22096B-page 24
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
INL
1
0.75
0.5
DNL
0.25
0
-0.25
RW
100
-0.5
-40°C
60
0
32
-0.75
85°C 25°C
20
64
-1
96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-36:
50 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
15000
14000
13000
12000
11000
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
256
Refer to Appendix B: “Characterization Data Analysis” for additional information on the characteristics of the
wiper resistance (RW) with respect to
device voltage and wiper setting value.
-0.2
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
125°C
DNL
0
32
RW
140
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-33:
50 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
15000
14000
13000
12000
11000
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
85°C 25°C
125°C
-40°C
180
Wiper Resistance (Rw)
(ohms)
0
Wiper Resistance (RW)
(ohms)
-0.1
40
125°C 85°C 25°C
20
Note:
0
260
-0.1
RW
100
0.1
60
220
INL
DNL
0.2
DNL
300
0.2
0.3
125C Rw
125C INL
125C DNL
FIGURE 2-35:
50 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
0.3
125C Rw
125C INL
125C DNL
85C Rw
85C INL
85C DNL
80
0
Error (LSb)
Wiper Resistance (R W)
(ohms)
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
INL
20
FIGURE 2-32:
50 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
300
-40C Rw
-40C INL
-40C DNL
Error (LSb)
0.2
INL
DNL
120
Error (LSb)
0.3
125C Rw
125C INL
125C DNL
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
RW
INL
DNL
78.5
73.5
68.5
63.5
58.5
53.5
48.5
43.5
38.5
33.5
28.5
23.5
18.5
13.5
8.5
3.5
-1.5
Error (LSb)
85C Rw
85C INL
85C DNL
Wiper Resistance (R W)
(ohms)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (R W )
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (R W )
(ohms)
120
0 25 50 75 100 125 150 175 200 225 250
Wiper Setting (decimal)
Note:
Refer to Appendix B: “Characterization Data Analysis” for additional information on the characteristics of the
wiper resistance (RW) with respect to
device voltage and wiper setting value.
FIGURE 2-37:
50 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
60000
52000
50000
51500
1.8V
RWB (Ohms)
Nominal Resistance (R
(Ohms)
AB)
52500
51000
50500
50000
2.7V
40000
30000
20000
-40°C
25°C
85°C
125°C
10000
49500
5.5V
49000
0
-40
0
40
80
Ambient Temperature (°C)
120
FIGURE 2-38:
50 k – Nominal Resistance
() vs. Ambient Temperature and VDD.
2008-2013 Microchip Technology Inc.
0
32
64
96 128 160 192
Wiper Setting (decimal)
224
256
FIGURE 2-39:
50 k – RWB () vs. Wiper
Setting and Ambient Temperature.
DS22096B-page 25
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-40:
50 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-43:
50 k – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-41:
50 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-44:
50 k – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-42:
50 k – Power-Up Wiper
Response Time (1 µs/Div).
DS22096B-page 26
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
DNL
0
60
-0.1
40
25°C -40°C
-40C Rw
-40C INL
-40C DNL
100
0.1
INL
80
120
RW
-0.2
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
260
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
-0.1
40
-40°C
DNL
0.15
0
140
-0.05
100
RW
60
-0.1
-40°C
-0.15
125°C 85°C 25°C
20
0
32
25000
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
0.05
15000
-0.05
10000
-0.15
5000
RW
INL
0
64
128
192
Wiper Setting (decimal)
0.2
0
-0.2
RW
100
60
-0.4
-40°C
125°C 85°C 25°C
32
-0.6
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-49:
100 k Rheo Mode – RW
(), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
-40C Rw
-40C INL
-40C DNL
25000
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
RW
20000
INL
15000
10000
5000
DNL
0
256
Refer to Appendix B: “Characterization Data Analysis” for additional information on the characteristics of the
wiper resistance (RW) with respect to
device voltage and wiper setting value.
FIGURE 2-47:
100 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
2008-2013 Microchip Technology Inc.
0.4
140
-0.35
0
Note:
-0.25
0.6
125C Rw
125C INL
125C DNL
DNL
0
0.25
85C Rw
85C INL
85C DNL
180
0.35
0.15
DNL
20000
125C Rw
125C INL
125C DNL
25C Rw
25C INL
25C DNL
INL
20
Error (LSb)
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
220
-0.2
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-46:
100 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
32
-0.2
FIGURE 2-48:
100 k Rheo Mode – RW
(), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
260
0.05
180
RW
125°C 85°C 25°C
300
0.1
INL
220
0.1
0
0.2
Error (LSb)
Wiper Resistance (R W)
(ohms)
300
0.2
60
0
FIGURE 2-45:
100 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
0.3
125C Rw
125C INL
125C DNL
DNL
80
20
Wiper Resistance (Rw)
(ohms)
32
Wiper Resistance (RW)
(ohms)
0
85C Rw
85C INL
85C DNL
INL
125°C 85°C
20
25C Rw
25C INL
25C DNL
Error (LSb)
0.2
125C Rw
125C INL
125C DNL
Error (LSb)
85C Rw
85C INL
85C DNL
0
Note:
64
128
192
Wiper Setting (decimal)
59
54
49
44
39
34
29
24
19
14
9
4
-1
Error (LSb)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (R W )
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (R W )
(ohms)
120
256
Refer to Appendix B: “Characterization Data Analysis” for additional information on the characteristics of the
wiper resistance (RW) with respect to
device voltage and wiper setting value.
FIGURE 2-50:
100 k Rheo Mode – RW
(), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
DS22096B-page 27
MCP453X/455X/463X/465X
120000
103500
103000
102500
102000
101500
101000
100500
100000
99500
99000
98500
100000
Rwb (Ohms)
Nominal Resistance (R
(Ohms)
AB)
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
1.8V
2.7V
80000
60000
40000
-40°C
25°C
85°C
125°C
20000
5.5V
0
-40
0
40
80
Ambient Temperature (°C)
120
FIGURE 2-51:
100 k – Nominal
Resistance () vs. Ambient Temperature and
VDD .
DS22096B-page 28
0
32
64
96 128 160 192
Wiper Setting (decimal)
224
256
FIGURE 2-52:
100 k – RWB () vs. Wiper
Setting and Ambient Temperature.
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-53:
100 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-56:
100 k – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-54:
100 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-55:
100 k – Low-Voltage
Increment Wiper Settling Time (VDD =5.5V)
(1 µs/Div).
2008-2013 Microchip Technology Inc.
DS22096B-page 29
MCP453X/455X/463X/465X
0.12
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0.1
0.08
5.5V
%
%
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
0.06
0.04
3.0V
0.02
3.0V
0
-40
0
40
80
Temperature (°C)
120
FIGURE 2-57:
Resistor Network 0 to
Resistor Network 1 RAB (5 k) Mismatch vs. VDD
and Temperature.
-40
0.04
0.05
0.03
0.04
40
80
Temperature (°C)
0.03
5.5V
0.01
0
120
FIGURE 2-59:
Resistor Network 0 to
Resistor Network 1 RAB (50 k) Mismatch vs.
VDD and Temperature.
0.02
5.5V
0.02
0
%
%
5.5V
-0.01
3.0V
0
3.0V
-0.02
0.01
-0.01
-0.03
-0.02
-0.04
-0.03
-40
0
40
80
Temperature (°C)
120
FIGURE 2-58:
Resistor Network 0 to
Resistor Network 1 RAB (10 k) Mismatch vs.
VDD and Temperature.
DS22096B-page 30
-40
10
60
Temperature (°C)
110
FIGURE 2-60:
Resistor Network 0 to
Resistor Network 1 RAB (100 k) Mismatch vs.
VDD and Temperature.
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
4
3.5
5.5V
VOL (mV)
VIH (V)
3
2.5
2
2.7V
1.5
230
210
2.7V
190
170
150
130
5.5V
110
90
70
50
1
-40
0
40
80
120
Temperature (°C)
FIGURE 2-61:
Temperature.
-40
0
40
80
120
Temperature (°C)
VIH (SDA, SCL) vs. VDD and
FIGURE 2-63:
VOL (SDA) vs. VDD and
Temperature (IOL = 3 mA).
2
VIL (V)
5.5V
1.5
2.7V
1
-40
0
40
80
120
Temperature (°C)
FIGURE 2-62:
Temperature.
VIL (SDA, SCL) vs. VDD and
2008-2013 Microchip Technology Inc.
DS22096B-page 31
MCP453X/455X/463X/465X
2.1
Note: Unless otherwise indicated, TA = +25°C,
VDD = 5V, VSS = 0V.
Test Circuits
1.2
+5V
1
5.5V
VDD (V)
0.6
A
VIN
0.8
W
2.7V
B
Offset
GND
0.4
+
VOUT
-
0.2
2.5V DC
0
-40
0
40
80
120
Temperature (°C)
FIGURE 2-64:
and Temperature.
POR/BOR Trip point vs. VDD
FIGURE 2-65:
Test.
floating
VA
A
-3 db Gain vs. Frequency
VW
W
IW
B
VB
FIGURE 2-66:
DS22096B-page 32
RBW = VW/IW
RW = (VW-VA)/IW
RBW and RW Measurement.
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Additional descriptions of the device pins follows.
TABLE 3-1:
PINOUT DESCRIPTION FOR THE MCP453X/455X/463X/465X
Pin
Single
Dual
Rheo Pot(1) Rheo
Pot
Symbol
I/O
Buffer
Type
Weak
Pull-up/
down (1)
Standard Function
8L
8L
10L
14L
16L
1
1
1
1
16
HVC/A0
I
HV w/ST
“smart”
2
2
2
2
1
SCL
I
HV w/ST
No
I2C clock input
3
3
3
3
2
SDA
I/O
HV w/ST
No
I2C serial data I/O. Open Drain
output
4
4
4
4
3, 4
VSS
—
P
—
Ground
—
—
5
5
5
P1B
A
Analog
No
Potentiometer 1 Terminal B
—
—
6
6
6
P1W
A
Analog
No
Potentiometer 1 Wiper Terminal
—
—
—
7
7
P1A
A
Analog
No
Potentiometer 1 Terminal A
—
5
—
8
8
P0A
A
Analog
No
Potentiometer 0 Terminal A
5
6
7
9
9
P0W
A
Analog
No
Potentiometer 0 Wiper Terminal
6
7
8
10
10
P0B
A
Analog
No
Potentiometer 0 Terminal B
—
—
—
11
11, 12
NC
—
—
—
No Connection
—
—
—
12
13
A2
I
HV w/ST
“smart”
7
—
9
13
14
A1
I
HV w/ST
“smart”
8
8
10
14
15
VDD
—
P
—
Positive Power Supply Input
9
9
11
—
17
EP
—
—
—
Exposed Pad (Note 2)
High Voltage Command /
Address 0
Address 2
Address 1
Legend: HV w/ST = High Voltage tolerant input (with Schmidtt trigger input)
A = Analog pins (Potentiometer terminals) I = digital input (high Z)
O = digital output
I/O = Input / Output
P = Power
Note 1:
2:
The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and shutdown current.
The DFN and QFN packages have a contact on the bottom of the package. This contact is conductively
connected to the die substrate, and therefore should be unconnected or connected to the same ground as
the device’s VSS pin.
2008-2013 Microchip Technology Inc.
DS22096B-page 33
MCP453X/455X/463X/465X
3.1
High Voltage Command / Address 0
(HVC/A0)
The HVC/A0 pin is the Address 0 input for the I2C
interface as well as the High Voltage command pin. At
the device’s POR/BOR the value of the A0 address bit
is latched. This input, along with the A2 and A1 pins,
completes the device address. This allows up to eight
MCP45XX/46XX devices on a single I2C bus.
During normal operation the voltage on this pin determines if the I2C command is a normal command or a
High Voltage command (when HVC/A0 = VIHH).
3.2
Serial Clock (SCL)
The SCL pin is the serial interfaces Serial Clock pin.
This pin is connected to the Host Controllers SCL pin.
The MCP45XX/46XX is a slave device, so its SCL pin
accepts only external clock signals.
3.3
Serial Data (SDA)
The SDA pin is the serial interfaces Serial Data pin.
This pin is connected to the Host Controllers SDA pin.
The SDA pin is an open-drain N-channel driver.
3.4
Ground (VSS)
The VSS pin is the device ground reference.
3.5
Potentiometer Terminal B
The terminal B pin is connected to the internal
potentiometer’s terminal B.
The potentiometer’s terminal B is the fixed connection
to the Zero Scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x00 for both
7-bit and 8-bit devices.
3.7
The terminal A pin is available on the MCP4XX1
devices, and is connected to the internal potentiometer’s terminal A.
The potentiometer’s terminal A is the fixed connection
to the Full-Scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x100 for 8-bit
devices or 0x80 for 7-bit devices.
The terminal A pin does not have a polarity relative to
the terminal W or B pins. The terminal A pin can
support both positive and negative current. The voltage
on terminal A must be between VSS and VDD.
The terminal A pin is not available on the MCP4XX2
devices, and the internally terminal A signal is floating.
MCP46X1 devices have two terminal A pins, one for
each resistor network.
3.8
3.9
3.10
Positive Power Supply Input (VDD)
The VDD pin is the device’s positive power supply input.
The input power supply is relative to VSS.
While the device VDD < Vmin (2.7V), the electrical
performance of the device may not meet the data sheet
specifications.
MCP46XX devices have two terminal B pins, one for
each resistor network.
3.12
The terminal W pin is connected to the internal potentiometer’s terminal W (the wiper). The wiper terminal is
the adjustable terminal of the digital potentiometer. The
terminal W pin does not have a polarity relative to
terminals A or B pins. The terminal W pin can support
both positive and negative current. The voltage on
terminal W must be between VSS and VDD.
Address 1 (A1)
The A2 pin is the I2C interface’s Address 1 pin. Along
with the A2 and A0 pins, up to eight MCP45XX/46XX
devices can be used on a single I2C bus.
3.11
Potentiometer Wiper (W) Terminal
Address 2 (A2)
The A2 pin is the I2C interface’s Address 2 pin. Along
with the A1 and A0 pins, up to eight MCP45XX/46XX
devices can be used on a single I2C bus.
The terminal B pin does not have a polarity relative to
the terminal W or A pins. The terminal B pin can
support both positive and negative current. The voltage
on terminal B must be between VSS and VDD.
3.6
Potentiometer Terminal A
No Connect (NC)
These pins should be either connected to VDD or VSS.
Exposed Pad (EP)
This pad is conductively connected to the device’s
substrate. This pad should be tied to the same potential
as the VSS pin (or left unconnected). This pad could be
used to assist as a heat sink for the device when
connected to a PCB heat sink.
MCP46XX devices have two terminal W pins, one for
each resistor network.
DS22096B-page 34
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
4.0
FUNCTIONAL OVERVIEW
This data sheet covers a family of thirty-two digital
Potentiometer and Rheostat devices that will be
referred to as MCP4XXX. The MCP4XX1 devices are
the Potentiometer configuration, while the MCP4XX2
devices are the Rheostat configuration.
As the Device Block Diagram shows, there are four
main functional blocks. These are:
•
•
•
•
POR/BOR Operation
Memory Map
Resistor Network
Serial Interface (I2C)
The POR/BOR operation and the memory map are
discussed in this section and the Resistor Network and
I2C operation are described in their own sections. The
Device Commands commands are discussed in
Section 7.0 “Device Commands”.
4.1
POR/BOR Operation
The Power-on Reset is the case where the device has
power applied to it, starting from the VSS level. The
Brown-out Reset occurs when power is applied to the
device, and that power (voltage) drops below the specified range.
4.1.2
BROWN-OUT RESET
When the device powers down, the device VDD will
cross the VPOR/VBOR voltage.
Once the VDD voltage decreases below the VPOR/VBOR
voltage, the Serial Interface is disabled.
If the VDD voltage decreases below the VRAM voltage,
the following may happen:
• Volatile wiper registers become corrupt
• TCON register becomes corrupt
As the voltage recovers above the VPOR/VBOR voltage
see Section 4.1.1 “Power-on Reset”.
Serial commands not completed due to a brown-out
condition may cause the volatile memory location to
become corrupted.
4.2
Memory Map
The device memory map supports 16 locations, of
which three locations are used. Each location is 9-bits
wide (16x9 bits). This memory space is shown in
Table 4-1.
TABLE 4-1:
Address
MEMORY MAP
Function
Memory Type
The device’s RAM retention voltage (VRAM) is lower
than the POR/BOR voltage trip point (VPOR/VBOR). The
maximum VPOR/VBOR voltage is less than 1.8V.
00h
Volatile Wiper 0
RAM
01h
Volatile Wiper 1
RAM
02h
Reserved
When VPOR/VBOR < VDD < 2.7V, the electrical performance may not meet the data sheet specifications. In
this region, the device is capable of incrementing, decrementing, reading and writing to its volatile memory if
the proper serial command is executed.
03h
Reserved
04h
Volatile TCON register
RAM
05h
Reserved
RAM
4.1.1
—
—
06h - 0Fh Reserved
—
POWER-ON RESET
When the device powers up, the device VDD will cross
the VPOR/VBOR voltage. Once the VDD voltage crosses
the VPOR/VBOR voltage the following happens:
• Volatile wiper register is loaded with value
(mid-scale)
• The TCON register is loaded with the default
value
• The device is capable of digital operation
4.2.1
VOLATILE MEMORY (RAM)
There are four volatile memory locations. These are:
• Volatile Wiper 0
• Volatile Wiper 1
(Dual Resistor Network devices only)
• Terminal Control (TCON) register
• Reserved
The volatile memory starts functioning at the RAM
retention voltage (VRAM).
4.2.1.1
Address 05h (Reserved)
This memory location is Reserved and is mapped to
the Status Register of the nonvolatile MCP45XX/46XX
devices. Since the nonvolatile device’s bits are not
used by the volatile device, this location is reserved.
Reading this address will result in a value of 1F7h.
2008-2013 Microchip Technology Inc.
DS22096B-page 35
MCP453X/455X/463X/465X
4.2.1.2
Terminal Control (TCON) Register
This register contains 8 control bits. Four bits are for
Wiper 0, and four bits are for Wiper 1. Register 4-1
describes each bit of the TCON register.
The state of each resistor network terminal connection
is individually controlled. That is, each terminal
connection (A, B and W) can be individually connected/
disconnected from the resistor network. This allows the
system to minimize the currents through the digital
potentiometer.
When the WL1 bit is enabled, writes to the TCON
register bits R1HW, R1A, R1W, and R1B are inhibited.
When the WL0 bit is enabled, writes to the TCON
register bits R0HW, R0A, R0W, and R0B are inhibited.
On a POR/BOR this register is loaded with 1FFh
(9-bits), for all terminals connected. The Host
Controller needs to detect the POR/BOR event and
then update the volatile TCON register value.
Additionally, there is a bit which enables the operation
of General Call commands.
The value that is written to this register will appear on
the resistor network terminals when the serial
command has completed.
DS22096B-page 36
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
REGISTER 4-1:
TCON BITS (ADDRESS = 0x04) (1)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
GCEN
R1HW
R1A
R1W
R1B
R0HW
R0A
R0W
R0B
bit 8
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 8
GCEN: General Call Enable bit
This bit specifies if I2C General Call commands are accepted
1 = Enable Device to “Accept” the General Call Address (0000h)
0 = The General Call Address is disabled
bit 7
R1HW: Resistor 1 Hardware Configuration Control bit
This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin
1 = Resistor 1 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 1 is forced to the hardware pin “shutdown” configuration
bit 6
R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network
1 = P1A pin is connected to the Resistor 1 Network
0 = P1A pin is disconnected from the Resistor 1 Network
bit 5
R1W: Resistor 1 Wiper (P1W pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network
1 = P1W pin is connected to the Resistor 1 Network
0 = P1W pin is disconnected from the Resistor 1 Network
bit 4
R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network
1 = P1B pin is connected to the Resistor 1 Network
0 = P1B pin is disconnected from the Resistor 1 Network
bit 3
R0HW: Resistor 0 Hardware Configuration Control bit
This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin
1 = Resistor 0 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 0 is forced to the hardware pin “shutdown” configuration
bit 2
R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network
1 = P0A pin is connected to the Resistor 0 Network
0 = P0A pin is disconnected from the Resistor 0 Network
bit 1
R0W: Resistor 0 Wiper (P0W pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network
1 = P0W pin is connected to the Resistor 0 Network
0 = P0W pin is disconnected from the Resistor 0 Network
bit 0
R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network
1 = P0B pin is connected to the Resistor 0 Network
0 = P0B pin is disconnected from the Resistor 0 Network
Note 1:
These bits do not affect the wiper register values.
2008-2013 Microchip Technology Inc.
DS22096B-page 37
MCP453X/455X/463X/465X
NOTES:
DS22096B-page 38
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
5.0
RESISTOR NETWORK
5.1
The Resistor Network has either 7-bit or 8-bit
resolution. Each Resistor Network allows zero scale to
full-scale connections. Figure 5-1 shows a block
diagram for the resistive network of a device.
The Resistor Network is made up of several parts.
These include:
• Resistor Ladder
• Wiper
• Shutdown (Terminal Connections)
Devices have either one or two resistor networks,
These are referred to as Pot 0 and Pot 1.
A
RW
RS
RW
R
RAB S
The resistor ladder is a series of equal value resistors
(RS) with a connection point (tap) between the two
resistors. The total number of resistors in the series
(ladder) determines the RAB resistance (see
Figure 5-1). The end points of the resistor ladder are
connected to analog switches, which are connected to
the device Terminal A and Terminal B pins. The RAB
(and RS) resistance has small variations over voltage
and temperature.
For an 8-bit device, there are 256 resistors in a string
between terminal A and terminal B. The wiper can be
set to tap onto any of these 256 resistors, thus providing 257 possible settings (including terminal A and terminal B).
8-Bit
N=
256
(1) (100h)
7-Bit
N=
128
(80h)
For a 7-bit device, there are 128 resistors in a string
between terminal A and terminal B. The wiper can be
set to tap onto any of these 128 resistors, thus providing 129 possible settings (including terminal A and terminal B).
255
(FFh)
127
(7Fh)
Equation 5-1 shows the calculation for the step
resistance.
254
(FEh)
126
(7Eh)
EQUATION 5-1:
RW (1)
RS
Resistor Ladder Module
(1)
RS CALCULATION
RAB
RS = ------------ 256
8-bit Device
R AB
R S = ------------- 128
7-bit Device
W
RW
RS
RW
1
(1) (01h)
1
(01h)
0
(00h)
0
(00h)
(1)
Analog Mux
B
Note 1: The wiper resistance is dependent on
several factors including, wiper code,
device VDD, Terminal voltages (on A, B,
and W), and temperature.
Also for the same conditions, each tap
selection resistance has a small variation.
This RW variation has greater effects on
some specifications (such as INL) for the
smaller resistance devices (5.0 k)
compared to larger resistance devices
(100.0 k).
FIGURE 5-1:
Resistor Block Diagram.
2008-2013 Microchip Technology Inc.
DS22096B-page 39
MCP453X/455X/463X/465X
TABLE 5-1:
A value in the Volatile Wiper register selects which
analog switch to close, connecting the W terminal to
the selected node of the resistor ladder.
The wiper can connect directly to Terminal B or to
Terminal A. A zero-scale connection, connects the Terminal W (wiper) to Terminal B (wiper setting of 000h). A
full-scale connection, connects the Terminal W (wiper)
to Terminal A (wiper setting of 100h or 80h). In these
configurations, the only resistance between Terminal W
and the other Terminal (A or B) is that of the analog
switches.
A wiper setting value greater than full-scale (wiper
setting of 100h for 8-bit device or 80h for 7-bit devices)
will also be a Full-Scale setting (Terminal W (wiper)
connected to Terminal A). Table 5-1 illustrates the full
wiper setting map.
Equation 5-2 illustrates the calculation used to determine the resistance between the wiper and terminal B.
EQUATION 5-2:
RWB CALCULATION
R AB N
R WB = -------------- + R W
256
8-bit Device
N = 0 to 256 (decimal)
R AB N
R WB = -------------- + R W
128
N = 0 to 128 (decimal)
DS22096B-page 40
7-bit Device
Wiper Setting
Properties
7-bit Pot 8-bit Pot
3FFh
081h
3FFh
101h
Reserved (Full-Scale (W = A)),
Increment and Decrement
commands ignored
080h
100h
Full-Scale (W = A),
Increment commands ignored
07Fh
041h
0FFh
081
W=N
040h
080h
W = N (Mid-Scale)
03Fh
001h
07Fh
001
W=N
000h
000h
Zero Scale (W = B)
Decrement command ignored
A POR/BOR event will load the Volatile Wiper register
value with the default value. Table 5-2 shows the
default values offered. Custom POR/BOR options are
available. Contact the local Microchip Sales Office.
TABLE 5-2:
DEFAULT FACTORY
SETTINGS SELECTION
Default POR
Wiper Setting
Each tap point (between the RS resistors) is a
connection point for an analog switch. The opposite
side of the analog switch is connected to a common
signal, which is connected to the Terminal W (Wiper)
pin.
VOLATILE WIPER VALUE VS.
WIPER POSITION MAP
Typical
RAB Value
Wiper
-502
5.0 k
Mid-scale
80h
40h
-103
10.0 k Mid-scale
80h
40h
-503
50.0 k Mid-scale
80h
40h
-104
100.0 k Mid-scale
80h
40h
Resistance
Code
5.2
Wiper Code
8-bit
7-bit
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
5.3
5.3.2
Shutdown
Shutdown is used to minimize the device’s current
consumption. The MCP4XXX achieves this through the
Terminal Control Register (TCON).
5.3.1
TERMINAL CONTROL REGISTER
(TCON)
The Terminal Control (TCON) register is a volatile
register used to configure the connection of each
resistor network terminal pin (A, B, and W) to the
Resistor Network. This bits are described in
Register 4-1.
When the RxHW bit is a “0”, the selected resistor network is forced into the following state:
INTERACTION OF RxHW BIT AND
RxA, RxW, AND RxB BITS (TCON
REGISTER)
Using the TCON bits allows each resistor network
(Pot 0 and Pot 1) to be individually “shutdown”.
The state of the RxHW bit does NOT corrupt the other
bit values in the TCON register, nor the value of the
Volatile Wiper registers. When the Shutdown mode is
exited (RxHW changes state from “0” to “1”):
• The device returns to the Wiper setting specified
by the Volatile Wiper value
• The RxA, RxB, and RxW bits return to controlling
the terminal connection state of that resistor network
• The PxA terminal is disconnected
• The PxW terminal is simultaneously connected to
the PxB terminal (see Figure 5-2)
• The Serial Interface is NOT disabled, and all
Serial Interface activity is executed
Alternate low power configurations may be achieved
with the RxA, RxW, and RxB bits.
Note 1: The RxHW bits are identical to the RxHW
bits of the MCP41XX/42XX devices. The
MCP42XX devices also have a SHDN pin
which forces the resistor network into the
same state as that resistor networks
RxHW bit.
2: When RxHW = “0”, the state of the TCON
register RxA, RxW, and RxB bits is overridden (ignored). When the state of the
RxHW bit returns to “1”, the TCON
register RxA, RxW, and RxB bits return to
controlling the terminal connection state.
In other words, the RxHW bit does not
corrupt the state of the RxA, RxW, and
RxB bits.
Resistor Network
A
FIGURE 5-2:
Configuration.
W
B
Resistor Network Shutdown
2008-2013 Microchip Technology Inc.
DS22096B-page 41
MCP453X/455X/463X/465X
NOTES:
DS22096B-page 42
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
6.0
SERIAL INTERFACE (I2C)
6.1
The MCP45XX/46XX devices support the I2C serial
protocol. The MCP45XX/46XX I2C’s module operates
in Slave mode (does not generate the serial clock).
Figure 6-1 shows a typical I2C Interface connection. All
I2C interface signals are high-voltage tolerant.
The MCP45XX/46XX devices use the two-wire I2C
serial interface. This interface can operate in standard,
fast or High-Speed mode. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data, as receiver. The bus has to be controlled by a master device which generates the serial
clock (SCL), controls the bus access and generates the
START and STOP conditions. The MCP45XX/46XX
device works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated. Communication is initiated by the master (microcontroller) which
sends the START bit, followed by the slave address
byte. The first byte transmitted is always the slave
address byte, which contains the device code, the
address bits, and the R/W bit.
2C
Refer to the Phillips I
the I2C specifications.
document for more details of
Typical I2C Interface Connections
MCP4XXX
Host
Controller
SCL
SCL
SDA
SDA
I/O
(1)
HVC/A0
(2)
A1 (2, 3)
A2 (2, 3)
Note 1: If High voltage commands are desired,
some type of external circuitry needs to
be implemented.
2: These pins have internal pull-ups. If
faster rise times are required, then
external pull-ups should be added.
3: This pin could be tied high, low, or
connected to an I/O pin of the Host
Controller.
FIGURE 6-1:
Diagram.
Typical
I2C
Interface Block
Signal Descriptions
The I2C interface uses up to five pins (signals). These
are:
•
•
•
•
•
SDA (Serial Data)
SCL (Serial Clock)
A0 (Address 0 bit)
A1 (Address 1 bit)
A2 (Address 2 bit)
6.1.1
SERIAL DATA (SDA)
The Serial Data (SDA) signal is the data signal of the
device. The value on this pin is latched on the rising
edge of the SCL signal when the signal is an input.
With the exception of the START and STOP conditions,
the High or Low state of the SDA pin can only change
when the clock signal on the SCL pin is LOW. During
the high period of the clock the SDA pin’s value (high or
low) must be stable. Changes in the SDA pin’s value
while the SCL pin is HIGH will be interpreted as a
START or a STOP condition.
6.1.2
SERIAL CLOCK (SCL)
The Serial Clock (SCL) signal is the clock signal of the
device. The rising edge of the SCL signal latches the
value on the SDA pin. The MCP45XX/46XX supports
three I2C interface clock modes:
• Standard mode: clock rates up to 100 kHz
• Fast mode: clock rates up to 400 kHz
• High-Speed mode (HS mode): clock rates up to
3.4 MHz
The MCP4XXX will not stretch the clock signal (SCL)
since memory read accesses occur fast enough.
Depending on the clock rate mode, the interface will
display different characteristics.
6.1.3
THE ADDRESS BITS (A2:A1:A0)
There are up to three hardware pins used to specify the
device address. The number of address pins is
determined by the part number.
Address 0 is multiplexed with the High Voltage
Command (HVC) function. So the state of A0 is latched
on the MCP4XXX’s POR/BOR event.
The state of the A2 and A1 pins should be static, that is
they should be tied high or tied low.
6.1.3.1
The High Voltage Command (HVC)
Signal
The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that
the command, or sequence of commands, are in the
High Voltage mode. High Voltage commands are supported for compatibility with the nonvolatile devices.
The HVC pin has an internal resistor connection to the
MCP45XX/46XXs internal VDD signal.
2008-2013 Microchip Technology Inc.
DS22096B-page 43
MCP453X/455X/463X/465X
6.2
I2C Operation
6.2.1.3
The MCP45XX/46XX’s I2C module is compatible with
the Philips I2C specification. The following lists some of
the module’s features:
• 7-bit slave addressing
• Supports three clock rate modes:
- Standard mode, clock rates up to 100 kHz
- Fast mode, clock rates up to 400 kHz
- High-speed mode (HS mode), clock rates up
to 3.4 MHz
• Support Multi-Master Applications
• General call addressing
• Internal weak pull-ups on interface signals
The I2C 10-bit addressing mode is not supported.
The Philips I2C specification only defines the field
types, field lengths, timings, etc. of a frame. The frame
content defines the behavior of the device. The frame
content for the MCP4XXX is defined in Section 7.0.
6.2.1
I2C BIT STATES AND SEQUENCE
Figure 6-8 shows the I2C transfer sequence. The serial
clock is generated by the master. The following
definitions are used for the bit states:
• Start bit (S)
• Data bit
• Acknowledge (A) bit (driven low) /
No Acknowledge (A) bit (not driven low)
• Repeated Start bit (Sr)
• Stop bit (P)
6.2.1.1
2nd Bit
SCL
S
FIGURE 6-2:
6.2.1.2
Start Bit.
Data Bit
The SDA signal may change state while the SCL signal
is LOW. While the SCL signal is HIGH, the SDA signal
MUST be stable (see Figure 6-5).
SDA
1st Bit
SDA
SCL
FIGURE 6-4:
2nd Bit
D0
A
8
9
Acknowledge Waveform.
Not A (A) Response
The A bit has the SDA signal HIGH. Table 6-1 shows
some of the conditions where the Slave Device will
issue a Not A (A).
If an error condition occurs (such as an A instead of A),
then an START bit must be issued to reset the
command state machine.
Event
The Start bit (see Figure 6-2) indicates the beginning of
a data transfer sequence. The Start bit is defined as the
SDA signal falling when the SCL signal is HIGH.
1st Bit
The A bit (see Figure 6-4) is typically a response from
the receiving device to the transmitting device.
Depending on the context of the transfer sequence, the
A bit may indicate different things. Typically, the Slave
device will supply an A response after the Start bit and
8 “data” bits have been received. The A bit has the SDA
signal low.
TABLE 6-1:
Start Bit
SDA
Acknowledge (A) Bit
MCP45XX/46XX A / A
RESPONSES
Acknowledge
Bit
Response
Comment
General Call
A
Slave Address
valid
A
Slave Address
not valid
A
Device memory address
and specified
command
(AD3:AD0 and
C1:C0) are an
invalid combination
A
After device has
received address
and command
N.A.
I2C Module
Resets, or a “Don’t
Care” if the collision occurs on the
Masters “Start bit”.
Bus Collision
Only if GCEN bit is
set
SCL
Data Bit
FIGURE 6-3:
DS22096B-page 44
Data Bit.
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
6.2.1.4
6.2.1.5
Repeated Start Bit
The Repeated Start bit (see Figure 6-5) indicates the
current Master Device wishes to continue communicating with the current Slave Device without releasing the
I2C bus. The Repeated Start condition is the same as
the Start condition, except that the Repeated Start bit
follows a Start bit (with the Data bits + A bit) and not a
Stop bit.
Stop Bit
The Stop bit (see Figure 6-6) Indicates the end of the
I2C Data Transfer Sequence. The Stop bit is defined as
the SDA signal rising when the SCL signal is HIGH.
A Stop bit resets the I2C interface of all MCP4XXX
devices.
SDA A / A
The Start bit is the beginning of a data transfer
sequence and is defined as the SDA signal falling when
the SCL signal is HIGH.
SCL
P
Note 1: A bus collision during the Repeated Start
condition occurs if:
FIGURE 6-6:
Transmit Mode.
•SDA is sampled low when SCL goes
from low to high.
6.2.2
•SCL goes low before SDA is asserted
low. This may indicate that another
master is attempting to transmit a
data "1".
Stop Condition Receive or
CLOCK STRETCHING
“Clock Stretching” is something that the receiving
device can do, to allow additional time to “respond” to
the “data” that has been received.
The MCP4XXX will not stretch the clock signal (SCL)
since memory read accesses occur fast enough.
1st Bit
SDA
6.2.3
If any part of the I2C transmission does not meet the
command format, it is aborted. This can be intentionally
accomplished with a START or STOP condition. This is
done so that noisy transmissions (usually an extra
START or STOP condition) are aborted before they
corrupt the device.
SCL
Sr = Repeated Start
FIGURE 6-5:
Waveform.
ABORTING A TRANSMISSION
Repeat Start Condition
SDA
SCL
S
FIGURE 6-7:
1st Bit
2nd Bit 3rd Bit
4th Bit
5th Bit
6th Bit
7th Bit
8th Bit
A/A
P
Typical 8-Bit I2C Waveform Format.
SDA
SCL
START
Condition
FIGURE 6-8:
Data allowed
to change
Data or
A valid
STOP
Condition
I2C Data States and Bit Sequence.
2008-2013 Microchip Technology Inc.
DS22096B-page 45
MCP453X/455X/463X/465X
6.2.4
ADDRESSING
The address byte is the first byte received following the
START condition from the master device. The address
contains four (or more) fixed bits and (up to) three user
defined hardware address bits (pins A2, A1, and A0).
These 7-bits address the desired I2C device. The
A7:A4 address bits are fixed to “0101” and the device
appends the value of following three address pins (A2,
A1, A0). Address pins that are not present on the
device are pulled up (a bit value of ‘1’).
Since there are up to three address bits controlled by
hardware pins, there may be up to eight MCP4XXX
devices on the same I2C bus.
Figure 6-9 shows the slave address byte format, which
contains the seven address bits. There is also a read/
write bit. Table 6-2 shows the fixed address for each
device.
Hardware Address Pins
The hardware address bits (A2, A1, and A0)
correspond to the logic level on the associated address
pins. This allows up to eight devices on the bus.
These pins have a weak pull-up enabled when the
VDD < VBOR. The weak pull-up utilizes the “smart”
pull-up technology and exhibits the same characteristics as the High-voltage tolerant I/O structure.
The state of the A0 address pin is latch on POR/BOR.
This is required since High-Voltage commands force
this pin (HVC/A0) to the VIHH level.
Slave Address
S A6 A5 A4 A3 A2 A1 A0 R/W
“0” “1” “0” “1”
See Table 6-2
Start
bit
A/A
R/W bit
R/W = 0 = write
R/W = 1 = read
A bit (controlled by slave device)
A = 0 = Slave Device Acknowledges byte
A = 1 = Slave Device does not Acknowledge byte
FIGURE 6-9:
I2C Control Byte.
TABLE 6-2:
Slave Address Bits in the
DEVICE SLAVE ADDRESSES
Device
Address
MCP45X1 ‘0101 11’b + A0
Comment
Supports up to 2
devices. (Note 1)
MCP45X2 ‘0101 1’b + A1:A0 Supports up to 4
devices. (Note 1)
MCP46X1 ‘0101’b + A2:A1:A0 Supports up to 8
devices. (Note 1)
MCP46X2 ‘0101 1’b + A1:A0 Supports up to 4
devices. (Note 1)
Note 1: A0 is used for High-Voltage commands,
and the value is latched at POR.
6.2.5
SLOPE CONTROL
The MCP45XX/46XX implements slope control on the
SDA output.
As the device transitions from HS mode to FS mode,
the slope control parameter will change from the HS
specification to the FS specification.
For Fast (FS) and High-Speed (HS) modes, the device
has a spike suppression and a Schmidt trigger at SDA
and SCL inputs.
DS22096B-page 46
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
6.2.6
HS MODE
After switching to the High-Speed mode, the next
transferred byte is the I2C control byte, which specifies
the device to communicate with, and any number of
data bytes plus acknowledgements. The Master
Device can then either issue a Repeated Start bit to
address a different device (at High-Speed), or a Stop bit
to return to Fast/Standard bus speed. After the Stop bit,
any other Master Device (in a Multi-Master system) can
arbitrate for the I2C bus.
2
The I C specification requires that a high-speed mode
device must be ‘activated’ to operate in High-Speed
(3.4 Mbit/s) mode. This is done by the Master sending
a special address byte following the START bit. This
byte is referred to as the high-speed Master Mode
Code (HSMMC).
The MCP45XX/46XX device does not acknowledge
this byte. However, upon receiving this command, the
device switches to HS mode. The device can now communicate at up to 3.4 Mbit/s on SDA and SCL lines.
The device will switch out of the HS mode on the next
STOP condition.
See Figure 6-10 for illustration of HS mode command
sequence.
For more information on the HS mode, or other I2C
modes, please refer to the Phillips I2C specification.
The master code is sent as follows:
1.
2.
3.
6.2.6.1
START condition (S)
High-Speed Master Mode Code (0000 1XXX),
The XXX bits are unique to the high-speed (HS)
mode Master.
No Acknowledge (A)
Slope Control
The slope control on the SDA output is different
between the Fast/Standard Speed and the High-Speed
clock modes of the interface.
6.2.6.2
Pulse Gobbler
The pulse gobbler on the SCL pin is automatically
adjusted to suppress spikes < 10 ns during HS mode.
F/S-mode
HS-mode
P
F/S-mode
S ‘0 0 0 0 1 X X X’b
A Sr ‘Slave Address’ R/W A
HS Select Byte
Control Byte
“Data”
Command/Data Byte(s)
S = Start bit
Sr = Repeated Start bit
A = Acknowledge bit
A = Not Acknowledge bit
R/W = Read/Write bit
P = Stop bit (Stop condition terminates HS Mode)
FIGURE 6-10:
A/A
HS-mode continues
Sr ‘Slave Address’ R/W A
Control Byte
HS Mode Sequence.
2008-2013 Microchip Technology Inc.
DS22096B-page 47
MCP453X/455X/463X/465X
6.2.7
GENERAL CALL
TABLE 6-3:
GENERAL CALL COMMANDS
The General Call is a method that the “Master” device
can communicate with all other “Slave” devices. In a
Multi-Master application, the other Master devices are
operating in Slave mode. The General Call address
has two documented formats. These are shown in
Figure 6-11. We have added a MCP45XX/46XX format
in this figure as well.
7-bit
Command (1, 2, 3)
This will allow customers to have multiple I2C Digital
Potentiometers on the bus and have them operate in a
synchronous fashion (analogous to the DAC Sync pin
functionality). If these MCP45XX/46XX 7-bit commands conflict with other I2C devices on the bus, then
the customer will need two I2C busses and ensure that
the devices are on the correct bus for their desired
application functionality.
Dual Pot devices cannot update both Pot0 and Pot1
from a single command. To address this, there are
General Call commands for the Wiper 0, Wiper 1, and
the TCON registers.
Table 6-3 shows the General Call commands. Three
commands are specified by the I2C specification and
are not applicable to the MCP45XX/46XX (so command is Not Acknowledged) The MCP45XX/46XX
General Call commands are Acknowledge. Any other
command is Not Acknowledged.
Note:
There is only one General Call command
per General Call control byte (address).
Any additional General Call commands
are ignored and Not Acknowledged.
DS22096B-page 48
Comment
‘1000 00d’b
Write Next Byte (Third Byte) to
Volatile Wiper 0 Register
‘1001 00d’b
Write Next Byte (Third Byte) to
Volatile Wiper 1 Register
‘1100 00d’b
Write Next Byte (Third Byte) to
TCON Register
‘1000 010’b
or
‘1000 011’b
Increment Wiper 0 Register
‘1001 010’b
or
‘1001 011’b
Increment Wiper 1 Register
‘1000 100’b
or
‘1000 101’b
Decrement Wiper 0 Register
‘1001 100’b
or
‘1001 101’b
Decrement Wiper 1 Register
Note 1:
2:
3:
Any other code is Not Acknowledged.
These codes may be used by other
devices on the I2C bus.
The 7-bit command always appends a “0”
to form 8-bits. .
“d” is the D8 bit for the 9-bit write value.
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Second Byte
S 0 0
0
0
0 0
0
0 A X X X X X
General Call Address
X
X
0
A P
“7-bit Command”
Reserved 7-bit Commands (By I2C Specification - Philips # 9398 393 40011, Ver. 2.1 January 2000)
‘0000 011’b - Reset and write programmable part of slave address by hardware.
‘0000 010’b - Write programmable part of slave address by hardware.
‘0000 000’b - NOT Allowed
MCP45XX/MCP46XX 7-bit Commands
‘1000 01x’b - Increment Wiper 0 Register.
‘1001 01x’b - Increment Wiper 1 Register.
‘1000 10x’b - Decrement Wiper 0 Register.
‘1001 10x’b - Decrement Wiper 1 Register.
The Following is a Microchip Extension to this General Call Format
Second Byte
S 0
0 0
0
0 0
0
0 A X X X X X
General Call Address
X d
0
Third Byte
A d
“7-bit Command”
d
d
d
d
d
d
d A P
“0” for General Call Command
MCP45XX/MCP46XX 7-bit Commands
‘1000 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 0 Register.
‘1001 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 1 Register.
‘1100 00d’b - Write Next Byte (Third Byte) to TCON Register.
The Following is a “Hardware General Call” Format
Second Byte
S 0
0 0
0
0
0 0
0
General Call Address
FIGURE 6-11:
A X X X X X
“7-bit Command”
X
n occurrences of (Data + A)
X
1
A X X X X X X X X A P
This indicates a “Hardware General Call”
MCP45XX/MCP46XX will ignore this byte and
all following bytes (and A), until
a Stop bit (P) is encountered.
General Call Formats.
2008-2013 Microchip Technology Inc.
DS22096B-page 49
MCP453X/455X/463X/465X
NOTES:
DS22096B-page 50
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
7.0
DEVICE COMMANDS
7.1
The MCP4XXX’s I2C command formats are specified in
this section. The I2C protocol does not specify how
commands are formatted.
The MCP4XXX supports four basic commands.
Depending on the location accessed determines the
commands that are supported.
For the Volatile Wiper registers, these commands are:
•
•
•
•
Write Data
Read Data
Increment Data
Decrement Data
For the TCON Register, these commands are:
• Write Data
• Read Data
These commands have formats for both a single
command or continuous commands. These commands
are shown in Table 7-1.
Each command has two operational states. These
operational states are referred to as:
• Normal Serial Commands
• High-Voltage Serial Commands
Note:
TABLE 7-1:
High Voltage commands are supported
for compatibility with nonvolatile devices
in the family.
I2C COMMANDS
Command
Operation
Mode
# of Bit
Clocks (1)
Operates on
Volatile/
Nonvolatile
Memory
Write Data
Single
29
Both
Continuous 18n + 11 Volatile Only
Read Data
Single
29
Both
Random
48
Both
Continuous 18n + 11 Both
Increment
Single
20
Volatile Only
Continuous 9n + 11 Volatile Only
Decrement Single
20
Volatile Only
Continuous 9n + 11 Volatile Only
Note 1: “n” indicates the number of times the
command operation is to be repeated.
Command Byte
The MCP4XXX’s Command Byte has three fields: the
Address, the Command Operation, and two data bits,
(see Figure 7-1). Currently only one of the data bits is
defined (D8).
The device memory is accessed when the Master
sends a proper Command Byte to select the desired
operation. The memory location getting accessed is
contained in the Command Byte’s AD3:AD0 bits. The
action desired is contained in the Command Byte’s
C1:C0 bits (see Table 7-1). C1:C0 determines if the
desired memory location will be read, written,
Incremented (wiper setting +1) or Decremented (wiper
setting -1). The Increment and Decrement commands
are only valid on the volatile wiper registers.
If the Address bits and Command bits are not a valid
combination, then the MCP4XXX will generate a Not
Acknowledge pulse to indicate the invalid combination.
The I2C Master device must then force a Start Condition to reset the MCP4XXX’s 2C module.
D9 and D8 are the most significant bits for the digital
potentiometer’s wiper setting. The 8-bit devices utilize
D8 as their MSb while the 7-bit devices utilize D7 (from
the data byte) as it’s MSb.
COMMAND BYTE
A A A A A C C D D A
D D D D 1 0 9 8
3 2 1 0
MSbits (Data)
MCP4XXX
Memory Address
Command Operation bits
00 = Write Data
01 = Increment
10 = Decrement
11 = Read Data
FIGURE 7-1:
Command Byte Format.
Normal serial commands are those where the HVC pin
is driven to VIH or VIL. With High-Voltage Serial Commands, the HVC pin is driven to VIHH. In each mode,
there are four possible commands.
Table 7-2 shows the supported commands for each
memory location.
Table 7-3 shows an overview of all the device commands and their interaction with other device features.
2008-2013 Microchip Technology Inc.
DS22096B-page 51
MCP453X/455X/463X/465X
TABLE 7-2:
MEMORY MAP AND THE SUPPORTED COMMANDS
Address
Command Operation
Value
00h
01h
Function
Volatile Wiper 0
Volatile Wiper 1
Data
(10-bits) (1)
Write Data
nn nnnn nnnn
Read Data (3)
nn nnnn nnnn
Increment Wiper
—
Decrement Wiper
—
Write Data
nn nnnn nnnn
Read Data (3)
nn nnnn nnnn
Increment Wiper
—
Decrement Wiper
—
02h
Reserved
—
—
03h
Reserved
—
—
04h
(2)
Volatile TCON Register Write Data
05h
Reserved
06h - 0Fh (2) Reserved
Note 1:
2:
3:
nn nnnn nnnn
(3)
nn nnnn nnnn
Read Data (3)
nn nnnn nnnn
Read Data
(2)
—
Comment
Maps to nonvolatile
MCP45XX/46XX device’s
STATUS Register
—
The Data memory is only 9-bits wide, so the MSb is ignored by the device.
Increment or Decrement commands are invalid for these addresses.
I2C read operation will read 2 bytes, of which the 10-bits of data are contained within.
DS22096B-page 52
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
7.2
Data Byte
7.3
Only the Read Command and the Write Command
have Data Byte(s).
The Write command concatenates the 8-bits of the
Data Byte with the one data bit (D8) contained in the
Command Byte to form 9-bits of data (D8:D0). The
Command Byte format supports up to 9-bits of data so
that the 8-bit resistor network can be set to Full-Scale
(100h or greater). This allows wiper connections to
Terminal A and to Terminal B. The D9 bit is currently
unused.
Error Condition
If the four address bits received (AD3:AD0) and the two
command bits received (C1:C0) are a valid combination, the MCP4XXX will Acknowledge the I2C bus.
If the address bits and command bits are an invalid
combination, then the MCP4XXX will Not Acknowledge
the I2C bus.
Once an error condition has occurred, any following
commands are ignored until the I2C bus is reset with a
Start Condition.
7.3.1
ABORTING A TRANSMISSION
A Restart or Stop condition in the expected data bit
position will abort the current command sequence and
data will not be written to the MCP4XXX.
TABLE 7-3:
COMMANDS
# of Bits
High
Voltage
(VIHH) on
HVC pin?
Write Data
29
—
Read Data
29
—
Increment Wiper
20
—
Decrement Wiper
20
—
High Voltage Write Data
29
Yes
High Voltage Read Data
29
Yes
High Voltage Increment Wiper
20
Yes
High Voltage Decrement Wiper
20
Yes
Command Name
2008-2013 Microchip Technology Inc.
DS22096B-page 53
MCP453X/455X/463X/465X
7.4
Write Data
Normal and High Voltage
The Write command can be issued to both the volatile
and nonvolatile memory locations. The format of the
command (see Figure 7-2), includes the I2C Control
Byte, an A bit, the MCP4XXX Command Byte, an A bit,
the MCP4XXX Data Byte, an A bit, and a Stop (or
Restart) condition. The MCP4XXX generates the A/A
bits.
A Write command to a volatile memory location
changes that location after a properly formatted Write
Command and the A/A clock have been received.
7.4.1
SINGLE WRITE TO VOLATILE
MEMORY
For volatile memory locations, data is written to the
MCP4XXX after every byte transfer (during the
Acknowledge). If a Stop or Restart condition is generated during a data transfer (before the A), the data will
not be written to the MCP4XXX. After the A bit, the
master can initiate the next sequence with a Stop or
Restart condition.
7.4.2
CONTINUOUS WRITES TO
VOLATILE MEMORY
A continuous write mode of operation is possible when
writing to the volatile memory registers (address 00h,
01h, and 04h). This continuous write mode allows
writes without a Stop or Restart condition or repeated
transmissions of the I2C Control Byte. Figure 7-3
shows the sequence for three continuous writes. The
writes do not need to be to the same volatile memory
address. The sequence ends with the master sending
a STOP or RESTART condition.
7.4.3
THE HIGH VOLTAGE COMMAND
(HVC) SIGNAL
The High Voltage Command (HVC) signal is
multiplexed with Address 0 (A0) and is used to indicate
that the command, or sequence of commands, are in
the High Voltage operational state. High Voltage
commands allow the device’s WiperLock Technology
and write protect features to be enabled and disabled.
The HVC pin has an internal resistor connection to the
MCP45XX/46XXs internal VDD signal.
Refer to Figure 7-2 for the byte write sequence.
DS22096B-page 54
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Write bit
Fixed
Address
S 0
1
Device
Memory
Address
Variable
Address
0 1 A2 A1 A0 0
A
AD AD AD AD
3 2 1 0 0
0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P
WRITE Command
Control Byte
Write bit
Fixed
Address
S 0 1
Variable
Address
0 1 A2 A1 A0 0 A
Device
Memory
Address
Write “Data” bits
Command
AD AD AD AD
3 2 1 0 0
0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A
WRITE Command
Control Byte
AD AD AD AD
3 2 1 0 0
Write Data bits
0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A
WRITE Command
AD AD AD AD
3 2 1 0 0
Write Data bits
STOP bit
0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P
WRITE Command
FIGURE 7-3:
Write Data bits
I2C Write Sequence.
FIGURE 7-2:
Note:
Write “Data” bits
Command
Write Data bits
Only functions when writing the volatile wiper registers (AD3:AD0 = 00h, 01h, and 04h)
or the TCON register.
I2C Continuous Volatile Wiper Write.
2008-2013 Microchip Technology Inc.
DS22096B-page 55
MCP453X/455X/463X/465X
7.5
Read Data
Normal and High Voltage
7.5.1
SINGLE READ
Figure 7-4 shows the waveforms for a single read.
The Read command can be issued to both the volatile
and nonvolatile memory locations. The format of the
command (see Figure 7-4) includes the Start condition, I2C Control Byte (with R/W bit set to “0”), A bit,
MCP4XXX Command Byte, A bit, followed by a
Repeated Start bit, I2C Control Byte (with R/W bit set to
“1”), and the MCP4XXX transmitting the requested
Data High Byte, A bit, the Data Low Byte, the Master
generating the A, and Stop condition.
For single reads, the master sends a STOP or
RESTART condition after the data byte is sent from the
slave.
The I2C Control Byte requires the R/W bit equal to a
logic one (R/W = 1) to generate a read sequence. The
memory location read will be the last address
contained in a valid write MCP4XXX Command Byte or
address 00h, if no write operations have occurred since
the device was reset (Power-on Reset or Brown-out
Reset).
7.5.2
Read operations initially include the same address byte
sequence as the write sequence (shown in Figure 6-9).
This sequence is followed by another control byte
(including the Start condition and Acknowledge) with
the R/W bit equal to a logic one (R/W = 1) to indicate a
read. The MCP4XXX will then transmit the data contained in the addressed register. This is followed by the
master generating an A bit in preparation for more data,
or an A bit followed by a Stop. The sequence is ended
with the master generating a Stop or Restart condition.
The internal address pointer is maintained.
7.5.1.1
Random Read
Figure 7-5 shows the sequence for a Random Reads.
Refer to Figure 7-5 for the random byte read
sequence.
CONTINUOUS READS
Continuous reads allow the device’s memory to be
read quickly. Continuous reads are possible to all memory locations. If a nonvolatile memory write cycle is
occurring, then Read commands may only access the
volatile memory locations.
Figure 7-6 shows the sequence for three continuous
reads.
For continuous reads, instead of transmitting a STOP
or RESTART condition after the data transfer, the master reads the next data byte. The sequence ends with
the master Not Acknowledging and then sending a
STOP or RESTART.
7.5.3
THE HIGH VOLTAGE COMMAND
(HVC) SIGNAL
The High Voltage Command (HVC) signal is
multiplexed with Address 0 (A0) and is used to indicate
that the command, or sequence of commands, are in
the High Voltage mode. High Voltage commands allow
the device’s WiperLock Technology, and write protect
features to be enabled and disabled.
The HVC pin has an internal resistor connection to the
MCP4XXXs internal VDD signal.
7.5.4
IGNORING AN I2C TRANSMISSION AND
“FALLING OFF” THE BUS
The MCP4XXX expects to receive entire, valid I2C
commands, and will assume any command not
defined as a valid command is due to a bus corruption,
and will enter a passive high condition on the SDA signal. All signals will be ignored until the next valid Start
condition and Control Byte are received.
DS22096B-page 56
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Read bit
S 0
1
STOP bit
Variable
Address
Fixed
Address
Read Data bits
0 1 A2 A1 A0 1
A 0
0
0
0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2
0 0 0
P
Read bits
Control Byte
Note 1: Master Device is responsible for A/A signal. If an A signal occurs, the MCP45XX/46XX will
abort this transfer and release the bus.
2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the
Master Device can generate a Stop or Repeated Start condition.
3: The MCP45XX/46XX retains the last “Device Memory Address” that it has received. This is
the MCP45XX/46XX does not “corrupt” the “Device Memory Address” after Repeated Start or
Stop conditions.
4: The Device Memory Address pointer defaults to 00h on POR and BOR conditions.
I2C Read (Last Memory Address Accessed).
FIGURE 7-4:
Write bit
Fixed
Address
S 0 1
0
Repeated Start bit
Device
Memory
Address
Variable
Address
1 A2 A1 A0 0
A
Command
AD AD AD AD
3 2 1 0 1
1
x X A Sr
READ Command
Control Byte
STOP bit
Read bit
0
1 0
1 A2 A1 A0 1
A 0
Control Byte
Read Data bits
0
0
0 0 0
0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2
P
Read bits
Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will
abort this transfer and release the bus.
2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the
Master Device can generate a Stop or Repeated Start condition.
3: The MCP45XX/46XX retains the last “Device Memory Address” that it has received. This is
the MCP45XX/46XX does not “corrupt” the “Device Memory Address” after Repeated Start or
Stop conditions.
FIGURE 7-5:
I2C Random Read.
2008-2013 Microchip Technology Inc.
DS22096B-page 57
MCP453X/455X/463X/465X
Read bit
Fixed
Address
S 0 1
0
Variable
Address
Read Data bits
1 A2 A1 A0 1 A
0
0
0
0 0 0
0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A1
Read bits
Control Byte
Read Data bits
0
0
0
0 0 0
0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A1
STOP bit
Read Data bits
0
0
0
0 0 0
0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2
P
Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will
abort this transfer and release the bus.
2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the
Master Device can generate a Stop or Repeated Start condition.
FIGURE 7-6:
DS22096B-page 58
I2C Continuous Reads.
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
7.6
TABLE 7-4:
Increment Wiper
Normal and High Voltage
Current Wiper
Setting
The Increment Command provides a quick and easy
method to modify the potentiometer’s wiper by +1 with
minimal overhead. The Increment Command will only
function on the volatile wiper setting memory locations
00h and 01h.
Note:
Table 7-2 shows the valid addresses for
the Increment Wiper command. Other
addresses are invalid.
When executing an Increment Command, the volatile
wiper setting will be altered from n to n+1 for each
Increment Command received. The value will increment up to 100h maximum on 8-bit devices, and 80h on
7-bit devices. If multiple Increment Commands are
received after the value has reached 100h (or 80h), the
value will not be incremented further. Table 7-4 shows
the Increment Command versus the current volatile
wiper value.
Write bit
Device
Memory
Address
3FFh
081h
3FFh
101h
Reserved
No
(Full-Scale (W = A))
080h
100h
Full-Scale (W = A)
07Fh
041h
0FFh
081
W=N
040h
080h
W = N (Mid-Scale)
03Fh
001h
07Fh
001
W=N
000h
000h
Zero Scale (W = B) Yes
Note:
The advantage of using an Increment Command
instead of a read-modify-write series of commands is
speed and simplicity. The wiper will transition after
each Command Acknowledge when accessing the volatile wiper registers.
Variable
Address
8-bit
Pot
No
Yes
THE HIGH VOLTAGE COMMAND
(HVC) SIGNAL
The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that
the command, or sequence of commands, are in the
High Voltage mode. An HVC/A0 pin voltage > VIHH
(~8.5V) puts the MCP45XX/46XX device into the High
Voltage mode.
The command sequence can go from an
increment to any other valid command for
the specified address.
Fixed
Address
Increment
Command
Operates?
Wiper (W)
Properties
7-bit
Pot
7.6.1
Refer to Figure 7-7 for the Increment Command
sequence. The sequence is terminated by the Stop
condition. So when executing a continuous command
string, the Increment command can be followed by any
other valid command. This means that writes do not
need to be to the same volatile memory address.
Note:
INCREMENT OPERATION VS.
VOLATILE WIPER VALUE
There is a required delay after the HVC pin
is driven to the VIHH level to the 1st edge
of the SCL pin.
The HVC pin has an internal resistor connection to the
MCP45XX/46XXs internal VDD signal.
Command
AD AD AD AD
AD AD AD AD
S 0 1 0 1 A2 A1 A0 0 A 3 2 1 0 0 1 x X A 4 3 2 1 0 1 x X A P
Control Byte
INCR Command (n+1)
(2)
INCR Command (n+2)
Note1: Increment Command (INCR) only functions when accessing the volatile wiper
registers (AD3:AD0 = 0h and 1h).
2: This command sequence does not need to terminate (using the Stop bit) and can
change to any other desired command sequence (Increment, Read or Write).
FIGURE 7-7:
I2C Increment Command Sequence.
2008-2013 Microchip Technology Inc.
DS22096B-page 59
MCP453X/455X/463X/465X
7.7
TABLE 7-5:
Decrement Wiper
Normal and High Voltage
Current Wiper
Setting
The Decrement Command provides a quick and easy
method to modify the potentiometer’s wiper by -1, with
minimal overhead. The Decrement Command will only
function on the volatile wiper setting memory locations
00h and 01h.
Note:
Table 7-2 shows the valid addresses for
the Decrement Wiper command. Other
addresses are invalid.
When executing a Decrement Command, the volatile
wiper setting will be altered from n to n-1 for each
Decrement Command received. The value will
decrement down to a minimum of 000h. If multiple Decrement Commands are received after the value has
reached 000h, the value will not be decremented further. Table 7-5 shows the Increment Command versus
the current volatile wiper value.
Refer to Figure 7-8 for the Decrement Command
sequence. The sequence is terminated by the Stop
condition. So when executing a continuous command
string, The Increment command can be followed by any
other valid command. this means that writes do not
need to be to the same volatile memory address.
Note:
The command sequence can go from an
increment to any other valid command for
the specified address.
The advantage of using a Decrement Command
instead of a read-modify-write series of commands is
speed and simplicity. The wiper will transition after each
Command Acknowledge when accessing the volatile
wiper registers.
Write bit
Fixed
Address
Variable
Address
S 0 1 0 1 A2 A1 A0 0 A
Control Byte
DECREMENT OPERATION VS.
VOLATILE WIPER VALUE
Wiper (W)
Properties
Decrement
Command
Operates?
7-bit
Pot
8-bit
Pot
3FFh
081h
3FFh
101h
Reserved
No
(Full-Scale (W = A))
080h
100h
Full-Scale (W = A)
07Fh
041h
0FFh
081
W=N
040h
080h
W = N (Mid-Scale)
03Fh
001h
07Fh
001
W=N
000h
000h
Zero Scale (W = B) No
7.7.1
Yes
Yes
THE HIGH VOLTAGE COMMAND
(HVC) SIGNAL
The High Voltage Command (HVC) signal is
multiplexed with Address 0 (A0) and is used to indicate
that the command, or sequence of commands, are in
the High Voltage mode. An HVC/A0 pin voltage > VIHH
(~8.5V) puts the MCP45XX/46XX device into the High
Voltage mode.
Note:
There is a required delay after the HVC pin
is driven to the VIHH level to the 1st edge
of the SCL pin.
The HVC pin has an internal resistor connection to the
MCP45XX/46XXs internal VDD signal.
Device
Memory
Address Command
AD AD AD AD
AD AD AD AD
3 2 1 0 1 0 X X A 4 3 2 1 1 0 X X A P
DECR Command (n-1)
(2)
DECR Command (n-2)
Note1: Decrement Command (DECR) only functions when accessing the volatile wiper
registers (AD3:AD0 = 0h and 1h).
2: This command sequence does not need to terminate (using the Stop bit) and can
change to any other desired command sequence (INCR, Read, or Write).
FIGURE 7-8:
DS22096B-page 60
I2C Decrement Command Sequence.
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
8.0
APPLICATIONS EXAMPLES
Nonvolatile digital potentiometers have a multitude of
practical uses in modern electronic circuits. The most
popular uses include precision calibration of set point
thresholds, sensor trimming, LCD bias trimming, audio
attenuation, adjustable power supplies, motor control
overcurrent trip setting, adjustable gain amplifiers and
offset trimming. The MCP453X/455X/463X/465X
devices can be used to replace the common mechanical trim pot in applications where the operating and
terminal voltages are within CMOS process limitations
(VDD = 2.7V to 5.5V).
8.1
Techniques to force the HVC pin
to VIHH
The circuit in Figure 8-1 shows a method using the
TC1240A doubling charge pump. When the SHDN pin
is HIGH, the TC1240A is off, and the level on the HVC
pin is controlled by the PIC® microcontrollers (MCUs)
IO2 pin.
When the SHDN pin is low, the TC1240A is on and the
VOUT voltage is 2 * VDD. The resistor R1 allows the
HVC pin to go higher than the voltage such that the PIC
MCU’s IO2 pin “clamps” at approximately VDD.
The circuit in Figure 8-2 shows the method used on the
MCP402X nonvolatile Digital Potentiometer Evaluation
Board (Part Number: MCP402XEV). This method
requires that the system voltage be approximately 5V.
This ensures that when the PIC10F206 enters a
brown-out condition, there is an insufficient voltage
level on the HVC pin to change the stored value of the
wiper. The MCP402X nonvolatile Digital Potentiometer
Evaluation Board User’s Guide (DS51546) contains a
complete schematic.
GP0 is a general purpose I/O pin, while GP2 can either
be a general purpose I/O pin or it can output the internal
clock.
For the serial commands, configure the GP2 pin as an
input (high impedance). The output state of the GP0 pin
will determine the voltage on the HVC pin (VIL or VIH).
For high-voltage serial commands, force the GP0
output pin to output a high level (VOH), and configure
the GP2 pin to output the internal clock. This will form
a charge pump and increase the voltage on the HVC
pin (when the system voltage is approximately 5V).
PIC10F206
R1
GP0
MCP4XXX
PIC MCU
TC1240A
C+
VIN
CSHDN
VOUT
IO1
R1
IO2
C1
MCP45XX
HVC MCP46XX
C2
GP2
HVC
C1
C2
FIGURE 8-2:
MCP4XXX Nonvolatile
Digital Potentiometer Evaluation Board
(MCP402XEV) Implementation to Generate the
VIHH Voltage.
FIGURE 8-1:
Using the TC1240A to
Generate the VIHH Voltage.
2008-2013 Microchip Technology Inc.
DS22096B-page 61
MCP453X/455X/463X/465X
8.2
Using Shutdown
Figure 8-3 shows a possible application circuit where
the independent terminals could be used. Disconnecting the wiper allows the transistor input to be taken to
the Bias voltage level (disconnecting A and or B may be
desired to reduce system current). Disconnecting Terminal A modifies the transistor input by the RBW
rheostat value to the Common B. Disconnecting
Terminal B modifies the transistor input by the RAW
rheostat value to the Common A. The Common A and
Common B connections could be connected to VDD
and VSS.
Common A
Input
A
To base
of Transistor
(or Amplifier)
W
B
Common B
Bias
FIGURE 8-3:
Example Application Circuit
using Terminal Disconnects.
8.3
Note:
‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’
S
P
Nine bits of ‘1’
Start bit
Start
bit
Stop bit
FIGURE 8-4:
Format.
Software Reset Sequence
The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
Master Device. This occurs since the device is monitoring the data bus in Receive mode and can detect the
Start bit which forces an internal Reset.
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP45XX/46XX is driving an A
bit on the I2C bus, or is in output mode (from a Read
command) and is driving a data bit of ‘0’ onto the I2C
bus. In both of these cases, the previous Start bit could
not be generated due to the MCP45XX/46XX holding
the bus low. By sending out nine ‘1’ bits, it is ensured
that the device will see an A bit (the Master Device
does not drive the I2C bus low to acknowledge the data
sent by the MCP45XX/46XX), which also forces the
MCP45XX/46XX to reset.
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the Master
Device was reset while sending a Write command to
the MCP45XX/46XX, AND then as the Master Device
returns to normal operation and issues a Start condition, while the MCP45XX/46XX is issuing an Acknowledge. In this case, if the 2nd Start bit is not sent (and
the Stop bit was sent) the MCP45XX/46XX could initiate a write cycle.
Input
Balance
S
Software Reset Sequence
This technique is documented in AN1028.
At times it may become necessary to perform a Software Reset Sequence to ensure the MCP45XX/46XX
device is in a correct and known I2C Interface state.
This technique only resets the I2C state machine.
Note:
The potential for this erroneous write
ONLY occurs if the Master Device is reset
while sending a Write command to the
MCP45XX/46XX.
The Stop bit terminates the current I2C bus activity. The
MCP45XX/46XX wait to detect the next Start condition.
This sequence does not effect any other I2C devices
which may be on the bus, as they should disregard this
as an invalid command.
This is useful if the MCP45XX/46XX device powers up
in an incorrect state (due to excessive bus noise, ...), or
if the Master Device is reset during communication.
Figure 8-4 shows the communication sequence to software reset the device.
DS22096B-page 62
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
8.4
Figure 8-5 shows two I2C bus configurations. In many
cases, the single I2C bus configuration will be
adequate. For applications that do not want all the
MCP45XX/46XX devices to do General Call support or
have a conflict with General Call commands, the
multiple I2C bus configuration would be used.
Using the General Call Command
The use of the General Call Address Increment, Decrement, or Write commands is analogous to the “Load”
feature (LDAC pin) on some DACs (such as the
MCP4921). This allows all the devices to “Update” the
output level “at the same time”.
For some applications, the ability to update the wiper
values at the same time may be a requirement, since
they delay from writing to one wiper value and then the
next may cause application issues. A possible example
would be a “tuned” circuit that uses several MCP45XX/
46XX in rheostat configuration. As the system condition
changes (temperature, load, ...) these devices need to
be changed (incremented/decremented) to adjust for
the system change. These changes will either be in the
same direction or in opposite directions. With the
Potentiometer device, the customer can either select
the PxB terminals (same direction) or the PxA
terminal(s) (opposite direction).
Single I2C Bus Configuration
Device 1
Host
Controller
Device 4
Device 2
Multiple I2C Bus Configuration
Device 1a
Device 3a
Device na
Host
Bus a
Controller
Figure 8-6 shows that the update of six devices takes
6*TI2CDLY time in “normal” operation, but only
1*TI2CDLY time in “General Call” operation.
Note:
Device n
Device 3
Device 4a
Device 2a
The application system may need to
partition the I2C bus into multiple busses to
ensure that the MCP45XX/46XX General
Call commands do not conflict with the
General Call commands that the other I2C
devices may have defined. Also if only a
portion of the MCP45XX/46XX devices are
to require this synchronous operation,
then the devices that should not receive
these commands should be on the second
I2C bus.
Device 1b
Device 3b
Device nb
Bus b
Device 4b
Device 2b
Device 1n
Device 3n
Device nn
Bus n
Device 2n
FIGURE 8-5:
Configurations.
Device 4n
Typical Application I2C Bus
Normal Operation
INC
POT01
TI2CDLY
INC
POT02
TI2CDLY
INC
POT03
TI2CDLY
INC
POT04
TI2CDLY
INC
POT05
TI2CDLY
INC
POT06
TI2CDLY
General Call Operation
INC
POTs 01-06
TI2CDLY
INC
POTs 01-06
TI2CDLY
INC
POTs 01-06
TI2CDLY
INC
POTs 01-06
TI2CDLY
INC
POTs 01-06
TI2CDLY
INC
POTs 01-06
TI2CDLY
TI2CDLY = Time from one I2C command completed to completing the next I2C command.
FIGURE 8-6:
Updates.
Example Comparison of “Normal Operation” vs. “General Call Operation” Wiper
2008-2013 Microchip Technology Inc.
DS22096B-page 63
MCP453X/455X/463X/465X
8.5
Implementing Log Steps with a
Linear Digital Potentiometer
In audio volume control applications, the use of
logarithmic steps is desirable since the human ear
hears in a logarithmic manner. The use of a linear
potentiometer can approximate a log potentiometer,
but with fewer steps. An 8-bit potentiometer can
achieve fourteen 3 dB log steps plus a 100% (0 dB)
and a mute setting.
Figure 8-7 shows a block diagram of one of the
MCP45X1 resistor networks being used to attenuate an
input signal. In this case, the attenuation will be ground
referenced. Terminal B can be connected to a common
mode voltage, but the voltages on the A, B and Wiper
terminals must not exceed the MCP45X1’s VDD/VSS
voltage limits.
EQUATION 8-1:
dB CALCULATIONS
(VOLTAGE)
V OUT
L = 20 log 10 -------------
VIN
dB
VOUT / VIN Ratio
-3
0.70795
-2
0.79433
-1
0.89125
EQUATION 8-2:
dB CALCULATIONS
(RESISTANCE) - CASE 1
Terminal B connected to Ground (see Figure 8-7)
R BW
L = 20 log 10 -----------
RAB
MCP45X1
EQUATION 8-3:
P0A
P0W
P0B
FIGURE 8-7:
Signal Attenuation Block
Diagram - Ground Referenced.
Equation 8-1 shows the equation to calculate voltage
dB gain ratios for the digital potentiometer, while
Equation 8-2 shows the equation to calculate
resistance dB gain ratios. These two equations assume
that the B terminal is connected to ground.
If terminal B is not directly resistively connected to
ground, then this terminal B to ground resistance
(RB2GND) must be included into the calculation.
Equation 8-3 shows this equation.
DS22096B-page 64
dB CALCULATIONS
(RESISTANCE) - CASE 2
Terminal B through RB2GND to Ground
RBW + R B2GND
L = 20 log 10 --------------------------------------
R AB
Table 8-1 shows the codes that can be used for 8-bit
digital potentiometers to implement the log attenuation.
The table shows the wiper codes for -3 dB, -2 dB and
-1 dB attenuation steps. This table also shows the
calculated attenuation based on the wiper code’s linear
step. Calculated attenuation values less than the
desired attenuation are shown with red text. At lower
wiper code values, the attenuation may skip a step; if
this occurs the next attenuation value is colored
magenta to highlight that a skip occurred. For example,
in the -3 dB column the -48 dB value is highlighted
since the -45 dB step could not be implemented (there
are no wiper codes between 2 and 1).
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
TABLE 8-1:
LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS
-3 dB Steps
# of
Steps
-2 dB Steps
Calculated
Calculated
Desired
Wiper
Desired
Wiper
Attenuation
Attenuation
Attenuation Code
Attenuation Code
(1)
(1)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Note 1:
0 dB
-3 dB
-6 dB
-9dB
-12 dB
-15 dB
-18 dB
-21 dB
-24 dB
-27 dB
-30 dB
-33 dB
-36 dB
-39 dB
-42 dB
-48 dB
Mute
256
181
128
91
64
46
32
23
16
11
8
6
4
3
2
1
0
0 dB
-3.011 dB
-6.021 dB
-8.984 dB
-12.041 dB
-14.910 dB
-18.062 dB
-20.930 dB
-24.082 dB
-27.337 dB
-30.103 dB
-32.602 dB
-36.124 dB
-38.622 dB
-42.144 dB
-48.165 dB
Mute
256
203
162
128
102
81
64
51
41
32
26
20
16
13
10
8
6
5
4
3
2
1
0
Calculated
Desired
Wiper
Attenuation
Attenuatio
Code
(1)
n
0 dB
256
0 dB
-1 dB
228 -1.006 dB
-2 dB
203 -2.015 dB
-3 dB
181 -3.011 dB
-4 dB
162 -3.975 dB
-5 dB
144 -4.998 dB
-6 dB
128 -6.021 dB
-7 dB
114 -7.027 dB
-8 dB
102 -7.993 dB
-9 dB
91 -8.984 dB
-10 dB
81 -9.995 dB
-11 dB
72 -11.018 dB
-12 dB
64 -12.041 dB
-13 dB
57 -13.047 dB
-14 dB
51 -14.013 dB
-15 dB
46 - 14.910 dB
-16 dB
41 -15.909 dB
-17 dB
36 -17.039 dB
-18 dB
32 -18.062 dB
-19 dB
29 -18.917 dB
-20 dB
26 -19.865 dB
-21 dB
23 - 20.930 dB
-22 dB
20 -22.144 dB
-23 dB
18 -23.059 dB
-24 dB
16 -24.082 dB
-25 dB
14 -25.242 dB
-26 dB
13 -25.886 dB
-27dB
11 -27.337 dB
-28 dB
10 -28.165 dB
-29 dB
9 -29.080 dB
-30 dB
8 -30.103 dB
-31 dB
7 -31.263 dB
-33 dB
6 -32.602 dB
-34 dB
5 -34.185 dB
-36 dB
4 -36.124 dB
-39 dB
3 -38.622 dB
-42 dB
2 -42.144 dB
-48 dB
1 -48.165 dB
Mute
0
Mute
Attenuation values do not include errors from Digital Potentiometer errors, such as Full Scale Error or Zero
Scale Error.
2008-2013 Microchip Technology Inc.
0 dB
-2 dB
-4 dB
-6 dB
-8 dB
-10 dB
-12 dB
-14 dB
-16 dB
-18 dB
-20 dB
-22 dB
-24 dB
-26 dB
-28 dB
-30 dB
-32 dB
-34 dB
-36 dB
-38 dB
-42 dB
-48 dB
Mute
-1 dB Steps
0 dB
-2.015 dB
-3.975 dB
-6.021 dB
-7.993 dB
-9.995 dB
-12.041 dB
-14.013 dB
-15.909 dB
-18.062 dB
-19.865 dB
-22.144 dB
-24.082 dB
-25.886 dB
-28.165 dB
-30.103 dB
-32.602 dB
-34.185 dB
-36.124 dB
-38.622 dB
-42.144 dB
-48.165 dB
Mute
DS22096B-page 65
MCP453X/455X/463X/465X
8.6
8.6.2
Design Considerations
In the design of a system with the MCP4XXX devices,
the following considerations should be taken into
account:
• Power Supply Considerations
• Layout Considerations
8.6.1
POWER SUPPLY
CONSIDERATIONS
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 8-8 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (VDD) as
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
VDD
LAYOUT CONSIDERATIONS
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP4XXX’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
boards utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the silicon
is capable of providing. Particularly harsh environments may require shielding of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
8.6.3
RESISTOR TEMPCO
Characterization curves of the resistor temperature
coefficient (Tempco) are shown in Figure 2-12,
Figure 2-25, Figure 2-38, and Figure 2-51.
These curves show that the resistor network is
designed to correct for the change in resistance as
temperature increases. This technique reduces the
end-to-end change in RAB resistance.
8.6.4
HIGH VOLTAGE TOLERANT PINS
High Voltage support (VIHH) on the Serial Interface pins
is for compatibility with the nonvolatile devices.
0.1 µF
VDD
W
B
VSS
FIGURE 8-8:
Connections.
DS22096B-page 66
SCL
PIC® Microcontroller
A
MCP453X/455X/
463X/465X
0.1 µF
SDA
VSS
Typical Microcontroller
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
9.0
DEVICE OPTIONS
Additional, custom devices are available. These
devices have weak pull-up resistors on the SDA and
SCL pins. This is useful for applications where the
wiper value is programmed during manufacture and not
modified by the system during normal operation.
Please contact your local sales office for current information and minimum volume requirements.
9.1
Custom Options
The custom device will have a “P” (for Pull-up) after the
resistance version in the Product Identification System.
These devices will not be available through Microchip’s
online Microchip Direct, nor Microchip’s Sample systems.
Example part number:
MCP4631-103PE/ST
2008-2013 Microchip Technology Inc.
DS22096B-page 67
MCP453X/455X/463X/465X
NOTES:
DS22096B-page 68
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
10.0
DEVELOPMENT SUPPORT
10.1
Development Tools
10.2
Technical Documentation
Several additional technical documents are available to
assist you in your design and development. These
technical documents include Application Notes,
Technical Briefs, and Design Guides. Table 10-2
shows some of these documents.
Several development tools are available to assist in
your design and evaluation of the MCP45XX/46XX
devices. The currently available tools are shown in
Table 10-1.
These boards may be purchased directly from the
Microchip web site at www.microchip.com.
TABLE 10-1:
DEVELOPMENT TOOLS
Board Name
Part #
Supported Devices
MCP46XXDM-PTPLS
MCP46XX
MCP4XXXDM-DB
MCP42XXX, MCP42XX, MCP46XX,
MCP4021, and MCP4011
MCP46XXEV Evaluation Board
MCP46XXEV
MCP4631, MCP4641, MCP4651,
MCP4661
TSSOP-20 and SSOP-20 Evaluation Board
TSSOP20EV
MCP4631, MCP4641, MCP4651,
MCP4661
8-pin SOIC/MSOP/TSSOP/DIP Evaluation Board
SOIC8EV
Any 8-pin device in DIP, SOIC,
MSOP, or TSSOP package
14-pin SOIC/MSOP/DIP Evaluation Board
SOIC14EV
Any 14-pin device in DIP, SOIC, or
MSOP package
MCP46XX PICTail Plus Daughter Board (2)
MCP4XXX Digital Potentiometer Daughter Board
(1)
Note 1: Requires the use of a PICDEM Demo Board (see User’s Guide for details) and the SOIC14EV board to
convert an MCP46XX device in TSSOP package to the DIP footprint.
2: Requires the use of the PIC24 Explorer 16 Demo Board (see User’s Guide for details)
TABLE 10-2:
TECHNICAL DOCUMENTATION
Application
Note Number
Title
Literature #
AN1316
Using Digital Potentiometers for Programmable Amplifier Gain
DS01316
AN1080
Understanding Digital Potentiometers Resistor Variations
DS01080
AN737
Using Digital Potentiometers to Design Low Pass Adjustable Filters
DS00737
AN692
Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect
DS00692
AN691
Optimizing the Digital Potentiometer in Precision Circuits
DS00691
AN219
Comparing Digital Potentiometers to Mechanical Potentiometers
DS00219
—
Digital Potentiometer Design Guide
DS22017
—
Signal Chain Design Guide
DS21825
2008-2013 Microchip Technology Inc.
DS22096B-page 69
MCP453X/455X/463X/465X
NOTES:
DS22096B-page 70
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
11.0
PACKAGING INFORMATION
11.1
Package Marking Information
8-Lead DFN (3x3)
XXXX
XYWW
NNN
Example:
Part Number
Code
Part Number
Code
MCP4531-502E/MF
DACA
MCP4532-502E/MF
DACE
MCP4531-103E/MF
DACB
MCP4532-103E/MF
DACF
MCP4531-104E/MF
DACD
MCP4532-104E/MF
DACH
MCP4531-503E/MF
DACC
MCP4532-503E/MF
DACG
MCP4551-502E/MF
DACT
MCP4552-502E/MF
DACX
MCP4551-103E/MF
DACU
MCP4552-103E/MF
DACY
MCP4551-104E/MF
DACW
MCP4552-104E/MF
DADA
MCP4551-503E/MF
DACV
MCP4552-503E/MF
DACZ
Part Number
Code
Part Number
Code
MCP4531-103E/MS
453113
MCP4532-103E/MS
453213
MCP4531-104E/MS
453114
MCP4532-104E/MS
453214
MCP4531-502E/MS
453152
MCP4532-502E/MS
453252
MCP4531-503E/MS
453153
MCP4532-503E/MS
453253
MCP4551-103E/MS
455113
MCP4552-103E/MS
455213
8-Lead MSOP
XXXXXX
YWWNNN
MCP4551-104E/MS
455114
MCP4552-104E/MS
455214
MCP4551-502E/MS
455152
MCP4552-502E/MS
455252
MCP4551-503E/MS
455153
MCP4552-503E/MS
455253
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DACA
1028
256
Example
453113
028256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2008-2013 Microchip Technology Inc.
DS22096B-page 71
MCP453X/455X/463X/465X
Package Marking Information (Continued)
10-Lead DFN (3x3)
XXXX
YYWW
NNN
Example:
Part Number
Code
Part Number
Code
MCP4632-502E/MF
AABA
MCP4652-502E/MF
AAKA
MCP4632-103E/MF
AACA
MCP4652-103E/MF
AALA
MCP4632-104E/MF
AAEA
MCP4652-104E/MF
AAPA
MCP4632-503E/MF
AADA
MCP4652-503E/MF
AAMA
AAFA
1028
256
10-Lead MSOP
XXXXXX
YWWNNN
Example
Part Number
Code
Part Number
Code
MCP4632-502E/UN
463252
MCP4652-502E/UN
465252
MCP4632-103E/UN
463213
MCP4652-103E/UN
465213
MCP4632-104E/UN
463214
MCP4652-104E/UN
465214
MCP4632-503E/UN
463253
MCP4652-503E/UN
465253
14-Lead TSSOP (MCP4631, MCP4651)
XXXXXXXX
Example
4631502E
1028
YYWW
NNN
16-Lead QFN (MCP4631, MCP4651)
XXXXX
XXXXXX
XXXXXX
YYWWNNN
DS22096B-page 72
463252
028256
256
Example
4631
502
e3
E/ML^^
028256
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2013 Microchip Technology Inc.
DS22096B-page 73
MCP453X/455X/463X/465X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22096B-page 74
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2013 Microchip Technology Inc.
DS22096B-page 75
MCP453X/455X/463X/465X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22096B-page 76
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2013 Microchip Technology Inc.
DS22096B-page 77
MCP453X/455X/463X/465X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22096B-page 78
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2013 Microchip Technology Inc.
DS22096B-page 79
MCP453X/455X/463X/465X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22096B-page 80
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2013 Microchip Technology Inc.
DS22096B-page 81
MCP453X/455X/463X/465X
UN
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22096B-page 82
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
UN
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2013 Microchip Technology Inc.
DS22096B-page 83
MCP453X/455X/463X/465X
10-Lead Plastic Micro Small Outline Package (UN) [MSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22096B-page 84
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2013 Microchip Technology Inc.
DS22096B-page 85
MCP453X/455X/463X/465X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22096B-page 86
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2013 Microchip Technology Inc.
DS22096B-page 87
MCP453X/455X/463X/465X
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DS22096B-page 88
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2008-2013 Microchip Technology Inc.
DS22096B-page 89
MCP453X/455X/463X/465X
NOTES:
DS22096B-page 90
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
APPENDIX A:
REVISION HISTORY
Revision B (February 2013)
The following is the list of modifications:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
Corrected MCP45x1 DFN package pinout.
Corrected Device Block Diagram.
Updated the Absolute Maximum Ratings †
with Total Power Dissipation values for each
package type.
Updated typical thermal values in Temperature
Characteristics table.
Corrected labeling in Figure 2-1, from
Section 2.0 “Typical Performance Curves”.
Also corrected Figure 2-4.
Appropriate 1.8V Graphs in Section 2.0 “Typical Performance Curves” now reference
Appendix B: “Characterization Data Analysis”.
Added new Figure 2-66.
Corrected values in Figure 5-1.
Added description of wiper value on POR/BOR
(Section 5.2 “Wiper”).
Added new section Section 8.5 “Implementing
Log
Steps
with
a
Linear
Digital
Potentiometer”.
Added information in the Development Tools
Section
(Section 10.0
“Development
support”).
Updated packaging section with package
available landing pattern diagrams.
Added Appendix B: “Characterization Data
Analysis”.
Updated the format of the Absolute Maximum
Ratings † page in Section 1.0 “Electrical
Characteristics”.
Clarified actions of the POR in Section 4.1.1
“Power-on Reset”.
Removed Note 3 from Table 10-1.
Revision A (November 2008)
• Original Release of this Document.
2008-2013 Microchip Technology Inc.
DS22096B-page 91
MCP453X/455X/463X/465X
NOTES:
DS22096B-page 92
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
CHARACTERIZATION
DATA ANALYSIS
Some designers may desire to understand the device
operational characteristics outside of the specified
operating conditions of the device.
Applications where the knowledge of the resistor
network characteristics could be useful include battery
powered devices and applications that experience
brown-out conditions.
In battery applications, the application voltage decays
over time until new batteries are installed. As the
voltage decays, the system will continue to operate. At
some voltage level, the application will be below its
specified operating voltage range. This is dependent
on the individual components used in the design. It is
still useful to understand the device characteristics to
expect when this low-voltage range is encountered.
Unlike a microcontroller, which can use an external
supervisor device to force the controller into the Reset
state, a digital potentiometer’s resistance characteristic
is not specified. But understanding the operational
characteristics can be important in the design of the
application’s circuit for this low-voltage condition.
Other application system scenarios, where understanding the low-voltage characteristics of the resistor
network could be important, is for system brown-out
conditions.
For the MCP453X/455X/463X/465X devices, the analog operation is specified at a minimum of 2.7V. Device
testing has Terminal A connected to the device VDD (for
potentiometer configuration only) and Terminal B
connected to VSS.
B.1
Low-Voltage Operation
This appendix gives an overview of CMOS
semiconductor characteristics at lower voltages. This is
important so that the 1.8V resistor network
characterization graphs of the MCP453X/455X/463X/
465X devices can be better understood.
For this discussion, we will use the 5 k device data.
This data was chosen since the variations of wiper
resistance has much greater implications for devices
with smaller RAB resistances.
Figure B-1 shows the worst case RBW error from the
average RBW as a percentage, while Figure B-2 shows
the RBW resistance versus wiper code graph. Nonlinear
behavior occurs at approximately wiper code 160. This
is better shown in Figure B-2, where the RBW
resistance changes from a linear slope. This change is
due to the change in the wiper resistance.
2.00%
1.00%
0.00%
-1.00%
Error %
APPENDIX B:
-2.00%
-3.00%
-4.00%
-40C
+25C
+85C
+125C
-5.00%
-6.00%
-7.00%
0
32
64
96
128
160
192
224
256
Wiper Code
FIGURE B-1:
1.8V Worst Case RBW Error
from Average RBW (RBW0-RBW3) vs. Wiper Code
and Temperature (VDD = 1.8V, IW = 190 µA).
7000
Resistance ()
6000
5000
4000
3000
-40C
+25C
+85C
+125C
2000
1000
0
0
32
64
96
128
160
Wiper Code
192
224
256
FIGURE B-2:
RBW vs. Wiper Code And
Temperature (VDD = 1.8V, IW = 190 µA).
2008-2013 Microchip Technology Inc.
DS22096B-page 93
MCP453X/455X/463X/465X
Figure B-3 and Figure B-4 show the wiper resistance
for VDD voltages of 5.5, 3.0, 1.8 volts. These graphs
show that as the resistor ladder wiper node voltage
(VWCn) approaches the VDD/2 voltage, the wiper
resistance increases. These graphs also show the
different resistance characteristics of the NMOS and
PMOS transistors that make up the wiper switch. This
is demonstrated by the wiper code resistance curve,
which does not mirror itself around the mid-scale code
(wiper code = 128).
So why are the RW graphs showing the maximum
resistance at about mid-scale (wiper code = 128) and
the RBW graphs showing the issue at code 160?
This requires understanding low-voltage transistor
characteristics as well as how the data was measured.
The method in which the data was collected is
important to understand. Figure B-5 shows the
technique that was used to measure the RBW and RW
resistance. In this technique, Terminal A is floating and
Terminal B is connected to ground. A fixed current is
then forced into the wiper (IW), and the corresponding
wiper voltage (VW) is measured. Forcing a known
current through RBW (IW) and then measuring the
voltage difference between the wiper (VW) and
Terminal A (VA), the wiper resistance (RW) can be
calculated, as shown in Figure B-5. Changes in IW current will change the wiper voltage (VW). This may effect
the device’s wiper resistance (RW).
floating
VA
A
220
200
-40C @ 3.0V
+25C @ 3.0V
+85C @ 3.0V
+125C @ 3.0V
-40C @5.5V
+25C @ 5.5V
+85C @ 5.5V
+125C @ 5.5V
Resistance ()
180
IW
160
B
140
120
VB
RBW = VW/IW
RW = (VW-VA)/IW
100
80
FIGURE B-5:
60
40
20
0
64
128
192
256
Wiper Code
FIGURE B-3:
Wiper Resistance (RW) vs.
Wiper Code and Temperature
(VDD = 5.5V, IW = 900 UA; VDD = 3.0V,
IW = 480 µA).
+25C @ 1.8V
+85C @ 1.8V
1520
+125C @ 1.8V
1020
520
20
0
64
128
192
256
Wiper Code
FIGURE B-4:
Wiper Resistance (RW) vs.
Wiper Code and Temperature
(VDD = 1.8V, IW = 260 µA).
DS22096B-page 94
RBW and RW Measurement.
Figure B-6 shows a block diagram of the resistor
network where the RAB resistor is a series of 256 RS
resistors. These resistors are polysilicon devices. Each
wiper switch is an analog switch made up of an NMOS
and PMOS transistor. A more detailed figure of the
wiper switch is shown in Figure B-7. The wiper
resistance is influenced by the voltage on the wiper
switches’ nodes (VG, VW and VWCn). Temperature also
influences the characteristics of the wiper switch, as
shown in Figure B-4.
The NMOS transistor and PMOS transistor have
different characteristics. These characteristics, as well
as the wiper switch node voltages, determine the RW
resistance at each wiper code. The variation of each
wiper switch’s characteristics in the resistor network is
greater then the variation of the RS resistors.
-40C @ 1.8V
2020
Resistance ()
VW
W
The voltage on the resistor network node (VWCn) is
dependent upon the wiper code selected and the
voltages applied to VA, VB and VW. The wiper switch VG
voltage to VW or VWCn voltage determines how strongly
the transistor is turned on. When the transistor is
weakly turned on the wiper resistance, RW will be high.
When the transistor is strongly turned on, the wiper
resistance (RW) will be in the typical range.
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
So, looking at the wiper voltage (VW) for the
3.0V and 1.8V data gives the graphs in Figure B-8 and
Figure B-9. In the 1.8V graph, as the VW approaches
0.8V, the voltage increases nonlinearly. Since V = I * R,
and the current (IW) is constant, it means that the
device resistance increased nonlinearly at around
wiper code 160.
A
VA
Nn
RS
RW (1)
Nn-1
DVG
RW (1)
RS
1.2
RS
VWC(n-2)
RAB
Nn-3
NMOS
PMOS
RW (1)
VW
W
Wiper Voltage (V)
1.0
Nn-2
0.8
0.6
0.4
-40C
+25C
+85C
+125C
0.2
0.0
N1
RW
RW
(1)
N0
B
0
32
64
96 128 160
Wiper Code
192
224
256
FIGURE B-8:
Wiper Voltage (VW) vs.
Wiper Code (VDD = 3.0V, IW = 190 µA).
VB
1.4
1.2
Note 1: The wiper resistance is dependent on
several factors including, wiper code,
device VDD, Terminal voltages (on A, B
and W), and temperature.
FIGURE B-6:
Diagram.
Resistor Network Block
Wiper Voltage (V)
RS
(1)
1.0
0.8
0.6
-40C
+25C
+85C
+125C
0.4
0.2
The characteristics of the wiper are determined by the
characteristics of the wiper switch at each of the
resistor networks tap points. Figure B-7 shows an
example of a wiper switch. As the device operational
voltage becomes lower, the characteristics of the wiper
switch change due to a lower voltage on the VG signal.
0.0
0
32
64
96
128 160
Wiper Code
192
224
256
FIGURE B-9:
Wiper Voltage (VW) vs.
Wiper Code (VDD = 1.8V, IW = 190 µA).
Figure B-7 shows an implementation of a wiper switch.
When the transistor is turned off, the switch resistance
is in the Giga s. When the transistor is turned on, the
switch resistance is dependent on the VG, VW and
VWCn voltages. This resistance is referred to as RW.
RW (1)
VG (VDD/VSS)
“gate”
NMOS
NWC
VWCn
PMOS
Wiper
VW
“gate”
Note 1: Wiper Resistance (RW) depends on the
voltages at the wiper switch nodes
(VG, VW and VWCn).
FIGURE B-7:
Wiper Switch.
2008-2013 Microchip Technology Inc.
DS22096B-page 95
MCP453X/455X/463X/465X
RW
RNMOS
140
RPMOS
RW
120
5.00E+09
100
4.00E+09
80
NMOS
PMOS Theshold
Theshold
3.00E+09
2.00E+09
60
40
1.00E+09
Wiper Resistance ()
6.00E+09
20
0.00E+00
0
0.0
0.6
1.2
1.8
VIN Voltage
2.4
3.0
FIGURE B-12:
NMOS and PMOS
Transistor Resistance (RNMOS, RPMOS) and
Wiper Resistance (RW) VS. VIN
(VDD = 1.8V).
VG (VDD/VSS)
“gate”
300
NMOS
250
VOUT
PMOS
Resistance ()
VIN
“gate”
FIGURE B-10:
160
7.00E+09
NMOS and PMOS Resistance
()
Using the simulation models of the NMOS and PMOS
devices for the MCP4XXX analog switch (Figure B-10),
we plot the device resistance when the devices are
turned on. Figure B-11 and Figure B-12 show the
resistances of the NMOS and PMOS devices as the
VIN voltage is increased. The wiper resistance (RW) is
simply the parallel resistance on the NMOS and PMOS
devices (RW = RNMOS || RPMOS). Below the threshold
voltage for the NMOS and PMOS devices, the
resistance becomes very large (Giga s). In the
transistor’s active region, the resistance is much lower.
For these graphs, the resistances are on different
scales. Figure B-13 and Figure B-14 only plot the
NMOS and PMOS device resistance for their active
region and the resulting wiper resistance. For these
graphs, all resistances are on the same scale.
Analog Switch.
200
RNMOS
RPMOS
150
100
RW
50
3.00E+10
2500
RNMOS
0
2.50E+10
2000
RPMOS
2.00E+10
1500
1.50E+10
1000
1.00E+10
NMOS
500
Theshold
PMOS
Theshold
5.00E+09
0.00E+00
0.0
Wiper Resistance ()
NMOS and PMOS Resistance
()
RW
0.3
0.6
0.9
1.2
VIN Voltage
1.5
1.2
1.8
VIN Voltage
2.4
3.0
FIGURE B-13:
NMOS and PMOS
Transistor Resistance (RNMOS, RPMOS) and
Wiper Resistance (RW) VS. VIN
(VDD = 3.0V).
0
0.0
0.6
5000
1.8
4500
Resistance ()
4000
FIGURE B-11:
NMOS and PMOS
Transistor Resistance (RNMOS, RPMOS) and
Wiper Resistance (RW) VS. VIN
(VDD = 3.0V).
3500
3000
RNMOS
2500
RPMOS
2000
RW
1500
1000
500
0
0.0
0.3
0.6
0.9
1.2
VIN Voltage
1.5
1.8
FIGURE B-14:
NMOS and PMOS
Transistor Resistance (RNMOS, RPMOS) and
Wiper Resistance (RW) VS. VIN
(VDD = 1.8V).
DS22096B-page 96
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
B.2
Optimizing Circuit Design for LowVoltage Characteristics
R1
The low-voltage nonlinear characteristics can be
minimized by application design. The section will show
two application circuits that can be used to control a
programmable reference voltage (VOUT).
A
In example implementation #1 (Figure B-15), we
window the digital potentiometer using resistors R1 and
R2. When the wiper code is at full scale, the VOUT
voltage will be 0.6 * VDD, and when the wiper code is
at zero scale, the VOUT voltage will be 0.5 * VDD.
Remember that the digital potentiometers RAB variation
must be included. Table B-1 shows that the VOUT voltage can be selected to be between 0.455 * VDD and
0.727 * VDD, which includes the desired range. With
respect to the voltages on the resistor network node, at
1.8V the VA voltage would range from 1.29V to 1.31V,
while the VB voltage would range from 0.82V to 0.86V.
These voltages cause the wiper resistance to be in the
nonlinear region (see Figure B-12). In Potentiometer
mode, the variation of the wiper resistance is typically
not an issue, as shown by the INL/DNL graph
(Figure 2-7).
VW
W
Minimizing the low-voltage nonlinear characteristics is
done by keeping the voltages on the wiper switch
nodes at a voltage where either the NMOS or PMOS
transistor is turned on.
An example of this is if we are using a digital potentiometer for a voltage reference (VOUT). Let’s say that we
want VOUT to range from 0.5 * VDD to 0.6 * VDD.
VA
B
VOUT
VB
R2
FIGURE B-15:
TABLE B-1:
Example Implementation #1.
EXAMPLE #1 VOLTAGE
CALCULATIONS
Variation
Min
Typ
Max
R1
12,000
12,000
12,000
R2
20,000
20,000
20,000
RAB
8,000
10,000
12,000
VOUT (@ FS) 0.714 VDD
VOUT (@ ZS) 0.476 VDD
0.70 VDD
0.727 VDD
0.50 VDD
0.455 VDD
VA
0.714 VDD
0.70 VDD
0.727 VDD
VB
0.476 VDD
0.50 VDD
0.455 VDD
Legend: FS – Full Scale, ZS – Zero Scale
In example implementation #2 (Figure B-16), we use
the digital potentiometer in Rheostat mode. The resistor ladder uses resistors R1 and R2 with RBW at the
bottom of the ladder. When the wiper code is at full
scale, the VOUT voltage will be 0.6 * VDD, and when
the wiper code is at full scale, the VOUT voltage will be
0.5 * VDD. Remember that the digital potentiometers
RAB variation must be included. Table B-2 shows that
the VOUT voltage can be selected to be between
0.50 * VDD and 0.687 * VDD, which includes the desired
range. With respect to the voltages on the resistor network node, at 1.8V the VW voltage would range from
0.29V to 0.38V. These voltages cause the wiper
resistance to be in the linear region (see Figure B-12).
2008-2013 Microchip Technology Inc.
DS22096B-page 97
MCP453X/455X/463X/465X
R1
VOUT
R2
A VA
W
B
FIGURE B-16:
TABLE B-2:
VW
VB
Example Implementation #2.
EXAMPLE #2 VOLTAGE
CALCULATIONS
Variation
Min
Typ
Max
R1
10,000
10,000
10,000
R2
10,000
10,000
10,000
RBW (max)
8,000
10,000
12,000
VOUT (@ FS) 0.667 VDD
VOUT(@ ZS) 0.50 VDD
0.643 VDD
0.687 VDD
0.50 VDD
0.50 VDD
VW (@ FS)
0.333 VDD
0.286 VDD
0.375 VDD
VW (@ ZS)
VSS
VSS
VSS
Legend: FS – Full Scale, ZS – Zero Scale
DS22096B-page 98
2008-2013 Microchip Technology Inc.
MCP453X/455X/463X/465X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
XXX
X
/XX
Resistance Temperature Package
Version
Range
Device:
MCP4531:
MCP4531T:
MCP4532:
MCP4532T:
MCP4551:
MCP4551T:
MCP4552:
MCP4552T:
MCP4631:
MCP4631T:
MCP4632:
MCP4632T:
MCP4651:
MCP4651T:
MCP4652:
MCP4652T:
Resistance Version:
Single Nonvolatile 7-bit Potentiometer
Single Nonvolatile 7-bit Potentiometer
(Tape and Reel)
Single Nonvolatile 7-bit Rheostat
Single Nonvolatile 7-bit Rheostat
(Tape and Reel)
Single Nonvolatile 8-bit Potentiometer
Single Nonvolatile 8-bit Potentiometer
(Tape and Reel)
Single Nonvolatile 8-bit Rheostat
Single Nonvolatile 8-bit Rheostat
(Tape and Reel)
Dual Nonvolatile 7-bit Potentiometer
Dual Nonvolatile 7-bit Potentiometer
(Tape and Reel)
Dual Nonvolatile 7-bit Rheostat
Dual Nonvolatile 7-bit Rheostat
(Tape and Reel)
Dual Nonvolatile 8-bit Potentiometer
Dual Nonvolatile 8-bit Potentiometer
(Tape and Reel)
Dual Nonvolatile8-bit Rheostat
Dual Nonvolatile 8-bit Rheostat
(Tape and Reel)
502 = 5 k
103 = 10 k
503 = 50 k
104 = 100 k
Temperature Range:
E
= -40°C to +125°C
Package:
MF
ML
MS
ST
UN
=
=
=
=
=
Plastic Dual Flat No-lead (3x3 DFN), 8/10-lead
Plastic Quad Flat No-lead (QFN), 16-lead
Plastic Micro Small Outline (MSOP), 8-lead
Plastic Thin Shrink Small Outline (TSSOP), 14-lead
Plastic Micro Small Outline (MSOP), 10-lead
2008-2013 Microchip Technology Inc.
Examples:
a)
MCP4531-502E/XX:
b)
MCP4531-103E/XX:
c)
MCP4531-503E/XX:
d)
MCP4531-104E/XX:
e)
MCP4531T-104E/XX:
5 k 8LD Device
10 k, 8-LD Device
50 k, 8LD Device
100 k, 8LD Device
T/R, 100 k, 8LD Device
a)
b)
c)
d)
e)
MCP4532-502E/XX:
MCP4532-103E/XX:
MCP4532-503E/XX:
MCP4532-104E/XX:
MCP4532T-104E/XX:
5 k 8LD Device
10 k, 8-LD Device
50 k, 8LD Device
100 k, 8LD Device
T/R, 100 k, 8LD Device
a)
b)
c)
d)
e)
MCP4551-502E/XX:
MCP4551-103E/XX:
MCP4551-503E/XX:
MCP4551-104E/XX:
MCP4551T-104E/XX:
5 k 8LD Device
10 k, 8-LD Device
50 k, 8LD Device
100 k, 8LD Device
T/R, 100 k, 8LD Device
a)
b)
c)
d)
e)
MCP4552-502E/XX:
MCP4552-103E/XX:
MCP4552-503E/XX:
MCP4552-104E/XX:
MCP4552T-104E/XX:
5 k 8LD Device
10 k, 8-LD Device
50 k, 8LD Device
100 k, 8LD Device
T/R, 100 k, 8LD Device
a)
b)
c)
d)
e)
MCP4631-502E/XX:
MCP4631-103E/XX:
MCP4631-503E/XX:
MCP4631-104E/XX:
MCP4631T-104E/XX:
5 k 8LD Device
10 k, 8-LD Device
50 k, 8LD Device
100 k, 8LD Device
T/R, 100 k, 8LD Device
a)
b)
c)
d)
e)
MCP4632-502E/XX:
MCP4632-103E/XX:
MCP4632-503E/XX:
MCP4632-104E/XX:
MCP4632T-104E/XX:
5 k 8LD Device
10 k, 8-LD Device
50 k, 8LD Device
100 k, 8LD Device
T/R, 100 k, 8LD Device
a)
b)
c)
d)
e)
MCP4651-502E/XX:
MCP4651-103E/XX:
MCP4651-503E/XX:
MCP4651-104E/XX:
MCP4651T-104E/XX:
5 k 8LD Device
10 k, 8-LD Device
50 k, 8LD Device
100 k, 8LD Device
T/R, 100 k, 8LD Device
a)
b)
c)
d)
e)
XX
MCP4652-502E/XX: 5 k 8LD Device
MCP4652-103E/XX: 10 k, 8-LD Device
MCP4652-503E/XX: 50 k, 8LD Device
MCP4652-104E/XX: 100 k, 8LD Device
MCP4652T-104E/XX: T/R, 100 k, 8LD Device
= MF for 8/10-lead 3x3 DFN
= ML for 16-lead QFN
= MS for 8-lead MSOP
= ST for 14-lead TSSOP
= UN for 10-lead MSOP
DS22096B-page 99
MCP453X/455X/463X/465X
NOTES:
DS22096B-page 100
2008-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2008-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-023-8
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2008-2013 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS22096B-page 101
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China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS22096B-page 102
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
11/29/12
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