NTD78N03R Power MOSFET 25 V, 85 A, Single N−Channel, DPAK Features • Low RDS(on) to Minimize Conduction Losses • Optimized Gate Charge to Minimize Switching Losses • Pb−Free Packages are Available http://onsemi.com Applications RDS(on) TYP V(BR)DSS • VCORE Applications • DC−DC Converters • Optimized for Low Side Switching ID MAX 5.0 @ 11.5 V 25 V 85 A 7.5 @ 4.5 V D MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 25 V Gate−to−Source Voltage VGS "20 V ID 14.7 A Continuous Drain Current (RqJA) (Note 1) TA = 25°C Power Dissipation (RqJA) (Note 1) TA = 25°C Continuous Drain Current (RqJA) (Note 2) TA = 25°C S 11.4 PD 2.3 4 W 4 4 TA = 85°C A 11.3 1 2 8.8 TA = 25°C PD 1.4 W Continuous Drain Current (RqJC) TC = 25°C ID 85 A Power Dissipation (RqJC) TC = 25°C PD 76.9 W IDM 98 A IDmaxPkg 32 A TJ, Tstg −55 to 175 °C IS 77 A Drain to Source dV/dt dV/dt 8.0 V/ns Single Pulse Drain−to−Source Avalanche Energy (VDD = 24 V, VGS = 10 V, L = 5.0 mH, IL(pk) = 5.5 A, RG = 25 W) EAS 75 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Pulsed Drain Current Current Limited by Package TC = 85°C tp = 10 ms TA = 25°C Operating Junction and Storage Temperature Source Current (Body Diode) 66 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. 1 3 CASE 369C DPAK (Bend Lead) STYLE 2 1 2 3 CASE 369D DPAK (Straight Lead) STYLE 2 2 3 CASE 369AC 3 IPAK (Straight Lead) MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain YWW 78 N03RG Steady State ID YWW 78 N03RG Power Dissipation (RqJA) (Note 2) TA = 85°C N−Channel G 1 Gate 2 Drain 3 Source 1 Gate 3 Source 2 Drain Y = Year WW = Work Week 78N03R= Device Code G = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 4 1 Publication Order Number: NTD78N03R/D NTD78N03R THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction−to−Case (Drain) Parameter RqJC 1.95 °C/W Junction−to−Ambient − Steady State (Note 3) RqJA 65 Junction−to−Ambient − Steady State (Note 4) RqJA 110 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 25 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS V 10 VGS = 0 V, VDS = 20 V mV/°C TJ = 25°C 1.5 TJ = 125°C 10 IGSS VDS = 0 V, VGS = "20 V VGS(TH) VGS = VDS, ID = 250 mA mA "100 nA 3.0 V ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance VGS(TH)/TJ RDS(on) gFS 1.0 1.7 −5.3 mV/°C VGS = 10V to 11.5 V ID = 30 A 5.0 5.8 ID = 15 A 4.9 5.7 VGS = 4.5 V ID = 30 A 7.5 9.0 ID = 15 A 7.2 8.5 VDS = 15 V, ID = 10 A mW 23 S 1794 pF CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss VGS = 0 V, f = 1.0 MHz, VDS = 12 V 882 373 Total Gate Charge QG(TOT) 19.4 Threshold Gate Charge QG(TH) 0.8 Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 12.4 td(on) 11 VGS = 4.5 V, VDS = 20 V, ID = 20 A 24 nC 2.9 SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(off) VGS = 4.5 V, VDS = 20 V, ID = 20 A, RG = 2.5 W tf ns 75 18 17 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time tRR Charge Time ta Discharge Time tb Reverse Recovery Time 3. 4. 5. 6. VGS = 0 V, IS = 30 A TJ = 25°C 0.8 38 VGS = 0 V, dIs/dt = 100 A/ms, IS = 20 A QRR http://onsemi.com 2 V ns 16.5 22 31 Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. Surface−mounted on FR4 board using the minimum recommended pad size. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. Switching characteristics are independent of operating junction temperatures. 1.0 nC NTD78N03R ID, DRAIN CURRENT (AMPS) VGS = 4 V TJ = 25°C 100 6V 4.5 V 80 3.5 V 60 40 3V 20 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (mΩ) 120 10 V 2.6 V 2.4 V 0 1 4 3 2 5 6 8 7 9 10 40 7.75 6.50 5.25 5 4 7 6 8 9 10 20 TJ = −55°C 1 3 2 4 5 6 8 7 0.01 TJ = 25°C 0.008 VGS = 4.5 V 0.006 VGS = 10 V 0.004 0.002 10 15 20 25 30 VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 2 100000 VGS = 0 V ID = 30 A VGS = 10 V to 11.5V IDSS, LEAKAGE (nA) TJ = 175°C 1.6 10000 1.4 1.2 1 1000 TJ = 100°C 0.8 0.6 −50 TJ = 25°C TJ = 125°C Figure 2. Transfer Characteristics 9.00 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 60 Figure 1. On−Region Characteristics 10.25 1.8 80 VGS, GATE−TO−SOURCE VOLTAGE (V) ID = 30 A TJ = 25°C 3 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 11.50 4.00 VDS ≥ 10 V 0 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω) ID, DRAIN CURRENT (AMPS) 120 −25 0 25 50 75 100 125 150 175 100 2 4 6 8 10 12 14 16 18 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 20 VDS = 0 V VGS = 0 V TJ = 25°C C, CAPACITANCE (pF) 3000 C iss 2500 2000 Ciss Crss 1500 1000 Coss 500 0 20 Crss 15 10 5 VGS 0 VDS 5 10 15 20 25 5 4 VGS Q2 Q1 3 12 8 2 1 0 ID = 20 A TJ = 25°C 0 4 8 12 16 4 0 20 Qg, TOTAL GATE CHARGE (nC) Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge Figure 7. Capacitance Variation 40 1000 VDS = 15 V ID = 20 A VGS = 4.5 V IS, SOURCE CURRENT (AMPS) t, TIME (ns) 16 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) 100 tr tf td(off) 10 20 QT VDS, DRAIN−TO−SOURCE VOLTAGE (V) 3500 VGS, GATE−TO−SOURCE VOLTAGE (V) NTD78N03R td(on) 1 10 RG, GATE RESISTANCE (OHMS) 35 30 25 20 15 10 5 0 0.3 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance VGS = 0 V TJ = 25°C 0.6 0.9 VSD, SOURCE−TO−DRAIN VOLTAGE (V) 1.2 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 4 NTD78N03R ORDERING INFORMATION Order Number NTD78N03R Package DPAK NTD78N03RG DPAK (Pb−Free) NTD78N03RT4 DPAK NTD78N03RT4G Shipping† DPAK (Pb−Free) NTD78N03R−1 DPAK Straight Lead NTD78N03R−1G DPAK Straight Lead (Pb−Free) NTD78N03R−35 DPAK Straight Lead (3.5 " 0.15 mm) NTD78N03R−35G DPAK Straight Lead (3.5 " 0.15 mm) (Pb−Free) 75 Units/Rail 2500 Tape & Reel 75 Units/Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NTD78N03R PACKAGE DIMENSIONS DPAK CASE 369C−01 ISSUE O C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE −T− E R 4 Z A S 1 2 DIM A B C D E F G H J K L R S U V Z 3 U K F J L H D G 2 PL 0.13 (0.005) M T SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− NTD78N03R PACKAGE DIMENSIONS DPAK CASE 369D−01 ISSUE B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. C B E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G H M INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 3 PL 0.13 (0.005) DIM A B C D E F G H J K R S V Z T http://onsemi.com 7 MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− NTD78N03R PACKAGE DIMENSIONS 3 IPAK, STRAIGHT LEAD CASE 369AC−01 ISSUE O B V C E R DIM A B C D E F G H J K R V W A SEATING PLANE K W F J G D NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. H 3 PL 0.13 (0.005) W INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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