TI SN74ALVCH16373DGGR

SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
FEATURES
•
•
•
•
•
•
•
Member of the Texas Instruments Widebus™
Family
Operates From 1.65 V to 3.6 V
Max tpd of 3.6 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
XXXX
DESCRIPTION/ORDERING INFORMATION
This 16-bit transparent D-type latch is designed for
1.65-V to 3.6-V VCC operation.
The SN74ALVCH16373 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. This device can
be used as two 8-bit latches or one 16-bit latch.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is taken
low, the Q outputs are latched at the levels set up at
the D inputs.
SCES020I – JULY 1995 – REVISED NOVEMBER 2005
DGG OR DL PACKAGE
(TOP VIEW)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
A buffered output-enable (OE) input can be used to
place the eight outputs in either a normal logic state
(high or low logic levels) or the high-impedance state.
In the high-impedance state, the outputs neither
load nor drive the buslines significantly. The
high-impedance state and the increased drive provide
the capability to drive bus lines without need for
interface or pullup components. OE does not affect
internal operations of the latch. Old data can be
retained or new data can be entered while the
outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2005, Texas Instruments Incorporated
SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES020I – JULY 1995 – REVISED NOVEMBER 2005
ORDERING INFORMATION
PACKAGE (1)
TA
FBGA – GRD
FBGA – ZRD (Pb-free)
ORDERABLE PART NUMBER
SN74ALVCH16373GRDR
Tape and reel
SSOP – DL
VH373
SN74ALVCH16373ZRDR
Tube
TOP-SIDE MARKING
SN74ALVCH16373DL
SN74ALVCH16373DLR
Tape and reel
ALVCH16373
74ALVCH16373DLG4
–40°C to 85°C
74ALVCH16373DLRG4
SN74ALVCH16373DGGR
TSSOP – DGG
Tape and reel
74ALVCH16373DGGE4
ALVCH16373
74ALVCH16373DGGRG4
VFBGA – GQL
VFBGA – ZQL (Pb-free)
(1)
SN74ALVCH16373KR
Tape and reel
VH373
74ALVCH16373ZQLR
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
GQL OR ZQL PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS (1)
(56-Ball GQL/ZQL Package)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
1LE
B
1Q2
1Q1
GND
GND
1D1
1D2
C
1Q4
1Q3
VCC
VCC
1D3
1D4
D
1Q6
1Q5
GND
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
GND
2D4
2D3
H
2Q5
2Q6
VCC
VCC
2D6
2D5
J
2Q7
2Q8
GND
GND
2D8
2D7
K
2OE
NC
NC
NC
NC
2LE
abc
(1)
abc
NC – No internal connection
GRD OR ZRD PACKAGE
(TOP VIEW)
1
2
3
4
5
6
TERMINAL ASSIGNMENTS (1)
(54-Ball GRD/ZRD Package)
1
2
3
4
5
6
A
1Q1
NC
1OE
1LE
NC
1D1
B
1Q3
1Q2
NC
NC
1D2
1D3
C
1Q5
1Q4
VCC
VCC
1D4
1D5
D
1Q7
1Q6
GND
GND
1D6
1D7
D
E
2Q1
1Q8
GND
GND
1D8
2D1
E
F
2Q3
2Q2
GND
GND
2D2
2D3
G
2Q5
2Q4
VCC
VCC
2D4
2D5
H
2Q7
2Q6
NC
NC
2D6
2D7
J
2Q8
NC
2OE
2LE
NC
2D8
A
B
C
F
G
H
J
(1)
NC – No internal connection
xxxxx
2
SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES020I – JULY 1995 – REVISED NOVEMBER 2005
FUNCTION TABLE
(EACH 8-BIT SECTION)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE
1LE
1D1
1
2OE
48
2LE
C1
47
1D
2
1Q1
24
25
C1
2D1
36
To Seven Other Channels
13
1D
2Q1
To Seven Other Channels
Pin numbers shown are for the DGG and DL packages.
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
range (2) (3)
VI
Input voltage
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current
MIN
MAX
–0.5
4.6
V
–0.5
VCC + 0.5
V
–0.5
VCC + 0.5
Continuous current through each VCC or GND
θJA
Tstg
(1)
(2)
(3)
(4)
Package thermal impedance (4)
Storage temperature range
V
-50
mA
-50
mA
±50
mA
±100
mA
DGG package
70
DL package
63
GQL/ZQL package
42
GRD/ZRD package
36
–65
UNIT
150
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
3
SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES020I – JULY 1995 – REVISED NOVEMBER 2005
Recommended Operating Conditions (1)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 1.65 V to 1.95 V
MIN
MAX
1.65
3.6
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
4
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
V
0.35 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
0.8
V
0
VCC
V
0
VCC
V
VCC = 1.65 V
–4
VCC = 2.3 V
–12
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 1.65 V
4
VCC = 2.3 V
12
VCC = 2.7 V
12
VCC = 3 V
24
–40
mA
mA
10
ns/V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES020I – JULY 1995 – REVISED NOVEMBER 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
1.65 V to 3.6 V
1.65 V
IOH = –6 mA
2.3 V
2
2.3 V
1.7
2.7 V
2.2
IOH = –12 mA
II(hold)
V
3V
2.4
3V
2
IOL = 100 µA
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 6 mA
2.3 V
0.4
2.3 V
0.7
2.7 V
0.4
3V
0.55
IOL = 24 mA
UNIT
1.2
IOH = –24 mA
IOL = 12 mA
II
MAX
VCC – 0.2
IOH = –4 mA
VOH
VOL
MIN TYP (1)
VCC
V
±5
VI = VCC or GND
3.6 V
VI = 0.58 V
1.65 V
25
VI = 1.07 V
1.65 V
–25
VI = 0.7 V
2.3 V
45
VI = 1.7 V
2.3 V
–45
VI = 0.8 V
3V
75
VI = 2 V
3V
–75
µA
µA
VI = 0 to 3.6 V (2)
3.6 V
±500
IOZ
VO = VCC or GND
3.6 V
±10
µA
ICC
VI = VCC or GND
IO = 0
3.6 V
40
µA
∆ICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
3 V to 3.6 V
750
µA
Ci
Co
(1)
(2)
Control inputs
Data inputs
Outputs
VI = VCC or GND
3.3 V
VO = VCC or GND
3.3 V
3
pF
6
7
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
MIN
Pulse duration, LE high or low
(1)
tsu
Setup time, data before LE↓
(1)
th
Hold time, data after LE↓
(1)
tw
(1)
MAX
VCC = 2.5 V
± 0.2 V
MIN
3.3
MAX
VCC = 2.7 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
3.3
3.3
ns
1
1
1.1
ns
1.5
1.7
1.4
ns
This information was not available at the time of publication.
5
SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES020I – JULY 1995 – REVISED NOVEMBER 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
PARAMETER
D
tpd
LE
ten
OE
tdis
(1)
VCC = 1.8 V
TO
(OUTPUT)
OE
TYP
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
MIN
MAX
(1)
1
(1)
1
Q
(1)
Q
(1)
Q
MIN
VCC = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
4.5
4.3
1.1
3.6
4.9
4.6
1
3.9
1
6
5.7
1
4.7
ns
1.2
5.1
4.5
1.4
4.1
ns
ns
This information was not available at the time of publication.
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
(1)
6
Power dissipation
capacitance
Outputs enabled
Outputs disabled
TEST CONDITIONS
CL = 50 pF,
This information was not available at the time of publication.
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
(1)
19
22
(1)
4
5
UNIT
pF
SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES020I – JULY 1995 – REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
1.8 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
tw
VI
Timing
Input
VM
VM
VM
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VM
VM
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VLOAD/2
VM
tPZH
VOH
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPHL
VM
VI
VM
tPZL
VI
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VI
Data
Input
VM
0V
0V
tsu
Output
VI
VM
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VOH
VM
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74ALVCH16373DGGRG4
ACTIVE
TSSOP
DGG
48
74ALVCH16373DLG4
ACTIVE
SSOP
DL
48
74ALVCH16373DLRG4
ACTIVE
SSOP
DL
74ALVCH16373GRDR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
74ALVCH16373GRE4
ACTIVE
74ALVCH16373ZQLR
MSL Peak Temp (3)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
GRD
54
1000
SNPB
Level-1-240C-UNLIM
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQL
56
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
74ALVCH16373ZRDR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZRD
54
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
SN74ALVCH16373DGGR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALVCH16373DL
ACTIVE
SSOP
DL
48
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALVCH16373DLR
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALVCH16373KR
NRND
GQL
56
1000
SNPB
Level-1-240C-UNLIM
BGA MI
CROSTA
R JUNI
OR
2000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
25
25
TBD
TBD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2007
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
16-Jul-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
74ALVCH16373GRDR
GRD
54
HIJ
330
16
5.8
8.3
1.55
8
16
Q1
74ALVCH16373ZQLR
ZQL
56
HIJ
330
16
4.8
7.3
1.45
8
16
Q1
74ALVCH16373ZRDR
ZRD
54
HIJ
330
16
5.8
8.3
1.55
8
16
Q1
SN74ALVCH16373DGGR
DGG
48
MLA
330
24
8.6
15.8
1.8
12
24
Q1
SN74ALVCH16373DLR
DL
48
MLA
330
32
11.35
16.2
3.1
16
32
Q1
SN74ALVCH16373KR
GQL
56
HIJ
330
16
4.8
7.3
1.45
8
16
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
74ALVCH16373GRDR
GRD
54
HIJ
346.0
346.0
33.0
74ALVCH16373ZQLR
ZQL
56
HIJ
346.0
346.0
33.0
74ALVCH16373ZRDR
ZRD
54
HIJ
346.0
346.0
33.0
SN74ALVCH16373DGGR
DGG
48
MLA
333.2
333.2
31.75
SN74ALVCH16373DLR
DL
48
MLA
346.0
346.0
49.0
SN74ALVCH16373KR
GQL
56
HIJ
346.0
346.0
33.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
Pack Materials-Page 3
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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