TI 74HCT240

SN54HCT240, SN74HCT240
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS174C – MARCH 1984 – REVISED FEBRUARY 2000
D
D
SN54HCT240 . . . J OR W PACKAGE
SN74HCT240 . . . DW, N, OR PW PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
High-Current Outputs Drive up to 15 LSTTL
Loads
Package Options Include Plastic
Small-Outline (DW), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J) DIPs
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
description
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. The ’HCT240 devices are organized
as two 4-bit buffers/drivers with separate
output-enable (OE) inputs. When OE is low, the
device passes inverted data from the A inputs to
the Y outputs. When OE is high, the outputs are
in the high-impedance state.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
2Y4
1A1
1OE
VCC
SN54HCT240 . . . FK PACKAGE
(TOP VIEW)
1A2
2Y3
1A3
2Y2
1A4
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
1Y1
2A4
1Y2
2A3
1Y3
2Y1
GND
2A1
1Y4
2A2
The SN54HCT240 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HCT240 is characterized for
operation from –40°C to 85°C.
2OE
D
D
FUNCTION TABLE
(each buffer/driver)
INPUTS
OE
A
OUTPUT
Y
L
H
L
L
L
H
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54HCT240, SN74HCT240
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS174C – MARCH 1984 – REVISED FEBRUARY 2000
logic symbol†
1OE
1A1
1A2
1A3
1A4
1
EN
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
1Y4
2A3
2A4
19
EN
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
1
2OE
2
4
18
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
absolute maximum ratings over operating free-air temperature range‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54HCT240, SN74HCT240
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS174C – MARCH 1984 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 3)
SN54HCT240
SN74HCT240
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
0
0.8
0
0.8
V
Input voltage
0
0
Output voltage
0
0
VCC
VCC
V
VO
tt
VCC
VCC
Input transition (rise and fall) time
0
500
0
500
ns
High-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2
2
V
V
V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VOH
VI = VIH or VIL
IOH = –20 µA
IOH = –6 mA
45V
4.5
VOL
VI = VIH or VIL
IOL = 20 µA
IOL = 6 mA
45V
4.5
II
IOZ
VI = VCC or 0
VO = VCC or 0,
ICC
∆ICC†
VI = VIH or VIL
VI = VCC or 0,
IO = 0
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
TA = 25°C
TYP
MAX
SN54HCT240
MIN
MAX
SN74HCT240
MIN
4.4
4.499
4.4
4.4
3.98
4.3
3.7
3.84
MAX
UNIT
V
0.001
0.1
0.1
0.1
0.17
0.26
0.4
0.33
5.5 V
±0.1
±100
±1000
±1000
nA
5.5 V
±0.01
±0.5
±10
±5
µA
8
160
80
µA
1.4
2.4
3
2.9
mA
3
10
10
10
pF
5.5 V
5.5 V
4.5 V
to 5.5 V
Ci
MIN
V
† This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
d
A
Y
ten
OE
Y
tdis
di
OE
Y
tt
Y
VCC
TA = 25°C
MIN
TYP
MAX
SN54HCT240
MIN
MAX
SN74HCT240
MIN
MAX
4.5 V
13
25
37
32
5.5 V
12
23
33
29
4.5 V
21
35
53
44
5.5 V
19
32
48
40
4.5 V
19
35
53
44
5.5 V
18
32
48
40
4.5 V
8
12
18
15
5.5 V
7
11
16
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
3
SN54HCT240, SN74HCT240
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS174C – MARCH 1984 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
d
A
Y
ten
OE
Y
tt
Y
VCC
MIN
TA = 25°C
TYP
MAX
SN54HCT240
MIN
MAX
SN74HCT240
MIN
MAX
4.5 V
20
42
63
53
5.5 V
19
38
56
48
4.5 V
25
52
79
65
5.5 V
22
47
71
59
4.5 V
17
42
63
53
5.5 V
14
38
57
48
UNIT
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
4
TEST CONDITIONS
Power dissipation capacitance
No load
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
40
UNIT
pF
SN54HCT240, SN74HCT240
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS174C – MARCH 1984 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC
From Output
Under Test
CL
(see Note A)
PARAMETER
S1
Test
Point
tPZH
ten
RL
S2
1 kΩ
tPZL
tPHZ
tdis
S2
50 pF
or
150 pF
Open
Closed
Closed
Open
1 kΩ
––
LOAD CIRCUIT
2.7 V
S1
50 pF
tPLZ
tpd or tt
Input 1.3 V
0.3 V
CL
RL
2.7 V
50 pF
or
150 pF
Open
Closed
Closed
Open
Open
Open
3V
1.3 V
0.3 V 0 V
tr
tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
3V
Input
1.3 V
1.3 V
0V
tPLH
In-Phase
Output
1.3 V
10%
tPHL
90%
90%
tr
tPHL
Out-ofPhase
Output
90%
VOH
1.3 V
10% V
OL
tf
tPLH
1.3 V
10%
1.3 V
10%
tf
Output
Control
(Low-Level
Enabling)
3V
1.3 V
1.3 V
0V
tPZL
Output
Waveform 1
(See Note B)
tPLZ
≈ VCC
1.3 V
10%
VOL
tPZH
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
Output
Waveform 2
(See Note B)
1.3 V
90%
VOH
≈0V
tPHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright  2000, Texas Instruments Incorporated