CD74FCT244, CD74FCT244AT BiCMOS OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCBS722A – JULY 2000 – REVISED JULY 2000 D D D D D D D D D CD74FCT244, CD74FCT244AT . . . E, M, OR SM PACKAGE (TOP VIEW) BiCMOS Technology With Low Quiescent Power Buffered Inputs Noninverted Outputs Input/Output Isolation From VCC Controlled Output Edge Rates 64-mA Output Sink Current Output Voltage Swing Limited to 3.7 V SCR Latch-Up-Resistant BiCMOS Process and Circuit Design Package Options Include Plastic Small-Outline (M) and Shrink Small-Outline (SM) Packages and Standard Plastic (E) DIP 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 description The CD74FCT244 and CD74FCT244AT are octal buffer/line drivers with 3-state outputs using a small-geometry BiCMOS technology. The output stages are a combination of bipolar and CMOS transistors that limit the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces the power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 64 mA. These devices are organized as two 4-bit buffers/line drivers with separate active-low output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The CD74FCT244 and CD74FCT244AT devices are characterized for operation from 0°C to 70°C. FUNCTION TABLE (each buffer/driver) INPUTS OE A OUTPUT Y L H H L L L H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD74FCT244, CD74FCT244AT BiCMOS OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCBS722A – JULY 2000 – REVISED JULY 2000 logic symbol† 1OE 1A1 1A2 1A3 1A4 1 EN 2 2OE 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 EN 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 1 2OE 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ DC supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V DC input clamp current, IIK (VI < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA DC output clamp current, IOK (VO < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA DC output sink current per output pin, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA DC output source current per output pin, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA Continuous current through VCC, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 mA Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 mA Package thermal impedance, θJA (see Note 1): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W SM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD74FCT244, CD74FCT244AT BiCMOS OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCBS722A – JULY 2000 – REVISED JULY 2000 recommended operating conditions (see Note 2) MIN MAX UNIT 4.75 5.25 V VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 IOL ∆t/∆v Low-level output current High-level input voltage 2 High-level output current Input transition rise or fall rate (slew rate) 0 V 0.8 V VCC VCC V –15 mA V 64 mA 10 ns/V TA Operating free-air temperature 0 70 °C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C MIN MAX VCC MIN UNIT –1.2 V VIK VOH II = –18 mA IOH = –15 mA 4.75 V VOL II IOL = 64 mA VI = VCC or GND 4.75 V 0.55 0.55 V 5.25 V ±0.1 ±1 mA IOZ IOS† VO = VCC or GND VI = VCC or GND, ICC ∆ICC‡ Ci Co –1.2 MAX 4.75 V 2.4 2.4 ±0.5 5.25 V V ±10 –60 –60 mA 5.25 V VI = VCC or GND, VO = 0 IO = 0 5.25 V 8 80 mA One input at 3.4 V, Other inputs at VCC or GND 5.25 V 1.6 1.6 mA 10 10 pF 15 15 pF VI = VCC or GND VO = VCC or GND mA † Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms. ‡ This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. switching characteristics over recommended operating VCC = 5 V ± 0.25 V (unless otherwise noted) (see Figure 1) free-air CD74FCT244 FROM (INPUT) TO (OUTPUT) tpd A ten tdis PARAMETER temperature range, CD74FCT244AT TA = 25°C TYP MIN MAX Y 4.5 1.5 OE Y 6 OE Y 5 UNIT TA = 25°C TYP MIN MAX 6.5 3.8 1.5 5.3 ns 1.5 8 4.8 1.5 6.5 ns 1.5 7 4.5 1.5 5.8 ns TYP MAX noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C PARAMETER MIN UNIT VOL(P) VOH(V) Quiet output, maximum dynamic VOL 1 V Quiet output, minimum dynamic VOH 0.5 V VIH(D) VIL(D) High-level dynamic input voltage 2 Low-level dynamic input voltage V 0.8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 3 CD74FCT244, CD74FCT244AT BiCMOS OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCBS722A – JULY 2000 – REVISED JULY 2000 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP 35 UNIT pF CD74FCT244, CD74FCT244AT BiCMOS OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCBS722A – JULY 2000 – REVISED JULY 2000 PARAMETER MEASUREMENT INFORMATION 7V CL = 50 pF (see Note A) 500 Ω From Output Under Test Test Point From Output Under Test Open TEST GND CL = 50 pF (see Note A) 500 Ω S1 S1 Open 7V Open 7V tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω Open Drain LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 1.5 V 10% 90% 3V 1.5 V 10% 0 V 90% tr tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES 3V 1.5 V Timing Input 0V tw tsu 3V 1.5 V 1.5 V Input th 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V 1.5 V Input 0V tPLH tPHL 1.5 V 1.5 V VOL tPHL Out-of-Phase Output tPLZ ≈3.5 V 1.5 V tPZH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 (see Note B) tPLH 1.5 V 1.5 V tPZL VOH In-Phase Output 3V Output Control Output Waveform 2 (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V V VOH – 0.3 V OH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr and tf = 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated