SANYO LC75100M

Ordering number : ENA1021
CMOS IC
LC75100M
Digital Echo IC with Microphone
Amplifier Circuit
Overview
The LC75100M is a digital echo IC that incorporates a microphone amplifier and is ideal for use in minicompo and other
audio systems.
Functions
• Digital echo IC incorporating a microphone amplifier.
Specitications
Absolute Maximum Rating at Ta = 25°C, VSS = 0V
Parameter
Symbol
Pin Name
Conditions
Ratings
VDD
Unit
Maximum supply voltage
VDD max
Allowable power dissipation
Pd max
Operating ambient temperature
Topr
-20 to +70
°C
Storage ambient temperature
Tstg
-40 to +125
°C
Ta≤70°C
10.5
V
350
mW
Allowable Operating Ranges (Operating Conditions) at Ta = 25°C
Parameter
Symbol
Pin Name
min
typ
max
9.0
unit
Recommended supply voltage
VDD
VDD
V
Operating supply voltage range
VDDopg
VDD
8.0
10.0
Input high-level voltage
VIH
2.0
3.5
V
Input low-level voltage
VIL
0
0.5
V
Input pulse width
tφW
1.0
Hold time
thold
1.0
Operating frequency
fopg
μs
μs
500
kHz
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
31908HKIM 20071227-S00002 No.A1021-1/14
LC75100M
Electrical Characteristics at Ta=25°C, VDD=9.0V, fin=1kHz, RL=10kΩ
Parameter
Symbol
Pin
Quiescent current
IDDO
VDD
Clock frequency
FCLK
OSC
Conditions
OSC Ex.R=22kΩ
min
1.82
typ
max
unit
13
60
mA
2.6
3.38
MHz
Mic-AMP (Input=MICIN1/MICIN2, Output=MICOUT1/MICOUT2, VIN=-46dBV, VALC=VREF–1.414V, Mic-AMP NF Ex.R=6.2kΩ)
Mic gain 1
VGM1
Mic-AMP NF Ex.R=0Ω
+50
+53
+56
dB
Mic gain 2
VGM2
Mic-AMP NF Ex.R=6.2kΩ
+33
+36
+39
dB
Maximum output voltage
VoTM
Mic Gain=+36dB, THD=1%,
ALC=OFF
Total harmonic distortion 1
1.75
Vrms
THDM1
Mic Gain=+36dB, ALC=OFF,
THDM2
VO=-10dBV
Mic Gain=+36dB, ALC=ON,
Output noise voltage
VNOM
VO=-10dBV, VIN=0dBV
Mic Gain=+36dB, JIS-A
Input impedance
ZiM
ALC attack time
TaA
30
ms
ALC release time
TaR
1.0
s
Total harmonic distortion 2
37
0.3
1.0
%
1.5
2.0
%
-60
-55
dBV
50
62
kΩ
Digital Echo (Input=IN1/IN2, Output=ECHOOUT, VIN=-10dBV, Delay Time=100ms, Mic volume 1/2=0dB, feedback volume=-∞)
Delay time
DT
ECHOOUT
Output level deviation
VGE
ECHOOUT
FCLK=2.6MHz
Maximum output voltage
VoE
ECHOOUT
THD=10%
Total harmonic distortion
THDE
ECHOOUT
Output noise voltage
VNOE
ECHOOUT
100
+2.5
ms
+5.5
+8.5
Filter=A Filter
0.5
2.0
%
Filter=A Filter
-65
-55
dBV
1.5
dB
Vrms
Stereo Line (Input=LCHIN/RCHIN, Output=LCHOUT/RCHOUT, VIN=-10dBV, Line select=STEREO, Mic volume 1/2=ECHO volume=-∞)
Output level deviation
VGS
LCHOUT/RCHOUT
VIN=-10dBV
Maximum output voltage
VoS
LCHOUT/RCHOUT
THD=1%
Total harmonic distortion
THDS
LCHOUT/RCHOUT
JIS-A, Stereo out
Output noise voltage
VNOS
LCHOUT/RCHOUT
JIS-A, ECHO OFF
Vocal removal rate
VC
LCHOUT/RCHOUT
JIS-A, VIN=-10dBV
-2.5
-0.5
+1.5
0.1
%
-85
-75
dBV
-18
-16
dB
0.03
-20
dB
Vrms
1.5
Package Dimensions
unit : mm (typ)
3263
15.2
0.65
7.9
19
10.5
36
1
0.8
0.3
18
0.25
0.1
(2.25)
2.45max
(0.8)
SANYO : MFP36SDJ(375mil)
No.A1021-2/14
LC75100M
Pin Assignment
VALC
1
36
VDD
MICIN1
2
35
LCHIN
ALC1
3
34
RCHIN
MICNF1
4
33
FILTER
MICOUT1
5
32
SELOUT
IN1
6
31
SELIN
MICIN2
7
30
RCHOUT
ALC2
8
29
LCHOUT
MICNF2
9
28
ECHOIN
LC75100M
MICOUT2
10
27
ECHOOUT
IN2
11
26
LPF2
AAF1
12
25
LPF1
AAF2
13
24
D/A
AAF3
14
23
A/D
GND
15
22
NF
CE
16
21
VREF
DI
17
20
DC3V
CL
18
19
OSC
Top view
No.A1021-3/14
LC75100M
System Configuration Diagram
Key Control
LC75100M
Lch
Vocal Cut
+
Lch
+
Rch
Rch
Mic1
Mic Volume
+
Mic AMP
Mic2
Digital ECHO
+
Mic Volume
Mic AMP
ECHO Volume
FEED Back
Volume
Block Diagram
Rch output
Rch Input
Lch output
Lch Input
VCC
36
35
34
33
31
32
30
29
28
27
Selecter
(Lch Mono)
(Rch Mono)
(L+R)
(Vocal Cut)
25
26
LPF
22
23
24
D/A
21
19
20
A/D
+
SRAM
(16k_Bit)
Logic
+
+
ECHO
Volume
Feed back
Volume
+
Mic Volume
Mic AMP
ALC Control
Voltage
Mic AMP
LPF
+
Mic Volume
ALC
1
Mic Input1
Mic Input2
2
3
ALC
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CL
DA
CE
Analog GND
No.A1021-4/14
LC75100M
Pin Description
Pin
Pin Name
No.
Voltage
Internal Equivalent Circuit
Description
1
VALC
2
MICIN1
7
MICIN2
Mic signal input 2
3
ALC1
Auto level control pin 1
8
ALC2
Auto level control pin 2
4
MICNF1
9
MICNF2
5
MICOUT1
10
MICOUT2
ALC detection voltage setting pin
Mic signal input 1
1/2 VDD
Mic feedback signal input pin 1
1/2 VDD
Mic feedback signal input pin 2
1/2 VDD
Mic signal output pin 1
Mic signal output pin 2
6
IN1
11
IN2
1/2 VDD
ECHO circuit signal input pin 2
28
ECHOIN
ECHO signal input pin
12
AAF1
13
AAF2
25
LPF1
26
LPF2
ECHO circuit signal input pin 1
AAF input pin 1
1/2 VDD
AAF input pin 2
LPF input pin 1
13
LPF input pin 2
26
12
25
Continued on next page.
No.A1021-5/14
LC75100M
Continued from preceding page.
Pin
Pin Name
No.
Voltage
Internal Equivalent Circuit
Description
1/2 VDD
AAF input pin 3
GND
0V
Analog GND
CE
0V/3.3V
CCB CE pin
14
AAF3
15
16
18
CL(SCL)
17
DI(SDA)
0V/3.3V
CCB DI pin/I2C bus SDA pin
19
OSC
0V/3.3V
Oscillator circuit adjustment pin
20
DC3V
3.3V
Power supply for logic block
21
VREF
1/2 VDD
Internal reference voltage
22
NF
1/2 VDD
A/D pin
CCB CL pin/I2C bus SCL pin
Continued on next page.
No.A1021-6/14
LC75100M
Continued from preceding page.
Pin
Pin Name
No.
Voltage
Internal Equivalent Circuit
Description
A/D pin
23
A/D
24
D/A
1/2 VDD
27
ECHOOUT
29
LCHOUT
Lch output
30
RCHOUT
Rch output
31
SELIN
1/2 VDD
Selector input pin
32
SELOUT
1/2 VDD
Selector output pin
33
FILTER
1/2 VDD
Filter input pin 1
34
RCHIN
1/2 VDD
Rch input pin
35
LCHIN
D/A pin
ECHO signal output pin
1/2 VDD
Lch input pin
34
35
36
VDD
Supply voltage
No.A1021-7/14
LC75100M
Control Data (Serial Data Input) Format
Various settings of the LC75100M can be configured with a CCB or I2C bus. When controlling the LC75100M via an
I2C bus, set and hold the CE pin at low level.
(1) CCB control
1 Control register
• IN1 mode
Test0
0
(7) Test
Test1
M1D0
0
M1D1
Test2
M1D2
(3) Mic1 Volume
Test3
0
0
KEY
(2) Ext Key Control
0
LD0
M2D0
LD1
FB0
0
M2D1
0
(3) Mic2 Volume
0
FB1
1
0
1
M2D2
1
0
0
FB2
0
(1) Stereo Line Data
→
LD2
Address
• IN2 mode
1
1
1
0
0
1
(6) Feedback Volume
0
DT2
DT1
DT0
0
ED2
ED1
ED0
(5) ECHO Volume
0
(4) Delay Time Control
→
0
Address
No.A1021-8/14
LC75100M
2 Serial data input
• CL: Normal Hi
tEL
tES
tEH
CE
CL
tSU
tHD
B0
DI
B1
B2
B3
A0
A1
A2
A3
LD2
LD1 LD0
TEST2 TEST1 TEST0
tLC
Internal data
• CL: Normal Low
(2) I2C bus control
I2C bus register
The I2C (Inter IC) bus is a bus system developed by Philips Corporation.
It controls the start and stop condition with SDA (Serial Data) and SCL (Serial Clock). The outputs of these signals
are of open drain type and wired OR.
SCL
SDA
S
ACK
ACK
P
S: Start condition/P: Stop condition/ACK: Acknowledge
Data is transferred MSB first.
One unit is made up of 8 bits. ACK is returned by the slave for acknowledgement.
The slave IC reads the data on the rising edge of SCL.
The master IC changes the data on the falling edge of SCL.
1 Control registers
• Slave Address
MSB
0
LSB
0
1
1
1
0
0
0
Note: The LC75100M can be used in the receive only mode if the LSB is set to 0.
No.A1021-9/14
LC75100M
• I2C Data
Function
Sub Address
Data
BINARY
HEX
D7
D6
D5
D4
D3
D2
D1
D0
Stereo line select
0000 0001
01
LD2
LD1
LD0
KEY
0
MID2
MID1
MID0
Mic volume control
0000 0010
02
0
M2D2
M2D1
M2D0
TEST3
TEST2
TEST1
TEST0
Delay time control
0000 0011
03
0
DT2
DT1
DT0
0
ED2
ED1
ED0
0000 1000
04
0
FB2
FB1
FB0
0
0
0
0
ECHO/Feedback
volume
*: All test bits must be set to 0.
Control Data Description (common to both CCB and I2C bus)
No
(1)
Control Block/Data
Line Select
Description
Related Data
• Determines the line output.
LD2
LD1
LD0
(2)
External key control
LD2
LD1
LD0
0
0
0
Stereo output
0
0
1
Lch Mono output
0
1
0
Rch Mono output
0
1
1
L+R/2 output
1
0
0
Vocal cut output
1
0
1
Reserve
1
1
0
Reserve
1
1
1
Reserve
• Determines the path that uses the external key control.
enable/disable key
KEY
(3)
Mic volume gain data
External Key Control
0
Disabled
1
Enabled
• Determines the gain of mic inputs 1 and 2.
M1D2
M1D1
M1D2
M1D1
M1D0
M2D2
M2D1
M2D0
M2D1
0
0
0
0dB
M2D0
0
0
1
-2dB
0
1
0
-4dB
0
1
1
-6dB
1
0
0
-9dB
1
0
1
-12dB
1
1
0
-15dB
1
1
1
-∞
M1D0
M2D2
Continued on next page.
No.A1021-10/14
LC75100M
Continued from preceding page.
No
(4)
Control Block/Data
Delay time data
Description
Related Data
• Determines the echo delay time.
DT2
DT1
DT0
(5)
Echo volume gain data
DT2
DT1
DT0
0
0
0
OFF
0
0
1
75ms
0
1
0
100ms
0
1
1
125ms
1
0
0
150ms
1
0
1
175ms
1
1
0
200ms
1
1
1
Reserved
• Determines the gain of the echo output.
ED2
ED1
ED0
(6)
Feedback volume gain
ED2
ED1
ED0
0
0
0
0dB
0
0
1
-2dB
0
1
0
-4dB
0
1
1
-6dB
1
0
0
-9dB
1
0
1
-12dB
1
1
0
-15dB
1
1
1
-∞
• Determines the volume of the echo feedback.
data
FB2
FB1
FB0
(7)
IC test data
TEST3
FB2
FB1
FB0
0
0
0
-2dB
0
0
1
-4dB
0
1
0
-6dB
0
1
1
-8dB
1
0
0
-∞
1
0
1
Reserve
1
1
0
Reserve
1
1
1
Reserve
• Used for testing the IC.
TEST3 to TEST0 must all be set to 0.
TEST2
TEST1
TEST0
No.A1021-11/14
10k
10k
0.01 F
0.01 F
0.01 F
1 F
1 F
1 F
6k
6k
1 F
2.2 F
22k
0.1 F
100 F
1000pF
4700pF
4700pF
1000pF
1 F
2.2 F
1000pF
1 F
0.22 F
1 F
1 F
0.1 F
1 F
0.1 F
220 F
0.22 F
10k
LC75100M
Recommended Circuit (Mic-Gain=-36dB)
[CCB Control]
[I2C Control]
No.A1021-12/14
LC75100M
Setting the Mic Amplifier Gain
The mic amplifier gain can be adjusted by the resistors connected to pins 3 and 34. Moreover, the low frequency region
can be cut off by connecting a capacitor. The mic amplifer has a built-in ALC (Auto Level Control) and the output level
can be controlled by applying the reference voltage to pin 1.
2
R2
4
R4
R3
+
R1
5
ALC
C1
VREF
3
(1) Setting the mic AMP gain
• R1=562.3kΩ, R2=1.0kΩ
[When Mic Gain=45dB]
R4=(R1/Mic Gain)-R2
=562.3k/177.8-1k
≈2.2kΩ
(2) Determining the fc
fc =
1
2π(R1 + 1k)C1
(3) Setting the ALC operating voltage
1.0Vrms
1/2 VCC+1.41V
1/2 VCC
VALC = 1/2 VCC-1.41V
1/2 VCC-1.41V
0V
No.A1021-13/14
LC75100M
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
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export license from the authorities concerned in accordance with the above law.
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Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
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intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of March, 2008. Specifications and information herein are subject
to change without notice.
PS No.A1021-14/14