SANYO LV23015T

Ordering number : ENA1352
Bi-CMOS IC
LV23015T
For Mini Component, receiver
1-chip Tuner IC
Incorporating PLL
Overview
The LV23015T is a Single-chip tuner IC with built-in PLL for mini component, receiver.
Functions
• AM tuner
• FM tuner
• MPX stereo decoder
• PLL frequency synthesizer
Specifications
Maximum Ratings at Ta = 25 °C
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
VCC max
VCC
Maximum input voltage
VIN1 max
CE, CI, CL
7.0
V
VIN2 max
XIN
*1 Vreg2+0.3
V
VO1 max
DO
7.0
V
Vreg2+0.3
V
Maximum output voltage
7.0
V
VO2 max
XOUT, PD
VO3 max
BO1, AOUT
12.0
V
Allowable power dissipation
Pd max
Ta≤70°C *2
400
mW
Operating temperature
Topr
-20 to +70
°C
Storage temperature
Tstg
-40 to +125
°C
*1 Vreg2 : 21 pin output voltage (Reference voltage of PLL) Reference value (3.0V±0.2V)
*2 Specified board : 114.3mm×76.1mm×1.6mm, glass epoxy board.
•
•
CCB is a registered trademark of SANYO Electric Co., Ltd.
CCB is SANYO Semiconductor's original bus format. All bus addresses are managed by SANYO
Semiconductor for this format.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
N0508 MS PC 20081020-S00019 No.A1352-1/17
LV23015T
Operating Condition at Ta = 25 °C
Parameter
Symbol
Recommended supply voltage
VCC
Operating supply voltage range
VCC op
Conditions
Ratings
Unit
5.0
V
4.0 to 6.0
V
PLL block Allowable Operating Range at Ta = -20°C to +70°C, VSS = 0V
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
Input high level voltage
VIH
CE, CL, DI
0.7Vreg2
6.0
V
Input low level voltage
VIL
CE, CL, DI
0
0.3Vreg2
V
V
Output voltage
Operating frequency
VO1
DO
0
6.0
VO2
BO1, AOUT
0
10
fIN1
XIN ; VIN1
75
V
kHz
fIN2
FMIN ; VIN2
10
160
fIN3
AMIN (SNS = 1) ; VIN3
2
40
MHz
MHz
fIN4
AMIN (SNS = 0) ; VIN4
0.5
10
MHz
Note : The XIN pin has extremely high input impedance, so that due care must be taken to prevent leakage.
Operating Characteristics at Ta = 25°C, VCC = 5.0V, for the specified test circuit.
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
FM-FE characteristics : fc = 98MHz, fm = 1kHz, 22.5kHzdev.
3dB sensitivity
-3dB LS
60dBμV, 22.5kHzdev output reference,
5
-3dB input
(12)
dBμV
Reference
EMF
value
Practical sensitivity
QS
S/N = Input at S/N = 30dB
8
(15)
dBμV
Reference
EMF
value
FM oscillation voltage
VOSC
No input, Pin 32 output, FET probe used
30
40
50
mVrms
FM-EF stereo characteristics : fc = 98MHz, fm = 1kHz, 75kHzdev, L+R = 90%, Pilot = 10%, VIN = 60dBμVEMF
Stereo ON bandwidth
ST-BW
ST-ON frequency bandwidth,
(300)
18pin (DO) output
kHz
Reference
value
FM-IF monaural characteristics : fc = 10.7MHz, fm = 1kHz, 75kHzdev.
Demodulation output
VO
100dBμV, 12pin output
750
1000
1200
mVrms
Channel balance
CB
100dBμV, 12pin output
-1.0
0
+1.0
dB
Signal to noise ratio
S/N
100dBμV, 12pin output
68
74
dB
AM suppression ratio
AMR
70dBμV input 12pin output reference,
40
50
dB
FM = no-mod, AM = 1kHz-30%mod,
12pin output
Total harmonic distortion
THD
100dBμV, 12pin output
0.6
1.5
%
3dB LS
100dBμV, 75kHzdev output reference,
38
44
dBμV
53
dBμV
(monaural)
3dB sensitivity
-3dB input
IF count sensitivity
IF-C3
SDC0 = 1, SDC1 = 0, 18pin (DO) output
39
46
Mute attenuation
Mute-Att
100dBμV, 12pin output
60
70
dB
28
38
dB
FM-IF stereo characteristics : fc = 10.7MHz, fm = 1kHz, Pilot = 10%
Separation
SEP
100dBμV, L+R = 90%, L-mod,
12pin output/13pin output
Total harmonic distortion (main)
THD-ST
100dBμV, L+R = 90%, Main-mod, 12pin output
1.0
2.0
%
Total harmonic distortion (L only)
THD-L
100dBμV, L+R = 90%, L-mod, 12pin output
0.6
2.0
%
Stereo ON sensitivity
ST-ON
100dBμV, L+R = 90%, Pin 18(DO) output
0.6
6.5
%
Capture range
CR
Pilot = 10% modulated, Pin 18(DO) output
-0.4
+0.4
kHz
Continued on next page.
No.A1352-2/17
LV23015T
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
AM characteristics : fc = 1000kHz, fm = 1kHz, 30%mod
Detection output 1
VO1
23dBμV, 12pin output
60
120
240
mVrms
Detection output 2
VO2
80dBμV, 12pin output
220
330
440
mVrms
Signal to noise ratio 1
S/N1
23dBμV, 12pin output
15
20
Signal to noise ratio 2
S/N2
80dBμV, 12pin output
47
54
Total harmonic distortion
THD
80dBμV, 12pin output
IF count sensitivity
IF-C
18pin (DO) output
Mute attenuation
Mute-Att
80dBμV, 12pin output
dB
dB
1.2
2.5
%
16
26
36
dBμV
54
65
dB
Current drain
FM tuner
ICCFM
No input at FM
25
35
45
mA
AM tuner
ICCAM
No input at AM
11
22
33
mA
PLL characteristics
Built-in return resistor
Rf
XIN
Built-in output resistor
Rd
XOUT
Hysteresis width
VHIS
CE, CL, DI
Output high level voltage
VOH
PD ; IO = -1mA
Output low level voltage
VOL2
VOL3
Input high level current
Input low level current
Output off-leak current
8
MΩ
250
kΩ
0.1Vreg2
V
Vreg2-1.0
V
BO1 ; IO = 1mA
0.25
V
BO1 ; IO = 5mA
1.25
V
DO ; IO = 1mA
0.25
V
VOL4
AOUT ; IO = 1mA, AIN = 2.0V
0.5
V
IIH1
CE, CL, DI ; VI = 6.0V
5.0
μA
IIH2
XIN ; VI = VDD
0.9
μA
0.16
IIH3
AIN ; VI = 6.0V
200
nA
IIL1
CE, CL, DI ; VI = 0V
5.0
μA
IIL2
XIN ; VI = 0V
0.9
μA
IIL3
AIN ; VI = 0V
200
nA
IOFF1
AOUT, BO1 ; VO = 10V
5.0
μA
IOFF2
DO ; VO = 6.0V
5.0
μA
0.16
Note : The reference value is calculated from more than one data and does not ensure conformance to the specifications. No data control by selection is
implemented.
Package Dimensions
unit : mm (typ)
3253B
9.75
0.5
5.6
7.6
19
36
1
0.18
18
0.15
0.08
(1.0)
(0.63)
1.2max
(0.5)
SANYO : TSSOP36(275mil)
No.A1352-3/17
IFSW
(4) IFSW
SDC0
(15) SDC0
P13
P14
P15
SNS
DVS
DZ0
DZ1
GT0
GT1
R1
TEST2
TEST1
TEST0
(12) TEST
R0
IFS
(11) IFS
(2) R-CTR
R3
R2
DNC
DLC
(10) PD-C
(13) Don't care
SDC1
CTE
P12
UL1
(3) IF-CTR
P11
P9
P8
UL0
(1) P-CTR
P7
P6
P5
P4
P3
P2
P1
P0
P10
1 0 0 1 0 1 0 0
DOC2
Address
DOC1
(2) IN2 mode
(16) SDC1
(3) IF-CTR
(8) DZ-C
(7) UNLOCK
(6) DO-C
STSW
(14) STSW
DOC0
BDSW1
(5) BDSW
0
BO1
(9) O-PORT
0
DI
1
DI
0
LV23015T
Composition of DI control data (serial data input)
(1) IN mode
Address
0 0 0 1 0 1 0 0
No.A1352-4/17
LV23015T
Description of DI control Data
No.
Control/data
(1)
Programmable
divider data
Description
Related data
• Data to set the number of divisions of programmable divider Binary value using P15 as MSB.
LSB varies depending on DVS and SNS.
(* : don’t care)
P0 to P15
DVS
DVS, SNS
SNS
LSB
Set number of divisions (N)
Actual number of divisions
1
*
P0
272 to 65535
Twice the set value
0
1
P0
272 to 65535
Set value
0
0
P4
4 to 4095
Set value
* LSB : P0 to P3 invalid when LSB is P4.
• Selection of the signal input (FMIN, AMIN) to the programmable divider and switching of the input
frequency.
(* : don’t care)
DVS
(2)
Reference
divider data
R0 to R3
SNS
Input
Operation frequency range
10 to 160MHz
1
*
FMIN
0
1
AMIN
2 to 40MHz
0
0
AMIN
0.5 to 10MHz
• Data to select the reference frequency.
R3
R2
R1
R0
Reference frequency
0
0
0
0
25kHz
0
0
0
1
25kHz
0
0
1
0
25kHz
0
0
1
1
25kHz
0
1
0
0
12.5kHz
0
1
0
1
6.25kHz
0
1
1
0
3.125kHz
0
1
1
1
3.125kHz
1
0
0
0
5kHz
1
0
0
1
5kHz
1
0
1
0
5kHz
1
0
1
1
1kHz
1
1
0
0
3kHz
1
1
0
1
15kHz
1
1
1
0
PLL INHIBIT+X’tal OSC STOP
1
1
1
1
PLL INHIBIT
* PLL INHIBIT
• Programmable divider and IF counter blocks stop, FMIN, AMIN, and IFIN inputs enter the pull-down
state (GND), and the charge pump has high impedance.
(3)
IF counter
control data
• IF counter measurement start data
IFS
CTE = 1 : Count start
= 0 : Count reset
CTE
GT0, GT1
(4)
MUTE
IF count output
SD time constant
changeover
control data
• Determines the universal counter measurement time.
GT1
GT0
Measurement time
Wait time
0
0
4ms
3 to 4ms
0
1
8ms
3 to 4ms
1
0
16ms
3 to 4ms
1
1
32ms
3 to 4ms
• Data to determine the output of the output port IFSW, controlling the MUTE function, IF count
output (*1), and SD time constant changeover circuit (*2).
“Data” = 0 : MUTE, IF count output, SD time constant changeover circuit-OFF
(during normal reception)
1 : MUTE, IF count output, SD time constant changeover circuit-ON
(during search of the desired station)
IFSW
*1 : IF counter buffer output entered in the IF counter circuit of the PLL logic block
*2 : The rise time of AM-AGC voltage is shortened through rapid charge to the pin-25 external
capacity when IFSW has been set to 1.
(5)
FM/AM
BAND switch
control data
• Data to determine the output of the output port BDSW, controlling switching of BAND.
“Data” = 0 : AM
1 : FM
BDSW
Continued on next page.
No.A1352-5/17
LV23015T
Continued from preceding page.
No.
Control/data
(6)
DO pin
Description
Related data
• Data to determine the output of the DO pin.
control data
UL0, UL1
DOC2
DOC1
DOC0
0
0
0
Open
0
0
1
Low detection of unlock
0
1
0
end-UC (See below)
0
1
1
Open
1
0
0
Open
1
0
1
Low at SD ON
1
1
0
Low at stereo
1
1
1
Open
DOC0
DOC1
DOC2
CTE
DO pin state
• Open selected with power ON reset
* IF counter measurement end check
DO pin
(1) Count start
(2) Count end
(3) CE : HI
(1) DO pin open automatically when end-UC is set and the IF counter starts (CTE = 0→1).
(2) DO pin becomes low, enabling check of the counter end when the IF counter measurement is
over.
(3) DO pin open with serial data input/output (CE pin : Hi)
Note)DO pin open regardless of the DO pin control data (DOC0 to 2) during data input period (IN1
and IN2 modes CE-Hi period).
The DO pin state allows output of the content of internal DO serial data in synchronization with
CL regardless of the DO pin control data (DOC0 to 2) during data input period (OUT mode CE :
Hi period).
(7)
Unlock
detection data
• Data to select the phase error (φE) detection width to determine if PLL is locked. Unlock is determined
when the phase error exceeding the detection width occurs.
DOC1
(* : don’t care)
UL0, UL1
DOC0
UL1
UL0
φE Detection width
0
0
Stop
Open
0
1
0
φE output directly
1
*
±6.67μs
φE extended by 1 to 2ms
DOC2
Detection output
* unlock : DO pin becomes Low and the serial data output becomes UL = 0.
(8)
Phase
comparator
control data
DZ0, DZ1
• Data to control the dead band of phase comparator.
DZ1
DZ0
Deadband mode
0
0
DZA
0
1
DZB
1
0
DZC
1
1
DZD
Dead band : DZA < DZB < DZC < DZD
(9)
Output port data
• Data to determine the output of output ports BO1
“Data” = 0 : OPEN
BO1
(10)
Charge pump
control data
DLC
1 : Low
• Data for forced control of the charge pump output
DLC
Charge pump output
0
Normal operation
1
Forced Low
When the VCO control voltage (Vtune) develops dead lock because of stop of oscillation of VCO at
0V, set the charge pump output to LOW and Vtune to VCC to escape the dead lock. (Dead lock
clear circuit)
(11)
IFS
(12)
LSI test data
• Normally, set data = 1. Setting the data = 0 causes worsening of the input sensitivity, resulting in decrease
of the sensitivity by about 10 to 30mVrms.
• LSI test data
TEST0
TEST0 to 2
TEST1
All to be set to “0”
TEST2
All set to 0 for power ON reset
(13)
DNC
• Set data = 0.
Continued on next page.
No.A1352-6/17
LV23015T
Continued from preceding page.
No.
Control block data
(14)
Forced monaural
Description
Related data
• Data to determine the output of the output port STSW, controlling the forced monaural stereo
function
control data
“Data” = 0 : MONO
1 : STEREO
STSW
• Data to determine the output of output ports SDC0 and SDC1, setting the SD sensitivity
(15)
SD sensitivity
(16)
adjustment data
“Data” = SDC0 : 0, SDC1 : 0 → SD sensitivity = 50dBμV (Typ)
SDC0 : 0, SDC1 : 1 → SD sensitivity = 53dBμV (Typ)
SDC0
SDC0 : 1, SDC1 : 0 → SD sensitivity = 59dBμV (Typ)
SDC1
SDC0 : 1, SDC1 : 1 → SD sensitivity = 64dBμV (Typ)
Composition of the DO control data (serial data output)
(1) OUT mode
Address
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
(3) IF-CTR
C12
C13
C14
C15
C16
C17
C18
C19
0
UL
SDIND
(1) IN-PORT
DO
0 1 0 1 0 1 0 0
STIND
DI
Description of DO output data
No.
(1)
Control/data
Stereo indicator
SD indicator
Control data
Description
Related data
• Data latching stereo indicator and SI indicator states.
Latch made at a time of the data output mode (OUT mode).
STIND←Stereo indicator state
0 : ST ON, 1 : ST OFF
SDIND←SD indicator state
0 : SD ON, 1 : SD OFF
STIND, SDIND
(2)
PLL unlock data
• Data latching the content of the unlock detection circuit
UL←0 : At unlock
UL
(3)
IF counter
Binary counter
UL0
UL1
1 : At lock or detection stop mode
• Data latching the content of IF counter (20 bit binary counter)
CTE
C19←MSB of binary counter
GT0
C0 ←LSB of binary counter
GT1
C19 to C0
No.A1352-7/17
LV23015T
Serial data input (IN1/IN2) tSU, tHD, tEL, tES, tEH ≥ 0.75μs tLC < 0.75μs
(1) CL : normal Hi
tEL
tES
tEL
CE
CL
tHD
tSU
B0
DI
B1
B2
B3
A0
A1
A2
A3
P0
P1
P2
P3
R0
R1
R2
R3
tLC
Internal data
(2) CL : normal Low
tEL
tES
tEL
CE
CL
tSU
tHD
B0
DI
B1
B2
B3
A0
A1
A2
A3
P0
P1
P2
P3
R0
R1
R2
R3
tLC
Internal data
Serial data output (OUT) tSU, tHD, tEL, tES, tEH ≥ 0.75μs tDC, tDH < 0.35μs
(1) CL : normal Hi
tEL
tES
tEL
CE
CL
tSU
tHD
B0
DI
B1
B2
B3
A0
A1
A2
A3
tDH
DO
tDH
I2
(2) CL : normal Low
tEL
I1
tDH
UL
C3
C2
tES
C1
C0
tEL
CE
CL
tSU
DI
tHD
B0
B1
B2
B3
A0
A1
A2
A3
tDH
DO
tDH
I2
I1
tDH
UL
C3
C2
C1
C0
Note : The DO pin is an Nch open drain pin, so that the data change time (tDC, tDH) changes depending on the pull-up
resistance and substrate capacity.
No.A1352-8/17
LV23015T
Serial data timing
VIH
CE
tCH
VI
VIL
CL
VIL
tCL
VIH
VIL
VIH
VIH
tEL
VIH
VIL
tES
tEH
DI
VIL
tSU
tHD
VIL
tDC
tDC
tDH
DO
tLC
Old
Internal data latch
New
<< CL stopped at “L” level >>
VIH
CE
tCH
CL
VIL
tCL
VIH
VIL
VIH
VIH
VIH
VIH
VIL
tEL
tES
tEH
DI
VIL
tSU
tHD
VIL
tDC
tDH
DO
tLC
Internal data latch
Old
New
<< CL stopped at “H” level >>
Parameter
Symbol
Pin
Conditions
Min
Typ
Max
Unit
Data setup time
tSU
DI, CL
0.75
μs
Data hold time
tHD
DI, CL
0.75
μs
Clock L level time
tCL
CL
0.75
μs
Clock H level time
tCH
CL
0.75
μs
CE wait time
tEL
CE, CL
0.75
μs
CE setup time
tES
CE, CL
0.75
μs
CE hold time
tEH
CE, CL
0.75
Data latch change time
tLC
Data output time
tDC
tDH
DO, CL
Varies depending on the pull-up resistance
DO, CE
and substrate capacity
μs
0.75
μs
0.35
μs
No.A1352-9/17
AM ANT
BPF
1
AM
RF
FM
RF
36
+
2
REG
GND2
35
3
FM
MIX
34
VCC2
4
GND1
33
5
AM
MIX
AM
OSC
31
6
+
VCC1
7
AM
IF
AM
DET
30
SD
8
FM
IF
FM
DET
FM
S-METER
29
450kHz 10.7MHz
AM
AGC
OSC
BUFFER
FM
OSC
32
+
9
LPF
+
10
+
PILOT
DET
TRIG
27
IF
BUFFER
ST
28
+B
11
ST
SW
FF
26
12
23
L-OUT
+B
R-OUT
13
14
PHASE
MUTE
COMP
VCO
24
DECODER
FF
FF
25
+
22
PHASE DETECTOR
CHARGE PUMP
15
17
μ-COM
16
CCB
I/F
DATA SHIFT REGISTOR
LATCH
UNIVERSAL
COUNTER
20
X'tal
75kHz
19
VCC
18 REG2
UNLOCK
DETECTOR
REFERENCE
DIVIDER
REG2 POWER ON
RESET
21
PROGRAMABLE SWALLOW
DIVIDER
COUNTER
+
+
LV23015T
Block Diagram
No.A1352-10/17
51Ω
0.047μF
39mH
+
GND1
/VSS
4
0.047μF
+
AM
IF IN
7
AM
OSC
SFULA450KU2B-B0
51Ω
SFELA10M7GA00-B0
0.047μF
300Ω
+ 0.47μF 10kΩ
+
1μF
3.3kΩ
23
4.7μF
R-OUT
L-OUT
SD
IND
14
AM
FM
DET OUT DET OUT
24
L-OUT R-OUT
12
13
AM
AGC
25
4700pF
+B = 9V
2.2kΩ
FM IF IN
+
1μF
FM
P-DET P-COMP DET
9
10
11
FM-S
METER
FM
IF IN
8
A-IN
A-OUT
BO1
26
+
CE
15
MPX
IN
22
+
0.1μF 20kΩ
+18kΩ
4700pF
100μF
VCC1
6
FM
MIX
3
AM
MIX
5
10μF
REG
2
FM
OSC
FM
FM
VCC2
BYPASS RF OUT
27
SW7
28
100kΩ
29
SW8
1.2kΩ
+
22μF
AM ANT
1000pF
30
SW9
51kΩ
4.7μF
3.3kΩ
10pF
SW5
20
CL
17
SW2
DO
18
X-IN
VCC = 5.0V
10kΩ
SW3
SW4
19
75kHz
10pF
100kΩ
X-OUT
μ-COM
DI
16
VDD
21
0.1μF
+
100μF
CFV-206
AM
RF IN
1
0.047μF
10pF
GND2
SVC201
FM RF
SA-149
31
8pF
32
SA-181
SA-151
FM OSC
33pF
33
390
pF 16pF
SVC347
1μF
FM
RF IN
SVC201
34
1000pF
0.047μF
33kΩ
3300pF
35
10Ω
33kΩ
910pF
36
1000pF
0.047μF
0.047μF
FM RF
IN
51Ω
33kΩ
Vt = 8V
LV23015T
Test Circuit
2.2kΩ
600BNAS-10963Z
SA-164
No.A1352-11/17
LV23015T
LV23014T Pin description and pin voltage (VCC = 5.0V, +B = 9.0V)
No.
1
Pin name
AM RF input
Pin description
Connect the AM ANT coil between this pin
No input voltage (V)
AM
FM
Vreg1
Vreg1
Internal equivqlent circuit
2
and pin 2 (Vreg1).
1
2
REG1
Reference voltage of AM/FM, IF/MPX block
2.2
2.2
2
3
FM MIX output
Rout = 270Ω
(2/3) VCC (2/3) VCC
-0.5
-0.7
3
Rout
4
GND1
GND of AM/FM, IF/MPX block
5
AM MIX output
Connect the AM MIX coil between this pin and
0
0
VCC
VCC
5.0
5.0
Vreg1
Vreg1
5
pin 6 (VCC voltage).
6
VCC1
VCC of AM/FM, IF/MPX block
7
AM IF input
Rin = 2kΩ
6
7
Rin
2
8
FM IF input
Rin = 330Ω
Vreg1
Vreg1
8
Rin
2
9
Pilot filter
R = 10kΩ
VCC-1
VCC-1
9
R
Continued on next page.
No.A1352-12/17
LV23015T
Continued from preceding page.
No.
Pin name
10
Phase comparator
Pin description
R = 10kΩ
No input voltage (V)
AM
FM
VCC-1
VCC-1
Internal equivqlent circuit
10
filter
R
11
FM DET
Connect the FM DET coil between this pin
VCC
VCC
and pin 6 (VCC voltage).
Recommended detection coil :
600BNAS-10963Z by TOKO.
11
12
L output
Resistance 2.2kΩ for output level
6.0
6.0
6.0
6.0
12
adjustments is connected between pin 12/13
13
R output
and +B (+9V).
(
R = 600Ω
13
)
R
14
SD IND
SD indicator Active low output.
R = 30kΩ
15
CE
Vreg2
Vreg2
21
14
R
Chip enable port
At changeover from "L" to "H" address
latching.
At changeover from "H" to "L" data latching.
15
16
DI
Serial data input port
Sets data in synchronization with rise of data
clock.
16
17
CL
Data clock input port
17
18
DO
Data output port
Outputs various data in synchronization with
18
fall of data clock in the out mode.
Continued on next page.
No.A1352-13/17
LV23015T
Continued from preceding page.
No.
Pin name
19
XIN
20
XOUT
Pin description
No input voltage (V)
AM
Internal equivqlent circuit
FM
Clock for internal reference
Connect 75kHz crystal oscillator.
19
20
21
VREG2
Reference voltage of PLL block
3.0
3.0
21
22
MPX input
Rin = 20kΩ
Vreg1
Vreg1
2
Rin
22
23
FM detection
The separation can be adjusted with an
output
external capacitor connected between this pin
0.8
Vreg1
Rout
and GND.
23
Rout = 3.3kΩ
24
AM detection
AM low frequency characteristic can be
output
adjusted with an external capacitor connected
2.0
0
Rout
between this pin and GND.
24
Rout = 5.0kΩ
25
AM AGC output
R = 13.8kΩ
0.8
0
25
R
26
FM S-meter
The FMSD sencitivity can be adjusted with an
output and FM
external resistor connected between this pin
SD adjust
and GND.
R = 14.0kΩ
27
AIN
0.8
26
R
Nch MOS transistor for PLL active low pass
filter.
28
0
1kΩ
27
AOUT
28
Continued on next page.
No.A1352-14/17
LV23015T
Continued from preceding page.
No.
Pin name
29
BO1
30
AM OSC
Pin description
No input voltage (V)
AM
Internal equivqlent circuit
FM
General purpose output port
AM OSC circuit with ALC
29
VCC
VCC
VCC
4.95
AM OSC coil used between pins 31 and 6
30
6
(VCC voltage).
31
FM OSC
R = 10kΩ
32
C1 = 10pF
C2 = 20pF
R
31
C1
C2
32
VCC2
VCC of FM FE block
33
FM RF output
FM RF coil used between pins 33 and 32
FM bypass
(VCC voltage).
The capacity of 1000pF is connected
34
5.0
5.0
VCC
VCC
0
1.6
0
0.9
33
32
34
between pins 34 and 35 (GND).
35
FM RF input
Rin = 1.5kΩ
36
Rin
35
GND2
GND of FM FE block
0
0
No.A1352-15/17
SVC201
9pF
SVC347
0.047μF
+
10μF
FM
AM
REG MIX OUT GND1 MIX OUT VCC1
2
3
4
5
6
+
AM
IF IN
7
+
3.3kΩ
+ 1μF
47pF
SFELA10M
7FA00-B0
SFU450A
100μF 0.047μF
+
FM-S
METER
26
24
23
4.7μF
22
+ 18kΩ
21
10μF
10pF
10kΩ
L-OUT R-OUT
2.2kΩ
4700pF
+B = 9.0V
SD
R-OUT
14
SD
IND
15
μ-COM
CE DI CL
16
17
19
10kΩ
DO
18
X-IN
X'tal
75kHz
20
0.1μF
10pF
AM
AM
FM
MPX REG2 X-OUT
AGC DET OUT DET OUT SIGNAL
IN
25
+
22kΩ
FM
P-COMP DET L-OUT
10
11
12
13
A-IN
0.47μF
P-DET
9
FM
IF IN
8
1μF
A-OUT
BO1
27
+
1μF
AM
OSC
28
29
1.2kΩ
4.7μF
22μF
FM
OSC
30
390pF 15pF
3.3kΩ
0.01μF
FM
VCC2
FM
BYPASS RF OUT
31
AM
RF IN
1
32
GND2
SA-149
FM
RF IN
33
8pF
SVC201
1000pF
10kΩ
SA-181
SA-151 33pF
35
34
1000pF
33kΩ
100kΩ
36
GFWB7
0.047μF
1000pF
0.047μF
820pF
AM ANT
FM IN
33kΩ
Vt = 9V
VCC = 5.0V
LV23015T
Application Circuit
4700pF
2.2kΩ
600BNAS
-10963Z
SA-164
0.047μF
No.A1352-16/17
LV23015T
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
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to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
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limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
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Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
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Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
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intellctual property rights which has resulted from the use of the technical information and products mentioned
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This catalog provides information as of November, 2008. Specifications and information herein are subject
to change without notice.
PS No.A1352-17/17