Ordering number : ENA0120A LC86F3448B CMOS IC 64K-byte Flash Memory (ROM 48K-byte+CGROM 16K-byte) on-chip 640-byte RAM and 352x9 bit Display RAM 8-bit 1-chip Microcontroller Overview The LC86F3448B is a CMOS 8-bit single chip microcontroller with Flash Memory for the LC863400series. This microcontroller contains the following on-chip functional blocks: • CPU : Operable at a minimum bus cycle time of 0.424µs • On-chip ROM capacity: 64K bytes Flash Memory Program ROM: 48K bytes CGROM: 16K bytes • On-chip RAM capacity: 640 bytes • OSD RAM: 352×9 bits • Closed-Caption TV controller and the on-screen display controller • Closed-Caption data slicer • Four channels×6-bit AD Converter • Three channels×7-bit PWM • Two 16-bit timer/counter, 14-bit base timer • IIC-bus compliant serial interface circuit (Multi-master type) • ROM correction function • 11-source 8-vectored interrupt system Continued on next page. Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please notify us of this in advance of our receiving your program ROM code order. Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these components in an IIC system, provided that the system conforms to the IIC Standard Specification as defined by Philips. Trademarks IIC is a trademark of Philips Corporation. * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.00 N0106HKIM 20060911-S00003 No.A0120-1/21 LC86F3448B Continued from preceding page. • Integrated system clock generator and display clock generator Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators All of the above functions are fabricated on a single chip. The program is rewritable by using the on-board writing system after the LSI has been installed on the application board. The LC86F3448B change to LC863500 series by writing program data of LC863500 series into the Flash Memory Features Built-in Flash Memory 64K bytes • Program ROM • Character ROM • Rewritable in page units • Page erase / program cycle 48K bytes 16K bytes 128 bytes / page 100 cycle per page (Ta=25±2°C) Random Access Memory (RAM) 640 × 8 bits (including 128 bytes for ROM correction function) 352 × 9 bits (for CRT display) The LC86F3448B consists of 48K bytes of Program ROM space and 640 bytes of RAM space. For this microcontroller, the usable program ROM capacity and RAM capacity are the same size for the mask ROM version. Mask ROM versions compatible with the LC86F3448B Program ROM limit set for the LC86F3448B RAM limit set for the LC86F3448B (including 128 bytes for the ROM correction function) LC863448 / LC863548 49152 bytes 640 bytes LC863440 / LC863540 40960 bytes 640 bytes LC863432 / LC863532 32768 bytes 512 bytes LC863428 / LC863528 28672 bytes 512 bytes LC863424 / LC863524 24576 bytes 512 bytes LC863420 / LC863520 20480 bytes 512 bytes LC863416/ LC863516 16384 bytes 512 bytes When using on-board rewriting system is selected by the option, the rewriting program (loader program) is allocated in the last 2K-byte of the memory ,following to 46K-byte (B800h) OSD Functions • Screen display : 36 characters×16 lines (by software) • RAM : LC863400 series : 352 words (9 bits per word) Display area : 36 words×8 lines Control area : 8 words×8 lines LC863500 series : 176 words (9 bits per word) Display area : 36 words×4 lines Control area : 8 words×4 lines • Characters Up to 252 kinds of 16×32 dot character fonts (4 characters including 1 test character are not programmable) Each font can be divided into two parts and used as two fonts (Ex. 16×16 dot character font×2) At least 111 characters need to be divide between a 16×18 dot and 8×9 dot character font to display the caption fonts. • Various character attributes Character colors : 16colors (analog mode: lVp-p output ) / 8colors (digital mode) Character background colors : 16colors (analog mode: lVp-p output ) / 8colors (digital mode) Fringe / shadow colors : 16colors (analog mode: lVp-p output ) / 8colors (digital mode) Full screen colors : 16colors (analog mode: lVp-p output ) / 8colors (digital mode) Rounding Underline Italic character (slanting) • Attribute can be changed without spacing No.A0120-2/21 LC86F3448B • Vertical display start line number can be set for each row independently (Rows can be overlapped) • Horizontal display start position can be set for each row independently • Horizontal pitch (9 to 16 dots)*1 and vertical pitch (1 to 32 dots) can be set for each row independently • Different display modes can be set for each row independently Caption • Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplified graphic mode • Ten character sizes *1 Horez. × Vert. = (1×1), (1×2), (2×2), (2×4), (0.5×0.5) (1.5×1), (1.5×2), (3×2), (3×4), (0.75×0.5) • Shuttering and scrolling on each row • Simplified Graphic Display Note *1: range depends on display mode : refer to the manual for details. Data Slicer (closed caption format) • Closed caption data and XDS data extraction • NTSC/PAL, and extracted line can be specified Bus Cycle Time / Instruction-Cycle Time Bus Cycle Time Instruction Cycle Time Clock Divider System Clock Oscillation Oscillation Frequency Voltage 0.424µs 0.848µs 1/2 Internal VCO 14.156MHz 4.5V to 5.5V 7.5µs 15.0µs 1/2 Internal RC 800kHz 4.5V to 5.5V 91.55µs 183.1µs 1/1 Crystal 32.768kHz 4.5V to 5.5V 183.1µs 366.2µs 1/2 Crystal 32.768kHz 4.5V to 5.5V Ports • Input / Output Ports : LC863400 series : 4 ports (23 terminals) : LC863500 series : 4 ports (24 terminals) Data direction programmable in nibble units : 1 port (8 terminals) (If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.) Data direction programmable for each bit individually : LC863400 series : 4 ports (15 terminals) : LC863500 series : 4 ports (16 terminals) AD Converter • 4 channels×6-bit AD converters Serial Interfaces • IIC-bus compliant serial interface (Multi-master type) Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected internally. PWM Output • 3 channels×7-bit PWM Timer • Timer 0 : 16-bit timer/counter With 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with a programmable prescaler Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with a programmable prescaler Mode 3 : 16-bit counter The resolution of timer is 1 tCYC. • Timer 1 : 16-bit timer/PWM (LC863500 series only) Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : Variable bit PWM (9 to 16 bits) In mode 0/1, the resolution of Timer1/PWM is 1 tCYC In mode 2/3, the resolution is selectable by program; tCYC or 1/2 tCYC No.A0120-3/21 LC86F3448B • Base Timer Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock) Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer clock) Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler output of Timer 0 Remote Control Receiver Circuit (connected to the P73/INT3/T0IN terminal) • Noise rejection function • Polarity switching Watchdog Timer External RC circuit is required Interrupt or system reset is activated when the timer overflows ROM Correction Function Max 128 bytes / 2 addresses Interrupts • LC863400 series : 12 source 8 vectored interrupts LC863500 series : 13 source 8 vectored interrupts 1. External Interrupt INT0 2. External Interrupt INT1 3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits) 4. External Interrupt INT3, base timer 5. Timer/counter T0H (Upper 8 bits) 6. Data slicer(LC863400 series only) Timer TIH,TIL (LC863500 series only) 7. Vertical synchronous signal interrupt (VS), Scan line 8. IIC, Software • Interrupt Priority Control Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 8 listed above. For the external interrupt INT0 and INT1, low or highest priority can be set. Sub-routine Stack Level • A maximum of 128 levels (stack is built in the internal RAM) Multiplication/Division Instruction • 16 bits×8 bits (7 instruction cycle times) • 16 bits÷8 bits (7 instruction cycle times) 3 Oscillation Circuits • Built-in RC oscillation circuit used for the system clock • Built-in VCO circuit used for the system clock and OSD • X’tal oscillation circuit used for base timer, system clock and PLL reference Standby Function • HALT mode The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This mode can be released by the interrupt request or the system reset. • HOLD mode The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be released by the following conditions. - Pull the reset terminal (RES) to low level. - Feed the selected level to either P70/INT0 or P71/INT1. No.A0120-4/21 LC86F3448B Applicable Mask ROM Version • LC863448 / LC863440 / LC863432 / LC863428 / LC863424/ LC863420 / LC863416 • LC863548 / LC863540 / LC863532 / LC863528 / LC863524/ LC863520 / LC863516 Package • MFP36SDJ (Lead-free type) • DIP36S (Lead-free type) Development Tools • Evaluation chip: • Emulator: LC863096 EVA86000 (main) + ECB863400 (evaluation chip board) + POD36-CABLE (cable) + POD36-DIP (for DIP36S) or POD36-MFP (for MFP36SDJ) Write Flash Memory SANYO provides special services including writing data to Flash Memory and stamping. There is a charge for these services. Please feel free to ask our sales persons for details. Package Dimensions unit : mm (typ) 3263 15.2 0.65 7.9 19 10.5 36 1 0.8 0.3 18 0.25 0.1 (2.25) 2.45max (0.8) SANYO : MFP36SDJ(375mil) No.A0120-5/21 LC86F3448B Package Dimensions unit : mm (typ) 3170A 32.4 10.16 19 1 18 (3.25) 0.51min 3.0 3.95max 0.95 0.25 8.6 36 1.78 0.48 (1.1) SANYO : DIP36S(400mil) Pin Assignment P10/SDA0 1 36 P03 P11/SCLK0 2 35 P02 P12/SDA1 3 34 P01 P13/SCLK1 4 33 P00 VSS 5 32 P17/PWM (LC863500 only) XT1 6 31 P16/PWM3 XT2 7 30 P15/PWM2 VDD 8 29 P14/PWM1 P04/AN4 9 28 P73/INT3/T0IN P05/AN5 10 27 P72/INT2/T0IN P06/AN6 11 26 P71/INT1 P07/AN7 12 25 P70/INT0 RES 13 24 P32 FILT 14 23 P31 CVIN (LC863400 only) /P33 (LC863500 only) 15 22 BL P30 16 21 B VS 17 20 G HS 18 19 R LC86F3448B Top view SANYO: MFP36SDJ SANYO: DIP36S “Lead-free Type” “Lead-free Type” No.A0120-6/21 LC86F3448B System Block Diagram Interrupt Control IR PLA Flash memory (64K) Standby Control RC VCO Clock X’tal Generator Flash memory Control PLL A0-A15 D0-D7 CE OE WE PC IIC ROM Correct Control ACC Timer 0 XRAM B Register Timer 1 (LC863500 only) Bus Interface C Register Base Timer Port 1 ALU Port 3 ADC INT0-3 Noise Rejection Filter Port 7 PSW PWM RAR Data Slicer (LC863400 only) RAM OSD Control Circuit CGROM Stack Pointer VRAM Port 0 Watchdog Timer No.A0120-7/21 LC86F3448B Pin Description Pin Description Table Flash Memory Mode Terminal I/O Function Description Option (Parallel input/ output mode) VSS - Negative power supply XT1 I Input terminal for crystal oscillator XT2 O Output terminal for crystal oscillator VDD - Positive power supply RES I Reset terminal Input to set up mode FILT O Filter terminal for PLL CVIN I Video signal input terminal(LC863400 only) VS I Vertical synchronization signal input terminal HS Input to set up mode I Horizontal synchronization signal input terminal R O Red (R) output terminal of RGB image output G O Green (G) output terminal of RGB image output Address input A9 B O Blue (B) output terminal of RGB image output Address input A10 BL O Fast blanking control signal Address input A11 Address input A8 Switch TV image signal and caption/OSD image signal Port 0 I/O •8-bit input/output port, Input/output can be specified in nibble unit P00 to P07 •Other functions I/O A0 to A7 CMOS/Nch-OD •8-bit input/output port Input/output can be specified for each bit P10 to P17 Address input provided/not provided Output Format AD converter input port (P04 to P07) Port 1 Pull-up resistor Output Format Data input/output CMOS/Nch-OD D0 to D7 (programmable pull-up resister provided) •Other functions Port 3 I/O P30 to P33 P10 IIC0 data I/O P11 IIC0 clock output P12 IIC1 data I/O P13 IIC1 clock output P14 PWM1 output P15 PWM2 output P16 PWM3 output P17 Timer1 (PWM) output (LC863500 only) •LC863400:3-bit input/output port(P30toP32) Control signal WE LC863500: 4-bit input/output port(P30toP33) Control signal OE Control signal CE Input/output can be specified for each bit (CMOS output/input with programmable pull-up resister) Port 7 P70 P71 to P73 I/O •4-bit input/output port Address input Input or output can be specified for each bit A12 to A15 P70: I/O with programmable pull-up resister P71 to P73: CMOS output/input with programmable pull-up resister •Other functions P70 INT0 input/HOLD release input/ Nch-Tr. output for watchdog timer P71 INT1 input/HOLD release input P72 INT2 input/Timer 0 event input P73 INT3 input (noise rejection filter connected)/ Timer 0 event input Interrupt receiver format, vector addresses Rising Falling INT0 enable enable INT1 enable enable INT2 enable INT3 enable Rising/ H level L level disable enable enable 03H disable enable enable 0BH enable enable disable disable 13H enable enable disable disable 1BH Falling Vector Note: A capacitor of at least 10µF must be inserted between VDD and VSS when using this IC. No.A0120-8/21 LC86F3448B • Output form and existence of pull-up resistor for all ports can be specified for each bit. • Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1. User Options User options can be changed using Flash Memory data. A kind of option Pin, Circuits Input/output form of Port 0 input/output ports (Specified in a bit) 1. Input: Without pull-up MOS Tr. Output: N-channel open drain 2. Input: With pull-up MOS Tr. Output: CMOS Port 1 1. Input: With programmable pull-up MOS Tr. (Specified in a bit) Output: N-channel open drain 2. Input: With programmable pull-up MOS Tr. Output: CMOS Notice for Use • Input level of terminal RES at power on Terminal RES must be held low for at least 200µs after the supply voltage exceeds the power supply lower limit. Power supply VDD limit 0V 200µs or more RES • Difference between the Mask version and Flash version 1. The operation after release of reset: The mask version operates the program from the address 0 in the program counter as soon as detecting the H level on the reset port. The flash version operates the program from the address 0 in the program counter after setting the option. 2. Current dissipation : Please refer to the latest semiconductor news. • Conditions during reset and after release of reset Port options are set using Flash Memory data. Port options are set internally within approximately 3ms after logic HIGH is applied to the RESET terminal. The configuration of the port outputs change over the duration of this period. Then the Program Counter is set to 0 and program execution begins. During reset, and in the few hundred milliseconds after reset is released, the port options on certain of the ports will not yet have been set. The conditions of the various ports during reset or on release of reset have been collected in the following table. Please refer to it when analyzing circuits where these conditions apply. No.A0120-9/21 LC86F3448B Pins P0 Options Condition during and on release of reset Input: Without pull-up MOS transistor Output -off Output: N-channel open drain Input mode: High impedance Input: With pull-up MOS transistor Output-off Output: CMOS Flash version: During reset and in the first few hundred µs after reset is released, the pull-up MOS transistor is OFF. Thereafter, set to input mode with pull-up MOS Tr. ON Mask version: During reset the pull-up MOS transistor is OFF. After soon, set to input mode with pull-up MOS Tr. ON P1 Input: With programmable pull-up MOS transistor Output-off Output: N-channel open drain Input mode: High impedance Input: With programmable pull-up MOS transistor Output: CMOS P3 No options Output -off Input: With programmable pull-up MOS transistor Input mode: High impedance Output: CMOS P7 No options Output-off Input: With programmable pull-up MOS transistor Input mode: High impedance Output: With pull-up MOS (P70) CMOS (P71 to P73) On-board writing system The LC86F3448B has the On-board writing system. The program is renewable by using SANYO Flash On-board System after the LSI has been installed on the application board. This system is composed of 4 types divided by the combination of mode setting pin and communication pin. Each type system has to connect the 6 pins (VDD, VSS, RES, communication pins) with the interface board of SANYO Flash On-board System. It is necessary that the pins to be used for the rewriting system should be able to be separated from the application board properly. The system type is selected by the option setting program (Su86K.exe). types mode setting pin communication pins type1 RES pin (high voltage (12V) applied) type2 RES pin (high voltage (12V) applied) P30(DATA1), P11(DATA0), P10(CLK) type3 P30 pin (High level voltage (5V) applied) P30(ENA/DATA1), P31(DATA0), P32(CLK) type4 P30 pin (High level voltage (5V) applied) P30(ENA/DATA1), P11(DATA0), P10(CLK) P30(DATA1), P31(DATA0), P32(CLK) • Type 3 or 4 is selected : P30 is exclusive for the on-board system. This pin must always be pulled-down, so this pin can’t be used for other applications. • The loader program must be written into the ROM to use On-board writing system. The loader program should be written into the ROM before the LSI has been installed on the board by the general purpose PROM programs. When the option setting selects the this system to use, the loader program automatically links on the user program linking. Please ask to our sales persons before using On-board writing system. No.A0120-10/21 LC86F3448B Method of how to rewrite it in FLASH programmer / SANYO FLASH writing tool (SFWS) When reading or writing data to the LC86F3448B , FLASH programmer of our recommendation or SANYO FLASH writing tool (SFWS) is used. In both cases, exclusive conversion board (W86F3448D, W86F3448M) is needed. (1) FLASH programmer of our recommendation Single Word Write Manufacture Name of device Flash Support Group co. version applicable device (code) after write operation SANYO AF9708 Rev2.43 Manufacture Name of device version applicable device (code) Flash Support Group co. AF9723 + RevX.XX SANYO (the former Ando Electric) AF9833 *1 LC86F3448B (XXXX) (the former Ando Electric) Data protection setting Protected LC86F3448B (3B223) Write Multiple Words Data protection setting after write operation Protected *1: Registration is being requested. The LC86F3448B does not support a silicon signature feature. Do not use the feature (automatic device type selection) when programming this device. To avoid erasing the program, confirm the setting of the protection for activating the written program before using. It can’t be written with device code 29EE512 (2) SANYO FLASH writing tool (SFWS) PC is connected with writer unit (SKK) by USB cable and it uses it. (3) Exclusive writing conversion board • W86F3448D • • • DIP36S purpose (It is common with production discontinuance model (LC86F3448A / LC86F3548A) ) • W86F3448M • • • MFP36SDJ purpose (It is common with production discontinuance model (LC86F3448A/ LC86F3548A) ) When using the conversion board, all of the jumper SW must be set to the OFF position. If set to the ON position, read/write operations will not perform correctly. Pin 1 of the conversion board should be located as indicated below. pin 1 pin 1 chip : pin 1 Set jumper SW to OFF Set jumper SW to OFF W86F3448D W86F3448M No.A0120-11/21 LC86F3448B Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Maximum supply Symbol VDD max Pins Conditions VDD voltage Input voltage VI(1) RES , HS , VS , CVIN (LC863400 only) Ratings VDD[V] min typ unit max -0.3 +6.5 -0.3 VDD+0.3 Output voltage VO(1) R, G, B, BL, FILT -0.3 VDD+0.3 Input/output voltage VIO Ports 0, 1, 3, 7 -0.3 VDD+0.3 High Peak IOPH(1) Ports 0, 1, 3, 7 level output output current •CMOS output •For each pin. IOPH(2) R, G, B, BL current •CMOS output •For each pin. -4 -5 Total ΣIOAH(1) Ports 0, 1 The Total of all pins. output ΣIOAH(2) Ports 3, 7 The Total of all pins. -10 current ΣIOAH(3) R, G, B, BL The Total of all pins -12 Low Peak IOPL(1) Ports 0, 1, 3 For each pin. 20 level output 15 output current mA IOPL(2) Port 7 For each pin. R, G, B, BL For each pin. Total ΣIOAL(1) Ports 0, 1 The Total of all pins output ΣIOAL(2) Ports 3, 7 The Total of all pins. 30 current ΣIOAL(3) R, G, B, BL The Total of all pins. 15 Pd max MFP36SDJ Ta=-10 to +70ºC Maximum power dissipation Operating -20 IOPL(3) current 5 40 350 DIP36S -10 +70 range temperature mW 610 Topr temperature Storage V ºC Tstg -55 +125 range No.A0120-12/21 LC86F3448B Recommended Operating Range at Ta = -10°C to +70°C, VSS = 0V Parameter Symbol Operating VDD(1) supply voltage VDD(2) Pins VDD Conditions Ratings VDD[V] VHD VDD typ unit max 0.844µs ≤ tCYC ≤ 0.852µs 4.5 5.5 4µs ≤ tCYC ≤ 400µs 4.5 5.5 2.0 5.5 4.5 to 5.5 0.6VDD VDD 4.5 to 5.5 0.75VDD VDD range Hold voltage min RAMs and the registers data are kept in HOLD mode. High level input VIH(1) Port 0 Output disable voltage VIH(2) •Ports 1, 3 (Schumitt) Output disable •Port 7 (Schumitt) port input/interrupt V • HS , VS , RES (Schumitt) VIH(3) Port 70 Output disable Watchdog timer input Low level input VIL(1) Port 0 Output disable voltage VIL(2) •Ports 1, 3 (Schumitt) Output disable •Port 7 (Schumitt) port input/interrupt 4.5 to 5.5 VDD-0.5 VDD 4.5 to 5.5 VSS 0.2VDD 4.5 to 5.5 VSS 0.25VDD 4.5 to 5.5 VSS 0.6VDD • HS , VS , RES (Schumitt) VIL(3) Port 70 Output disable Watchdog timer input CVIN VCVIN Operation tCYC(1) CVIN(LC863400 only) cycle time 5.0 •All functions operating tCYC(2) 0.7Vp-p 1Vp-p 1.4Vp-p 4.5 to 5.5 0.844 0.848 0.852 4.5 to 5.5 0.844 30 4.5 to 5.5 0.844 400 4.5 to 5.5 0.4 Vp-p* •AD converter operating •OSD and Data slicer are not µs operating tCYC(3) •OSD, AD converter and Data slicer are not operating Oscillation FmRC frequency Internal RC oscillation 0.8 3.0 MHz range * Vp-p: Peak-to-peak voltage No.A0120-13/21 LC86F3448B Electrical Characteristics at Ta = -10°C to +70°C, VSS = 0V Parameter High level input Symbol IIH(1) Pins Ports 0, 1, 3, 7 current Conditions Ratings VDD[V] min typ max unit •Output disable •Pull-up MOS Tr. OFF •VIN=VDD (including the off-leak 4.5 to 5.5 1 4.5 to 5.5 1 current of the output Tr.) IIH(2) • RES •VIN=VDD • HS , VS Low level input IIL(1) Ports 0, 1, 3, 7 current µA •Output disable •Pull-up MOS Tr. OFF •VIN=VSS (including the off-leak 4.5 to 5.5 -1 4.5 to 5.5 -1 4.5 to 5.5 VDD-1 VDD-0.5 current of the output Tr.) IIL(2) • RES VIN=VSS • HS , VS High level VOH(1) output voltage •CMOS output of IOH=-1.0mA ports 0, 1, 3, 71 to 73 VOH(2) R, G, B, BL IOH=-0.1mA R. G. B: digital mode 4.5 to 5.5 Low level output VOL(1) Ports 0, 1, 3, 71 to 73 IOL=10mA 4.5 to 5.5 1.5 voltage VOL(2) Ports 0, 3, 71 to 73 IOL=1.6mA 4.5 to 5.5 0.4 4.5 to 5.5 0.4 4.5 to 5.5 0.4 VOL(3) Pull-up MOS •R, G, B, BL IOL=3.0mA •Port 1 R. G. B: digital mode VOL(4) Port 70 IOL=1mA Rpu Ports 0, 1, 3, 7 VOH=0.9VDD Tr. resistance Bus terminal RBS short circuit 4.5 to 5.5 13 V 38 80 kΩ 4.5 to 5.5 130 300 Ω 4.5 to 5.5 0.1VDD •P10 to P12 •P11 to P13 resistance (SCL0-SCL1, SDA0-SDA1) Hysteresis VHYS voltage •Ports 1, 3, 7 Output disable • RES • HS , VS Input clump VCLMP voltage Pin capacitance V CVIN 5.0 (LC863400 only) CP All pins 2.3 2.5 2.7 •f=1MHz •Every other terminals are connected to VSS. 4.5 to 5.5 10 pF •Ta=25ºC No.A0120-14/21 LC86F3448B IIC Input/Output Conditions at Ta = -10°C to +70°C, VSS = 0V Parameter Standard Symbol min High speed max min unit max SCL Frequency fSCL 0 BUS free time between stop - start tBUF 4.7 1.3 µs HOLD time of start, restart condition tHD;STA 4.0 0.6 µs L time of SCL tLOW 4.7 1.3 µs H time of SCL tHIGH 4.0 0.6 µs Set-up time of restart condition tSU;STA 4.7 0.6 HOLD time of SDA tHD;DAT 0 0 Set-up time of SDA tSU;DAT 250 Rising time of SDA, SCL tR 1000 20+0.1Cb 300 ns Falling time of SDA, SCL tF 300 20+0.1Cb 300 ns Set-up time of stop condition tSU;STO 100 0 400 µs 0.9 100 4.0 kHz µs ns µs 0.6 Refer to figure 8 Note Cb: Total capacitance of all BUS (unit : pF) Pulse Input Conditions at Ta = -10°C to +70°C, VSS = 0V Parameter Symbol Pins Ratings Conditions VDD[V] High/low level tPIH(1) •INT0, INT1 •Interrupt acceptable pulse width tPIL(1) •INT2/T0IN •Timer0-countable tPIH(2) INT3/T0IN •Interrupt acceptable tPIL(2) (1tCYC is selected for noise •Timer0-countable min 4.5 to 5.5 1 4.5 to 5.5 2 4.5 to 5.5 32 typ unit max rejection clock.) tPIH(3) INT3/T0IN •Interrupt acceptable tPIL(3) (16tCYC is selected for •Timer0-countable tCYC noise rejection clock.) tPIH(4) INT3/T0IN •Interrupt acceptable tPIL(4) (64tCYC is selected for •Timer0-countable 4.5 to 5.5 128 4.5 to 5.5 200 4.5 to 5.5 3 noise rejection clock.) tPIL(5) RES Reset acceptable tPIH(6) HS , VS •Display position controllable •The active edge of tPIL(6) HS and VS must be apart µs at least 1tCYC. •Refer to figure 4. Rising/falling tTHL time tTLH Refer to figure 4. HS 4.5 to 5.5 500 ns AD Converter Characteristics at Ta = -10°C to +70°C, VSS = 0V Parameter Symbol Resolution N Absolute ET Pins Conditions Ratings VDD[V] min typ 6 (Note) tCAD Vref selection to conversion 1 bit conversion time=2×tCYC finish Analog input VAIN AN4 to AN7 VSS voltage range Analog port IAINH VAIN=VDD input current IAINL VAIN=VSS VDD 1 -1 LSB µs 1.69 4.5 to 5.5 unit bit ±1 precision Conversion time max V µA Note Absolute precision does not include quantizing error (1/2LSB). No.A0120-15/21 LC86F3448B Analog Mode RGB Characteristics at Ta = -10°C to +70°C, VSS = 0V Parameter Symbol Pins Conditions Ratings VDD[V] min. typ. max. Analog output R.G.B Low level output 0.45 0.5 0.55 voltage Analog Intensity output 0.90 1.0 1.10 1.35 1.5 1.65 output mode Time setting R.G.B High level output 5.0 70% 50 10pf load unit V ns Sample Current Dissipation Characteristics at Ta = -10°C to +70°C, VSS = 0V The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents through the output transistors and the pull-up MOS transistors are ignored. Parameter Current dissipation Symbol IDDOP(1) Pins VDD Conditions Ratings VDD[V] min typ max unit •FmX’tal=32.768kHz during basic X’tal oscillation operation •System clock : VCO •VCO for OSD operating 4.5 to 5.5 12 24 •OSD is Digital mode •Internal RC oscillation stops IDDOP(2) VDD mA •FmX’tal=32.768kHz X’tal scillation •System clock : VCO •VCO for OSD operating 4.5 to 5.5 20 32 4.5 to 5.5 70 300 µA 4.5 to 5.5 3 7 mA 4.5 to 5.5 400 1000 •OSD is Analog mode •Internal RC oscillation stops IDDOP(3) VDD •FmX’tal=32.768kHz X’tal scillation •System clock : X’tal (Instruction cycle time: 366.2µs) •VCO for system stops •VCO for OSD stops •Internal RC oscillation stop •Data slicer, AD converters stop Current dissipation IDDHALT(1) VDD in HALT mode •HALT mode •FmX’tal=32.768kHz X’tal oscillation •System clock : VCO •VCO for OSD stops •Internal RC oscillation stops IDDHALT(2) VDD •HALT mode •FmX’tal=32.768kHz X’tal oscillation •VCO for system stops •VCO for OSD stops •System clock : Internal RC IDDHALT(3) VDD µA •HALT mode •FmX’tal=32.768kHz X’tal oscillation •VCO for system stops 4.5 to 5.5 55 200 4.5 to 5.5 0.05 20 •VCO for OSD stops •System clock : X’tal Current dissipation in HOLD mode IDDHOLD VDD •HOLD mode •All oscillation stops. µA Note 3: The currents of the output transistors and the pull-up MOS transistors are ignored. No.A0120-16/21 LC86F3448B Recommended Oscillation Circuit and Sample Characteristics The sample oscillation circuit characteristics in the table below is based on the following conditions: Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation board. Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. Recommended oscillation circuit and sample characteristics (Ta = -10°C to +70°C) Recommended circuit parameters Frequency 32.768kHz Manufacturer SEIKO EPSON Oscillator C-002RX C1 C2 Rf Rd 18pF 18pF OPEN 510kΩ Operating Oscillation supply stabilizing time voltage range 4.5 to 5.5V typ max 1.0s 1.5s Notes Notes: The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable after the following conditions. (Refer to Figure 2.) 1. The VDD becomes higher than the minimum operating voltage after the power is supplied. 2. The HOLD mode is released. The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator manufacturer with the following notes in your mind. • Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. • The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10°C to +70°C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer. • When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo sales personnel. Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. • The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as possible. • The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND. • The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit. XT1 XT2 Rf Rd C1 C2 X’tal Figure 1 Recommended Oscillation Circuit No.A0120-17/21 LC86F3448B VDD VDD limit 0V Power supply Reset time RES Internal RC resonator oscillation XT1,XT2 tmsVCO VCO for system Operation mode stable Unfixed Reset Instruction execution mode Reset Time and Oscillation Stabilizing Time HOLD release signal Valid Internal RC resonator oscillation XT1, XT2 tmsVCO VCO for system Operation mode stable HOLD Instruction execution mode HOLD release signal and oscillation stabilizing time Figure 2 Oscillation Stabilizing Time No.A0120-18/21 LC86F3448B tPIL (1)-(5) tPIH (1)-(4) Figure 3 Pulse Input Timing Condition - 1 tPIL(6) HS 0.75VDD 0.25VDD tTLH VS tPIL(6) more than ±1tCYC Figure 4 Pulse Input Timing Condition - 2 LC86F3448B 10kΩ HS HS C536 Figure 5 Recommended Interface Circuit No.A0120-19/21 LC86F3448B Noise filter 1µF C-Video CVIN 200Ω 1000pF Coupling capacitor Output impedance of C-Video before Noise filter should be less then 100Ω. Figure 6 CVIN Recommended Circuit 100Ω FILT 1MΩ + - 2.2µF 33000pF Figure 7 FILT Recommended Circuit Note: Place FILT parts on board as close to the microcontroller as possible. P S P Sr SDA tBUF tHD;STA tR tF tHD;STA tsp SCL tHIGH tLOW tHD;DAT S : start condition P : stop condition Sr : restart condition tSU;DAT tsp : spike suppression tSU;STO tSU;STA Standard mode : not exist High speed mode : less than 50ns Figure 8 IIC Timing No.A0120-20/21 LC86F3448B I≈1mA ↓ I ↓ I R≈ 500Ω ↓ PAD Figure 9 R.G.B. Analog Output Equivalent Circuit SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of November, 2006. Specifications and information herein are subject to change without notice. PS No.A0120-21/21