TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 • • • • • • • • • • • • • • • Performance Up to 8.77 MIPs • • All TMS320C1x Devices are Object Code Compatible 144/256-Word On-Chip Data RAM 1.5K/4K/8K-Word On-Chip Program ROM • 4K-Word On-Chip Program EPROM (TMS320E14/P14/E15/P15/E17/P17) • One-Time Programmable (OTP) Versions Available (TMS320P14/P15/P17) EPROM Code Protection for Copyright Security 4K / 64K-Word Total External Memory at Full Speed 32-Bit ALU/Accumulator 16 × 16-Bit Multiplier With a 32-Bit Product 0 to 16-Bit Barrel Shifter Eight Input/Output Channels Dual-Channel Serial Port Simple Memory and I/O Interface Commercial and Military Versions Available Operating Free-Air Temperature . . . 0°C to 70°C Packaging: DIP, PLCC, Quad Flatpack, and CER-QUAD CMOS Technology: Device Cycle Time — TMS320C10 . . . . . . . . . . . . . . . . . . . 200-ns — TMS320C10-14 . . . . . . . . . . . . . . . . 280-ns — TMS320C10-25 . . . . . . . . . . . . . . . . 160-ns — TMS320C14 . . . . . . . . . . . . . . . . . . . 160-ns — TMS320E14 . . . . . . . . . . . . . . . . . . . 160-ns — TMS320P14 . . . . . . . . . . . . . . . . . . . 160-ns — TMS320C15 . . . . . . . . . . . . . . . . . . . 200-ns — TMS320C15-25 . . . . . . . . . . . . . . . . 160-ns — TMS320E15 . . . . . . . . . . . . . . . . . . . 200-ns — TMS320E15-25 . . . . . . . . . . . . . . . . 160-ns — TMS320LC15 . . . . . . . . . . . . . . . . . . 250-ns — TMS320P15 . . . . . . . . . . . . . . . . . . . 200-ns — TMS320C16 . . . . . . . . . . . . . . . . . . . 114-ns — TMS320C17 . . . . . . . . . . . . . . . . . . . 200-ns — TMS320E17 . . . . . . . . . . . . . . . . . . . 200-ns — TMS320LC17 . . . . . . . . . . . . . . . . . . 278-ns — TMS320P17 . . . . . . . . . . . . . . . . . . . 200-ns 5-V and 3.3-V Versions Available (TMS320LC15/LC17) introduction The TMS32010 digital signal processor (DSP), introduced in 1983, was the first DSP in the TMS320 family. From it has evolved this TMS320C1x generation of 16-bit DSPs. All ′C1x DSPs are object code compatible with the TMS32010 DSP. The ′C1x DSPs combine the flexibility of a high-speed controller with the numerical capability of an array processor, thereby offering an inexpensive alternative to multichip bit-slice processors. The highly paralleled architecture and efficient instruction set provide speed and flexibility to produce a CMOS microprocessor generation capable of executing up to 8.77 MIPS (million instructions per second) (′C16). These ′C1x devices utilize a modified Harvard architecture to optimize speed and flexibility, implementing functions in hardware that other processors implement through microcode or software. The ′C1x generation’s powerful instruction set, inherent flexibility, high-speed number-handling capabilities, reduced power consumption, and innovative architecture have made these cost-effective DSPs the ideal solution for many telecommunications, computer, commercial, industrial, and military applications. This data sheet provides detailed design documentation for the ′C1x DSPs. It facilitates the selection of devices best suited for various user applications by providing specifications and special features for each ′C1x DSP. This data sheet is arranged as follows: introduction, quick reference table of device parameters and packages, summary overview of each device, architecture overview, and the ′C1x device instruction set summary. These are followed by data sheets for each ′C1x device providing available package styles, terminal function tables, block diagrams, and electrical and timing parameters. An index is provided to facilitate data sheet usage. Copyright 1991, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 1 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 Table 1 provides an overview of ′C1x processors with comparisons of memory, I/O, cycle timing, military support, and package types. For specific availability, contact the nearest TI Field Sales Office. Table 1. TMS320C1x Device Overview DEVICE MEMORY I/O RAM ROM EPROM PROG. SERIAL TMS320C10 (2) 144 1.5K — 4K — TMS320C10-14 144 1.5K — 4K TMS320C10-25 144 1.5K — 4K TMS320C14 (3) 256 4K — TMS320E14 (3) TMS320P14† 256 — 4K 256 — TMS320C15 (3) 256 TMS320C15-25 256 TMS320E15 (3) 256 TMS320E15-25 TMS320LC15 TMS320P15† TMS320C16 CYCLE PARALLEL PACKAGE (1) (ns) DIP PLCC CER-QUAD 8 × 16 200 40 44 — — 8 × 16 280 40 44 — — 8 × 16 160 40 44 — 4K 1 7 × 16 (4) 160 — 68 — 4K 1 7 × 16 (4) 160 — — 68 CER 4K 4K 1 7 × 16 (4) 160 — 68 — 4K — 4K — 8 × 16 200 40 44 — 4K — 4K — 8 × 16 160 40 44 — — 4K 4K — 8 × 16 200 40 — 44 CER 256 — 4K 4K — 8 × 16 160 40 — 44 CER 256 4K — 4K — 8 × 16 250 40 44 — 256 — 4K 4K — 8 × 16 200 40 44 — 256 8K — 64K — 8 × 16 114 — — 64 QFP TMS320C17 256 4K — — 2 6 × 16 (5) 200 40 44 — TMS320E17 (5) 256 — 4K — 2 6 × 16 (5) 200 40 — 44 CER TMS320LC17 (5) TMS320P17 (5)† 256 4K — — 2 6 × 16 (5) 278 40 44 — 256 — 4K — 2 6 × 16 (5) 200 40 44 † One-time programmable (OTP) device is in a windowless plastic package and cannot be erased. NOTES: 1. DIP = dual in-line package. PLCC = plastic-leaded chip carrier. CER = ceramic-leaded chip carrier. QFP = plastic quad flat pack. 2. Military version available. 3. Military versions planned; contact nearest TI Field Sales Office for availability. 4. On-chip 16-bit I/O, four capture inputs, and six compare outputs are available. 5. On-chip 16-bit coprocessor interface is optional by pin selection. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 description TMS320C10 The ′C10 provides the core CPU used in all other ′C1x devices. Its microprocessor operates at 5 MIPS. It provides a parallel I/O of 8 × 16 bits. Three versions with cycle times of 160, 200, and 280 ns are available as illustrated in Table 1. The ′C10 versions are offered in plastic 40-pin DIP or a 44-lead PLCC packages. TMS320C14/E14/P14 The ′C14/E14/P14 devices, using the ′C10 core CPU, offer expanded on-chip RAM, and ROM or EPROM (′E14/P14), 16 pins of bit selectable parallel I/O, an I/O mapped asynchronous serial port, four 16-bit timers, and external/internal interrupts. The ′C14 devices can provide for microcomputer/microprocessor operating modes. Three versions with cycle times of 160-ns are available as illustrated in Table 1. These devices are offered in 68-pin plastic PLCC or ceramic CER-QUAD packages. TMS320C15/E15/P15 The ′C15/E15/P15 devices are a version of the ′C10, offering expanded on-chip RAM, and ROM or EPROM (′E15/P15). The ′P15 is a one-time programmable (OTP), windowless EPROM version. These devices can operate in the microcomputer or microprocessor modes. Five versions are available with cycle times of 160 to 200 ns (see Table 1). These devices are offered in 40-pin DIP, 44-pin PLCC, or 44-pin ceramic packages. TMS320LC15 The ′LC15 is a low-power version of the ′C15, utilizing a VDD of only 3.3-V. This feature results in a 2.3: 1 power requirement reduction over the typical 5-V ′C1x device. It operates at a cycle time of 250 ns. The device is offered in 40-pin DIP or 44-lead PLCC packages. TMS320C16 The ′C16 offers on-chip RAM of 256-words, an expanded program memory of 64K-words, and a fast instruction cycle time of 114 ns (8.77 MIPS). It is offered in a 64-pin quad flat-pack package. TMS320C17/E17/P17 The ′C17/E17/P17 versions consist of five major functional units: the ′C15 microcomputer, a system control register, a full-duplex dual channel serial port, µ-law/A-law companding hardware, and a coprocessor port. The dual-channel serial port is capable of full-duplex serial communication and offers direct interface to two combo-codecs. The hardware companding logic can operate in either µ-law or A-law format with either sign-magnitude or twos complement numbers in either serial or parallel modes. The coprocessor port allows the ′C17/E17/P17 to act as a slave microcomputer or as a master to a peripheral microcomputer. The ′P17 utilizes a one-time programmable (OTP) windowless EPROM version of the ′E17. TMS320LC17 The ′LC17 is a low-power version of the ′C17, utilizing a VDD of only 3.3-V. This feature results in a 2.3: 1 power requirement reduction over the typical 5-V ′C1x device. It operates at a cycle time of 278 ns. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 3 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PA1/RBLE PA0/HI/LO MC RS EXINT CLKOUT X1 X2/CLKIN BIO VSS D8/LD8 D9/LD9 D10/Ld10 D11/LD11 D12/LD12 D13/LD13 D14/LD14 D15/LD15 D7/LD7 D6/LD6 A2/PA2 A3 A4 A5 A6 A7 A8 MEN DEN WE VCC A9 A10 A11 D0 D1 D2 D3 D4 D5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 TMS320C10/C15/E15/LC15/P15 FN/FZ Packages (Top View) PA2/TBLF FSR FSX FR DX1 DX0 SCLK DR1 DEN/RD WE/WR VCC DR0 XF MC/PM D0/LD0 D1/LD1 D2/LD2 D3/LD3 D4/LD4 D5/LD5 INT RS MC/MP A0/PA0 A1/PA1 V CC A2/PA2 A3 A4 A5 A6 A1/PA1 A0/PA0 MC/MP RS INT CLKOUT X1 X2/CLKIN BIO VSS D8 D9 D10 D11 D12 D13 D14 D15 D7 D6 TMS320C17/E17/LC17/P17 N/JD Packages (Top View) 6 5 4 3 2 1 44 43 42 41 40 CLKOUT X1 X2/CLKIN BIO NC VSS D8 D9 D10 D11 D12 7 8 9 10 11 12 13 14 15 16 17 NC NC A0/PA0 A1/PA1 A2/PA2 A3 A4 A5 A6 VSS A7 A8 A9 A10 A11 A12 A13 A14 NC BIO INT MC/MP V SS V DD V DD V DD V DD MEN NC IOEN MWE IOWE 64636261605958575655545352 NC RS X1 X2/CLKIN VSS VSS VSS VSS CLKOUT D15 D14 NC D13 D12 D11 D10 D9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20212223242526272829303132 D8 D7 D6 D5 NC D4 VDD D3 D2 NC D1 D0 A15 TMS320C17/E17 FN/FZ Packages (Top View) EXINT RS MC PAO/HI/LO PA1/RBLE VSS PA2/TBLF FSR FSX FR DX1 D15 D14 IOP11 IOP10 D13 D12 IOP9 IOP8 D11 D4 D5 D6 D7 IOP0 IOP1 IOP2 IOP3 IOP4 IOP5 D8 D9 RXD/DATA TXD/CLK D10 IOP6 IOP7 6 5 4 3 2 1 44 43 42 41 40 CLKOUT X1 X2/CLKIN BIO NC VSS D8 D9 D10 D11 D12 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 POST OFFICE BOX 1443 • D1/LD1 VSS D13/LD13 D14/LD14 D15/LD15 D7/LD7 D6/LD6 D5/LD5 D4/LD4 D3/LD3 D2/LD2 18 19 20 21 22 23 24 25 26 27 28 4 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TMS320C16 PG Package (Top View) A9 CMP0 CMP1 A10 A11 VCC2 VSS2 CMP2 CMP3 CAP0 CAP1 AMP4/CAP2/FSR CMP5/CAP3/FSX D0 D1 D2 D3 A1 A0 IOP15 IOP14 IOP13 IOP12 VCC1 VSS1 TCLK/CLKR TCLK2/CLKX A8 A7 A6 WE REN RS INT CLKOUT A5 A4 NMI/MC/MP WDT CLKIN A3 A2 A7 A8 MEN DEN WE VCC A9 A10 A11 D0 D1 18 19 20 21 22 23 24 25 26 27 28 TMS320C14/E14/P14 FN/FZ Packages (Top View) 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 10 59 11 58 12 57 13 56 14 55 15 54 16 53 17 52 18 51 19 50 20 49 21 48 22 47 23 46 24 45 25 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 39 38 37 36 35 34 33 32 31 30 29 V CC D13 D14 D15 D7 D6 D5 D4 D3 D2 V CC TMS320C10/C15/LC15/P15 N/JD Packages (Top View) HOUSTON, TEXAS 77001 DX0 SCLK DR1 DEN/RD WE/WR VCC DR0 XF MC/PM D0/LD0 VSS TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 architecture The ′C1x DSPs use a modified Harvard architecture for speed and flexibility. In a strict Harvard architecture, program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch and one-cycle execution. The ′C1x DSPs modification allows transfers between program and data spaces, thereby increasing the flexibility of the device. This modification permits coefficients stored in program memory to be read into the RAM, eliminating the need for a separate coefficient ROM. 32-bit accumulator All ′C1x devices contain a 32-bit ALU and accumulator for support of double-precision, twos-complement arithmetic. The ALU is a general-purpose arithmetic unit that operates on 16-bit words taken from the data RAM or derived from immediate instructions. In addition to the usual arithmetic instructions, the ALU can perform Boolean operations, providing the bit manipulation ability required of a high-speed controller. The accumulator stores the output from the ALU and is often an input to the ALU. It operates with a 32-bit word length. The accumulator is divided into a high-order word (bits 31 through 16) and a low-order word (bits 15 through 0). Instructions are provided for storing the high- and low-order accumulator words in memory. shifters Two shifters are available for manipulating data. The ALU barrel shifter performs a left-shift of 0 to 16 places on data memory words loaded into the ALU. This shifter extends the high-order bit of the data word and zero-fills the low-order bits for twos-complement arithmetic. The accumulator parallel shifter performs a left-shift of 0, 1 or 4 places on the entire accumulator and places the resulting high-order accumulator bits into data RAM. Both shifters are useful for scaling and bit extraction. 16 × 16-bit parallel multiplier The multiplier performs a 16 × 16-bit twos-complement multiplication with a 32-bit result in a single instruction cycle. The multiplier consists of three units: the T Register, P Register, and a multiplier array. The 16-bit T Register stores the multiplicand, and the P Register stores the 32-bit product. Multiplier values either come from the data memory or are derived immediately from the MPYK (multiply immediate) instruction word. The fast on-chip multiplier allows the device to perform fundamental operations such as convolution, correlation, and filtering. data and program memory Since the ′C1x devices use a Harvard type architecture, data and program memory reside in two separate spaces. These DSP devices have 144-or 256-words of on-chip data RAM and 1.5K- to 8K-words of on-chip program ROM. On-chip program EPROM of 4K-words is provided in the ′E14/E15/E17 devices. An on-chip one-time programmable 4K-word EPROM is provided in the ′P14/P15/P17 devices. The EPROM cell utilizes standard PROM programmers and is programmed identically to a 64K CMOS EPROM (TMS27C64). (Reference Table 1.) program memory expansion All ′C1x devices except the ′C17/E17/LC17/P17 devices are capable of executing from off-chip external memory at full speed for those applications requiring external program memory space. This allows for external RAM-based systems to provide multiple functionality. The ′C17/E17/LC17/P17 devices provide no external memory expansion. (Reference Table 1.) microcomputer/microprocessor operating modes All devices except the ′x17 offer two modes of operation defined by the state of the MC/MP pin: the microcomputer mode (MC/MP = 1) or the microprocessor mode (MC/MP = 0 ). In the microcomputer mode, on-chip ROM is mapped into the program memory space. In the microprocessor mode, all words of progam memory are external. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 5 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 interrupts and subroutines All devices except the ′C16 contain a four-level stack for saving the contents of the program counter during interrupts and subroutine calls. Because of the larger 64K program space, the ′C16’s hardware stack has been increased to eight levels. Instructions are available for saving the device’s complete context. PUSH and POP instructions permit a level of nesting restricted only by the amount of available RAM. The interrupts used in these devices are maskable. input/output The 16-bit parallel data bus can be utilized to perform I/O functions in two cycles. The I/O ports are addressed by the three LSBs on the address lines. In addition, a polling input for bit test and jump operations (BIO) and an interrupt pin (INT) have been incorporated for multitasking. The bit selectable I/O of the ′C14 is suitable for microcontroller applications. serial port (TMS320C17/E17) Two of the I/O ports on the ′C17/E17 are dedicated to the serial port and companding hardware. I/O port 0 is dedicated to control register 0, which controls the serial port, interrupts, and companding hardware. I/O port 1 accesses control register 1, as well as both serial port channels, and companding hardware. The six remaining I/O ports are available for external parallel interfaces. serial port (TMS320C14/E14) The ′C14/E14 devices include one I/O-mapped serial port that operates asynchronously. I/O-mapped control registers are used to configure port parameters such as inter-processor communication protocols and baud rate. companding hardware (TMS320C17/E17) On-chip hardware enables the ′C17/E17 to compand (COMpress/exPAND) data in either µ-law or A-law format. The companding logic operation is configured via the system control register. Data may be companded in either serial mode for operation on serial port data (converting between linear and logarithmic PCM) or a parallel mode for computation inside the device. The ′C17/E17 allows the hardware companding logic to operate with either sign-magnitude or twos-complement numbers. coprocessor port (TMS320C17/E17) The coprocessor port on the ′C17/E17 provides a direct connection to most microcomputers and microprocessors. The port is accessed through I/O port 5 using IN and OUT instructions. The coprocessor interface allows the device to act as a peripheral (slave) microcomputer to a microprocessor, or as a master to a peripheral microcomputer. In the microcomputer mode, the 16 data lines are used for the 6 parallel 16-bit I/O ports. In the coprocessor mode, the 16-bit parallel port is reconfigured to operate as a 16-bit latched bus interface. For peripheral transfer, an 8-bit or 16-bit length of the coprocessor port can be selected. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 instruction set A comprehensive instruction set supports both numeric-intensive operations, such as signal processing, and general-purpose operations, such as high-speed control. All of the ′C1x devices are object-code compatible and use the same 60 instructions. The instruction set consists primarily of single-cycle single-word instructions, permitting execution rates of more than six million instructions per second. Only infrequently used branch and I/O instructions are multicycle. Instructions that shift data as part of an arithmetic operation execute in a single cycle and are useful for scaling data in parallel with other operations. NOTE The BIO pin on other ′C1x devices is not available for use in the ′C14/E14/P14. An attempt to execute the BIOZ (Branch on BIO low) instruction will result in a two cycle NOP action. Three main addressing modes are available with the instruction set: direct, indirect, and immediate addressing. direct addressing In direct addressing, seven bits of the instruction word concatenated with the 1-bit data page pointer form the data memory address. This implements a paging scheme in which the first page contains 128 words, and the second page contains up to 128 words. indirect addressing Indirect addressing forms the data memory address from the least-significant eight bits of one of the two auxiliary registers, AR0-AR1. The Auxiliary Register Pointer (ARP) selects the current auxiliary register. The auxiliary registers can be automatically incremented or decremented and the ARP changed in parallel with the execution of any indirect instruction to permit single-cycle manipulation of data tables. Indirect addressing can be used with all instructions requiring data operands, except for the immediate operand instructions. immediate addressing Immediate instructions derive data from part of the instruction word rather than from the data RAM. Some useful immediate instructions are multiply immediate (MPYK), load accumulator immediate (LACK), and load auxiliary register immediate (LARK). instruction set summary Table 2 lists the symbols and abbreviations used in Table 3, the instruction set summary. Table 3 contains a short description and the opcode for each ′C1x instruction. The summary is arranged according to function and alphabetized within each functional group. Table 2. Instruction Symbols SYMBOL MEANING ACC D M K PA R S X Accumulator Data memory address field Addressing mode bit Immediate operand field 3-bit port address field 1-bit operand field specifying auxiliary register 4-bit left-shift code 3-bit accumulator left-shift field POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 7 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 Table 3. TMS320C1x Instruction Set Summary ACCUMULATOR INSTRUCTIONS OPCODE MNEMONIC NO. CYCLES DESCRIPTION NO. WORDS INSTRUCTION REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ABS Absolute value of accumulator 1 1 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 ADD Add to accumulator with shift 1 1 0 0 0 0 ADDH Add to high-order accumulator bits 1 1 0 1 1 0 0 0 0 ADDS Add to accumulator with no sign extension 1 1 0 1 1 0 0 0 0 AND AND with accumulator 1 1 0 1 1 1 1 0 0 LAC Load accumulator with shift 1 1 0 0 1 0 LACK Load accumulator immediate 1 1 0 1 1 1 1 1 1 0 OR OR with accumulator 1 1 0 1 1 1 1 0 1 0 SACH Store high-order accumulator bits with shift 1 1 0 1 0 1 1 SACL Store low-order accumulator bits 1 1 0 1 0 1 0 0 0 SUB Subtract from accumulator with shift 1 1 0 0 0 1 SUBC Conditional subtract (for divide) 1 1 0 1 1 0 0 1 SUBH Subtract from high-order accumulator bits 1 1 0 1 1 0 0 SUBS Subtract from accumulator with no sign extension 1 1 0 1 1 0 XOR Exclusive OR with accumulator 1 1 0 1 1 ZAC Zero accumulator 1 1 0 1 0 0 1 ZALH Zero accumulator and load high-order bits 1 1 0 1 ZALS Zero accumulator and load low-order bits with no sign extension 1 1 0 1 2 1 0 0 0 K 0 0 K M D 0 M D 1 M D 1 M D M D S S K M D M D 0 M D M D 0 0 M D 0 1 0 M D 0 0 1 1 M D 1 1 0 0 0 M D 1 1 1 1 1 1 1 1 0 0 1 0 1 M D 1 0 0 1 1 0 M D X S 0 0 0 1 AUXILIARY REGISTER AND DATA PAGE POINTER INSTRUCTIONS OPCODE MNEMONIC 8 DESCRIPTION NO. CYCLES NO. WORDS INSTRUCTION REGISTER 15 14 13 12 11 10 9 8 7 LAR Load auxiliary register 1 1 0 0 1 1 1 0 0 R M LARK Load auxiliary register immediate 1 1 0 1 1 1 0 0 0 R LARP Load auxiliary register pointer immediate 1 1 0 1 1 0 1 0 0 0 1 LDP Load data memory page pointer 1 1 0 1 1 0 1 1 1 1 M LDPK Load data memory page pointer immediate 1 1 0 1 1 0 1 1 1 0 0 MAR Modify auxiliary register and pointer 1 1 0 1 1 0 1 0 0 0 M D SAR Store auxiliary register 1 1 0 0 1 1 0 0 0 R M D POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 6 5 4 3 D K 0 0 0 0 D 0 0 0 0 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 Table 3. TMS320C1x Instruction Set Summary (continued) BRANCH INSTRUCTIONS OPCODE MNEMONIC NO. CYCLES DESCRIPTION NO. WORDS B Branch unconditionally 2 2 BANZ Branch on auxiliary register not zero 2 2 Branch if accumulator ≥ 0 2 BGZ Branch if accumulator > 0 2 2 BIOZ Branch on BIO = 0 † 2 2 BGEZ 2 BLEZ Branch if accumulator ≤ 0 2 2 BLZ Branch if accumulator < 0 2 2 BNZ Branch if accumulator ≠ 0 2 2 BV Branch on overflow 2 2 BZ Branch if accumulator = 0 2 2 CALA Call subroutine from accumulator 2 1 CALL RET Call subroutine immediately 2 2 2 Return from subroutine or interrupt routine 1 INSTRUCTION REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 BRANCH ADDRESS 0 1 0 0 0 0 0 0 0 BRANCH ADDRESS 1 1 0 1 0 0 0 0 0 BRANCH ADDRESS 1 1 0 0 0 0 0 0 0 BRANCH ADDRESS 0 1 1 0 1 0 1 1 0 0 0 0 0 BRANCH ADDRESS 0 0 0 0 0 BRANCH ADDRESS 1 0 1 0 0 0 0 0 0 BRANCH ADDRESS 1 1 1 0 0 0 0 0 0 BRANCH ADDRESS 0 1 0 1 0 0 0 0 0 BRANCH ADDRESS 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 BRANCH ADDRESS BRANCH ADDRESS 1 1 1 1 1 0 0 0 1 1 0 1 T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS OPCODE MNEMONIC NO. CYCLES DESCRIPTION NO. WORDS INSTRUCTION REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 APAC Add P register to accumulator 1 1 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 LT Load T Register 1 1 0 1 1 0 1 0 1 0 M D LTA LTA combines LT and APAC into one instruction 1 1 0 1 1 0 1 1 0 0 M D LTD LTD combines LT, APAC, and DMOV into one instruction 1 1 0 1 1 0 1 0 1 1 M D MPY Multiply with T register, store product in P register 1 1 0 1 1 0 1 1 0 1 M D MPYK Multiply T register with immediate operand; store product in P register 1 1 1 0 0 PAC Load accumulator from P register 1 1 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 SPAC Subtract P register from accumulator 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 K † This instruction is a NOP on the ′320C14/E14/P14. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 9 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 Table 3. TMS320C1x Instruction Set Summary (concluded) CONTROL INSTRUCTIONS OPCODE MNEMONIC DESCRIPTION NO. CYCLES NO. WORDS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 INSTRUCTION REGISTER DINT Disable interrupt EINT Enable interrupt 1 1 0 1 1 1 1 1 1 1 1 LST Load status register 1 1 0 1 1 1 1 0 1 1 M NOP No operation 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 POP POP stack to accumulator 2 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 PUSH PUSH stack from accumulator 2 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 ROVM Reset overflow mode 1 1 0 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 SOVM Set overflow mode 1 1 0 1 1 1 1 1 1 1 1 0 0 0 1 0 1 1 SST Store status register 1 1 0 1 1 1 1 1 0 0 M 2 1 0 D D I/O AND DATA MEMORY OPERATIONS OPCODE MNEMONIC NO. CYCLES DESCRIPTION NO. WORDS INSTRUCTION REGISTER 15 14 13 12 11 10 9 8 7 0 0 1 M 6 5 4 3 D DMOV Copy contents of data memory location into next higher location 1 1 0 1 1 0 1 IN Input data from port 2 1 0 1 0 0 0 PA M D OUT Output data to port 2 1 0 1 0 0 1 PA M D TBLR Table read from program memory to data RAM 3 1 0 1 1 0 0 1 1 1 M D TBLW Table write from data RAM to program memory 3 1 0 1 1 1 1 1 0 1 M D 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C10, TMS320C10-14, TMS320C10-25 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 Key Features: TMS320C10 • • • • • • GND 144-Word RAM Interrupt Data (16) 144 Words of On-Chip Data RAM 1.5K-Word ROM 1.5K Words On-Chip Program ROM 32-Bit ALU/ACC External Memory Expansion up to 4K Words at Full Speed Multiplier 16 × 16-Bit Multiplier With 32-Bit Product Address (12) Shifters 0 to 16-Bit Barrel Shifter On-Chip Clock Oscillator Device Packaging: — 40-Pin DIP — 44-Lead PLCC Single 5-V Supply Operating Free-Air Temperature Range . . . 0°C to 70°C A1/PA1 A0/PA0 MC/MP RS INT CLKOUT X1 X2/CLKIN BIO VSS D8 D9 D10 D11 D12 D13 D14 D15 D7 D6 TMS320C10 N/JD Package TMS320C10 FN/FZ Package (Top View) (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A2/PA2 A3 A4 A5 A6 A7 A8 MEN DEN WE VCC A9 A10 A11 D0 D1 D2 D3 D4 D5 INT RS MC/MP A0/PA0 A1/PA1 VSS A2/PA2 A3 A4 A5 A6 • • • +5 V Instruction Cycle Timing — 160-ns (TMS320C10-25) — 200-ns (TMS32010) — 280-ns (TMS320C10-14) 6 5 4 3 2 1 44 43 42 41 40 CLKOUT X1 X2/CLKIN BIO NC VSS D8 D9 D10 D11 D12 POST OFFICE BOX 1443 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 A7 A8 MEN DEN WE VCC A9 A10 A11 D0 D1 18 19 20 21 22 23 24 25 26 27 28 VCC D13 D14 D15 D7 D6 D5 D4 D3 D2 V CC • • HOUSTON, TEXAS 77001 11 TMS320C10, TMS320C10-14, TMS320C10-25 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 TERMINAL FUNCTIONS NAME I/O† DEFINITION A11-A0/PA2-PA0 BIO CLKOUT O I O External address bus. I/O port address multiplexed over PA2-PA0. External polling input System clock output, 1/4 crystal/CLKIN frequency D15-D0 DEN INT MC/MP I/O O I I 16-bit parallel data bus Data enable for device input data on D15-D0 External interrupt input Memory mode select pin. High selects microcomputer mode. Low selects microprocessor mode. MEN NC RS VCC O O I I Memory enable indicates that D15-D0 will accept external memory instruction. No connection Reset for initializing the device + 5 V supply VSS WE X1 X2/CLKIN I O O I Ground Write enable for device output data on D15-D0 Crystal output for internal oscillator Crystal input internal oscillator or external system clock input † Input/Output/High-impedance state. 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C10, TMS320C10-14, TMS320C10-25 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 functional block diagram X1 Program Bus 12 LSB Controller 16 12 12 PC (12) 12 12 MUX 3 A11-A0/ PA2-PA0 MUX 12 Stack 4 × 12 3 Instruction 16 MUX WE DEN MEN BIO MC/MP INT RS X2/CLKIN Address CLKOUT Program ROM/EPROM (1.5K Words) D15-D0 Program Bus 16 16 Data Bus 7 16 16 16 AR0 (16) ARP DP AR1 (16) 8 T(16) Shifter (0–16) Multiplier 8 MUX 8 P(32) 32 32 MUX Address 32 Legend: ACC ALU ARP AR0 AR1 DP P PC T 16 32 Data RAM (144 Words) ALU (32) = = = = = = = = = Accumulator Arithmetic Logic Unit Auxiliary Register Pointer Auxiliary Register 0 Auxiliary Register 1 Data Page Pointer P Register Program Counter T Register Data 32 ACC (32) 32 32 Shifter (0,1,4) 16 16 16 Data Bus POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 13 TMS320C10, TMS320C10-14, TMS320C10-25 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 electrical specifications This section contains the electrical specifications for all speed versions of the ′C10 Digital Signal Processors, including test parameter measurement information. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range VCC (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 mW Operating free-air temperature: L suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55 °C to 150 °C † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 6: All voltage values are with respect to VSS. recommended operating conditions VCC VSS VIH Supply voltage NOM MAX UNIT 4.5 5 5.25 V Supply voltage High-level input voltage VIL Low-level input voltage IOH IOL High-level output current, all outputs TA Operating free-air temperature 14 MIN 0 CLKIN 3 All remaining inputs 2 V V V MC/MP 0.6 V All remaining inputs 0.8 V Low-level output current –300 µA 2 mA L suffix 0 70 °C A suffix – 40 85 °C POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C10, TMS320C10-14, TMS320C10-25 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 electrical characteristics over specified temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage IOH = MAX IOH = 20 µA (see Note 7) VOL Low-level output voltage IOL = MAX MIN TYP† 2.4 3 0.3 VO = 2.4 V VO = 0.4 V VCC = MAX II Input current All inputs except CLKIN VCC = VSS to VCC CLKIN Ci Input capacitance Co Output capacitance – 20 Data bus Data bus 0.5 20 Off-state output current f = 1 MHz, all other pins 0 V All others UNIT V VCC – 0.4‡ IOZ All others MAX ±20 ±50 V µA µA 25‡ 15‡ pF 25‡ 10‡ pF † All typical values are at VCC = 5 V, TA = 25°C. ‡ Values derived from characterization data and not tested. NOTE 7: This voltage specification is included for interface to HC logic. However, note that all of the other timing parameters defined in this data sheet are specified for TTL logic levels and will differ for HC logic levels. INTERNAL CLOCK OPTION X1 X2/CLKIN Crystal C1 C2 Figure 1. Internal Clock Option PARAMETER MEASUREMENT INFORMATION 2.15 V RL = 825 Ω From Output Under Test Test Point CL = 100 pF Figure 2. Test Load Circuit POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 15 TMS320C10, TMS320C10-25 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 electrical characteristics over specified temperature range (unless otherwise noted) TEST CONDITIONS (SEE FIGURE 2) TYP† MAX f = 20.5 MHz, VCC = 5.5 V, TA = – 40°C to 85°C 33 55 f = 25.6 MHz, VCC = 5.5 V TA = – 0°C to 70°C 40 65 PARAMETER ICC‡ Supply current TMS320C10 TMS320C10-25 MIN UNIT mA † All typical values are at TA = 70°C and are used for thermal resistance calculations. ‡ ICC characteristics are inversely proportional to temperature. For ICC dependence on temperature, frequency, and loading. CLOCK CHARACTERISTICS AND TIMING The ′C10/C10-25 can use either its internal oscillator or an external frequency source for a clock. internal clock option The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and should be specified at a load capacitance of 20 pF. PARAMETER Crystal frequency, fx TMS320C10 TMS320C10-25 C1, C2 TEST CONDITIONS MIN TA = – 40°C to 85°C TA = 0°C to 70°C 6.7 NOM 20.5 6.7 25.6 TA = – 40°C to 85°C MAX 10 UNIT MHz pF external clock option An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left unconnected. The external frequency injected must conform to the specifications listed in the table below. switching characteristics over recommended operating conditions PARAMETER tc(C) CLKOUT cycle time§ tr(C) CLKOUT rise time tf(C) CLKOUT fall time tw(CL) tw(CH) Pulse duration, CLKOUT low TEST CONDITIONS TMS320C10 MIN NOM 195.12 RL = 825 Ω, CL = 100 pF (see Figure 2) TMS320C10-25 MAX 200 MIN NOM 156.25 MAX UNIT 160 ns 10¶ 10¶ ns 8¶ 8¶ ns 92¶ 90¶ 72¶ 70¶ ns Pulse duration, CLKOUT high td(MCC) Delay time, CLKIN↑ to CLKOUT↓ 25¶ 60¶ 25 § tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used). ¶ Values derived from characterization data and not tested. ns 50¶ ns timing requirements over recommended operating conditions TMS320C10 tc(MC) tr(MC) tf(MC) TMS320C10-25 UNIT MIN NOM MAX MIN NOM 48.78 50 150 39.06 40 MAX 150¶ Rise time, master clock input 5¶ 10¶ 5¶ 10¶ ns Fall time, master clock input 5¶ 10¶ 5¶ 10¶ ns 0.55tc(MC)¶ ns Master clock cycle time 0.4tc(MC)¶ 0.6tc(MC)¶ 0.45tc(MC)¶ ns tw(MCP) Pulse duration, master clock tw(MCL) Pulse duration, master clock low 20¶ 15¶ ns tw(MCH) Pulse duration, master clock high 20¶ 15¶ ns ¶ Values derived from characterization data and not tested. 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C10, TMS320C10-25 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions PARAMETER TMS320C10 TEST CONDITIONS MIN td1 Delay time, CLKOUT↓ to address bus valid td2 Delay time, CLKOUT↓ to MEN↓ 1/4tc(C) – 5† td3 Delay time, CLKOUT↓ to MEN↑ –10† td4 Delay time, CLKOUT↓ to DEN↓ 1/4tc(C) – 5† td5 Delay time, CLKOUT↓ to DEN↑ –10† td6 Delay time, CLKOUT↓ to WE↓ td7 Delay time, CLKOUT↓ to WE↑ td8 Delay time, CLKOUT↓ to data bus OUT valid td9 Time after CLKOUT↓ that data bus starts to be driven td10 Time after CLKOUT↓ that data bus stops being driven tv Data bus OUT valid after CLKOUT↓ th(A-WMD) Address hold time after WE↑, MEN↑, or DEN↑ (see Note 8) tsu(A-MD) Address bus setup time prior to MEN↓ or DEN↓ 10† RL = 825 Ω CL = 100 pF, (see Figure 2) 1/2tc(C) – 5† –10† TYP TMS320C10-25 MAX MIN 50 10† 1/4tc(C) + 15 15 1/4tc(C) + 15 15 1/2tc(C) + 15 15 1/4tc(C) – 5† –10† 1/4tc(C) – 5† –10† 1/2tc(C) – 5† –10† MAX 40 1/4tc(C) + 12 12 1/4tc(C) + 12 12 1/2tc(C) + 12 12 1/4tc(C) + 52† 1/4tc(C) + 65 1/4tc(C) – 5† TYP 1/4tc(C) – 5† 1/4tc(C) + 40† 1/4tc(C) – 10 –10† 1/4tc(C) – 45 –10† 1/4tc(C) – 35 ns ns ns ns ns ns ns ns ns 1/4tc(C) + 40† 1/4tc(C) – 10 UNIT ns ns ns ns † Values derived from characterization data and not tested. NOTE 8: For interfacing I/O devices, see Figure 3. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 17 TMS320C10, TMS320C10-25 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 timing requirements over recommended operating conditions TEST CONDITION tsu(D) Setup time, data bus valid prior to CLKOUT↓ th(D) Hold time, data bus held valid after CLKOUT↓ (see Note 9) RL = 825 Ω, CL = 100 pF (see Figure 2) TMS320C10 MIN NOM MAX TMS320C10-25 MIN NOM MAX UNIT 50 40 ns 0 0 ns NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓. SUGGESTED I/O DECODE CIRCUIT The circuit shown in Figure 3 is a design example for interfacing I/O devices to the ′C10/C10-25. This circuit decodes the address for output operations using the OUT instruction. The same circuit can be used to decode input and output operations if the inverter (’ALS04) is replaced with a NAND gate and both DEN and WE are connected. Inputs and outputs can be decoded at the same port provided the output of the decoder (’AS137) is gated with the appropriate signal (DEN or WE) to select read or write (using an ’ALS32). Access times can be increased when the circuit shown in Figure 3 is repeated to support IN instructions with DEN connected rather than WE. The table write (TBLW) function requires a different circuit. A detailed discussion of an example circuit for this function is described in the application report, “Interfacing External Memory to the TMS32010”, published in the book, Digital Signal Processing Applications with the TMS320 Family (SPRA012A). TMS320C10 74AS137 74ALS04 4 32 WE GL 15 Y0 Y1 PA0 PA1 PA2 2 1 1 2 40 3 A B C 14 Y2 13 Y3 12 Y4 11 Y5 10 Y6 VCC 6 5 G1 Y7 7 G2 Figure 3. I/O Decode Circuit 18 POST OFFICE BOX 1443 • 9 HOUSTON, TEXAS 77001 I/O Device TMS320C10, TMS320C10-25 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 RESET (RS) TIMING switching characteristics over recommended operating conditions PARAMETER TEST CONDITIONS td11 Delay time, DEN↑, WE↑, and MEN↑ from RS tdis(R) Data bus disable time after RS MIN TYP RL 825 Ω, CL = 100 pF, (see Figure 2) MAX 1/2tc(C) +50† 1/4tc(C) +50† UNIT ns ns † Values derived from characterization data and not tested. timing requirements over recommended operating conditions TMS320C10 PARAMETER MIN tsu(R) Reset (RS) setup time prior to CLKOUT (see Note 10) tw(R) RS pulse duration NOM TMS320C10-25 MAX MIN NOM MAX UNIT 50 40 ns 5tc(C) 5tc(C) ns NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation. INTERRUPT (INT) TIMING timing requirements over recommended operating conditions TMS320C10 MIN tf(INT) Fall time, INT tw(INT) Pulse duration, INT tsu(INT) Setup time, INT↓ before CLKOUT↓ NOM TMS320C10-25 MAX MIN NOM 15 MAX 15 UNIT ns tc(C) tc(C) ns 50 40 ns IO (BIO) TIMING timing requirements over recommended operating conditions TMS320C10 MIN tf(IO) Fall time, BIO tw(IO) Pulse duration, BIO tsu(IO) Setup time, BIO↓ before CLKOUT↓ NOM TMS320C10-25 MAX MIN 15 POST OFFICE BOX 1443 • NOM MAX 15 UNIT ns tc(C) tc(C) ns 50 40 ns HOUSTON, TEXAS 77001 19 TMS320C10-14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 electrical characteristics over specified temperature range (unless otherwise noted) PARAMETER ICC‡ TEST CONDITIONS Supply current MIN f = 14.4, MHz, VCC = 5.5 V, TA = 0°C to 70°C TYP† MAX 28 65 UNIT mA † All typical values are at TA = 70°C and are used for thermal resistance calculations. ‡ ICC characteristics are inversely proportional to temperature; i.e., ICC decreases approximately linearly with temperature. CLOCK CHARACTERISTICS AND TIMING The TMS320C10-14 can use either its internal oscillator or an external frequency source for a clock. internal clock option The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and be specified at a load capacitance of 20 pF. PARAMETER Crystal frequency, fx C1, C2 TEST CONDITIONS MIN TA = 0°C to 70°C TA = 0°C to 70°C 6.7 NOM MAX UNIT 14.4 MHz 10 pF external clock option An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left unconnected. The external frequency injected must conform to the specifications listed in the table below. switching characteristics over recommended operating conditions TEST CONDITIONS tc(C) CLKOUT cycle time§ tr(C) CLKOUT rise time tf(C) CLKOUT fall time tw(CL) tw(CH) Pulse duration, CLKOUT low td(MCC) MIN NOM MAX 277.78 RL = 825 Ω, CL = 100 pF, (see Figure 2) Pulse duration, CLKOUT high ns 10 ns 8 ns 131 ns 129 25¶ Delay time, CLKIN↑ to CLKOUT↓ UNIT ns 60¶ ns § tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used). ¶ Values derived from characterization data and not tested. timing requirements over recommended operating conditions MIN MAX UNIT 150 ns Rise time, master clock input 5¶ 10¶ ns tf(MC) Fall time, master clock input 5¶ 10¶ ns tw(MCP) Pulse duration, master clock tw(MCL) tw(MCH) tc(MC) tr(MC) Master clock cycle time ns Pulse duration, master clock low, tc(MC) = 50 ns 0.6tc(MC)¶ 20¶ Pulse duration, master clock high, tc(MC) = 50 ns 20¶ ns 0.4tc(MC)¶ ¶ Values derived from characterization data and not tested. 20 NOM 69.5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 ns TMS320C10-14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions PARAMETER TEST CONDITIONS td1 Delay time, CLKOUT↓ to address bus valid td2 Delay time, CLKOUT↓ to MEN↓ td3 Delay time, CLKOUT↓ to MEN↑ td4 Delay time, CLKOUT↓ to DEN↓ td5 Delay time, CLKOUT↓ to DEN↑ td6 Delay time, CLKOUT↓ to WE↓ td7 Delay time, CLKOUT↓ to WE↑ td8 Delay time, CLKOUT↓ to data bus OUT valid RL = 825 Ω, CL = 100 pF (see Figure 2) td9 Time after CLKOUT↓ that data bus starts to be driven td10 Time after CLKOUT↓ that data bus stops being driven tv Data bus OUT valid after CLKOUT↓ th(A-WMD) Address hold time after WE↑, MEN↑, or DEN↑ (see Note 8) tsu(A-MD) Address bus setup time prior to MEN↓ or DEN↓ MIN 10† NOM MAX UNIT 50 ns 1/4tc(C) – 5† –10† 1/4tc(C) +15 1/4tc(C) – 5† –10† 1/4tc(C) +15 1/2tc(C) – 5† –10† 1/2tc(C) +15 15 15 15 1/4tc(C) + 65 1/4tc(C) – 5† ns ns ns ns ns ns ns ns 1/4tc(C) + 40† 1/4tc(C) – 10 ns ns –10† ns 1/4tc(C) – 45 ns † Values derived from characterization data and not tested. NOTE 8: For interfacing I/O devices, see Figure 3. timing requirements over recommended operating conditions TEST CONDITIONS tsu(D) Setup time, data bus valid prior to CLKOUT↓ th(D) Hold time, data bus held valid after CLKOUT↓ (see Note 9) RL = 825 Ω, CL = 100 pF (see Figure 2) MIN NOM MAX UNIT 50 ns 0 ns NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 21 TMS320C10-14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 RESET (RS) TIMING switching characteristics over recommended operating conditions PARAMETER TEST CONDITIONS td11 Delay time, DEN↑, WE↑, and MEN↑ from RS tdis(R) Data bus disable time after RS MIN RL = 825 Ω, CL = 100 pF (see Figure 2) TYP MAX UNIT 1/2tc(C) + 50† ns 1/4tc(C) + 50† ns † Values were derived from characterization data and not tested. timing requirements over recommended operating conditions MIN tsu(R) Reset (RS) setup time prior to CLKOUT (see Note 10) tw(R) RS pulse duration NOM MAX 50 UNIT ns 5tc(C) ns NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation. INTERRUPT (INT) TIMING timing requirements over recommended operating conditions MIN tf(INT) Fall time, INT tw(INT) Pulse duration, INT tsu(INT) Setup time, INT↓ before CLKOUT↓ NOM MAX 15 UNIT ns tc(C) ns 50 ns IO (BIO) TIMING timing requirements over recommended operating conditions MIN tf(IO) Fall time, BIO tw(IO) Pulse duration, BIO tsu(IO) Setup time, BIO↓ before CLKOUT↓ 22 NOM MAX 15 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 UNIT ns tc(C) ns 50 ns TMS320C10, TMS320C10-14, TMS320C10-25 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 TIMING DIAGRAMS Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2 volts, unless otherwise noted. clock timing tr(MC) tw(MCH) tw(MCP)† tc(MC) X2/CLKIN tw(MCL) tf(MC) tw(CH) td(MCC)† CLKOUT tr(C) tf(C) tw(CL) tc(C) † td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform. memory read timing tc(C) CLKOUT td2 td3 MEN td1 A11-A0 tsu(A-MD) th(A-WMD) Address Bus Valid tsu(D) th(D) Instruction Valid D15-D0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 23 TMS320C10, TMS320C10-14, TMS320C10-25 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 TBLR instruction timing CLKOUT td2 td3 MEN 1 2 td3 3 4 7 8 td1 A11-A0 5 6 th(D) tsu(D) 9 D15-D0 10 11 12 Legend: 1. 2. 3. 4. 5. 6. TBLR Instruction Prefetch Dummy Prefetch Data Fetch Next Instruction Prefetch Address Bus Valid Address Bus Valid 7. 8. 9. 10. 11. 12. Address Bus Valid Address Bus Valid Instruction Valid Instruction Valid Data Input Valid Instruction Valid TBLW instruction timing CLKOUT MEN A11-A0 1 2 4 5 3 6 7 td7 td6 WE td8 td9 D15-D0 8 9 Legend: 1. 2. 3. 4. 5. 6. 24 TBLW Instruction Prefetch Dummy Prefetch Next Instruction Prefetch Address Bus Valid Address Bus Valid Address Bus Valid 7. 8. 9. 10. 11. Address Bus Valid Instruction Valid Instruction Valid Data Output Valid Instruction Valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 td10 tv 10 11 TMS320C10, TMS320C10-14, TMS320C10-25 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 IN instruction timing CLKOUT MEN 1 2 tsu(A-MD) 3 A11-A0 tsu(D) 4 5 td5 td4 DEN th(D) 6 D15-D0 7 8 Legend: 1. 2. 3. 4. IN Instruction Prefetch Next Instruction Prefetch Address Bus Valid Peripheral Address Valid 5. 6. 7. 8. Address Bus Valid Instruction Valid Data Input Valid Instruction Valid OUT instruction timing CLKOUT MEN 1 A11-A0 3 2 4 5 td6 td7 td9 WE td8 D15-D0 tv 6 td10 7 8 Legend: 1. 2. 3. 4. OUT Instruction Prefetch Next Instruction Prefetch Address Bus Valid Peripheral Address Valid 5. 6. 7. 8. Address Bus Valid Instruction Valid Data Output Valid Instruction Valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 25 TMS320C10, TMS320C10-14, TMS320C10-25 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 reset timing CLKOUT tsu(R) tsu(R) RS tw(R) DEN WE MEN (see Note E) tdis(R) Data Out D15-D0 Data In From PC ADDR 0 td11 Data In From PC ADDR PC+1 Data Shown Relative to WE MEN AB = PC+1 AB = Address Bus Address Bus AB = PC AB = PC = 0 AB = PC+1 NOTES: A. RS forces DEN, WE, and MEN high and places data bus D0 through D15 in a high-impedance state. AB outputs (and program counter) are synchronously cleared to zero after the next complete CLK cycle from RS↓. B. RS must be maintained for a minimum of five clock cycles. C. Resumption of normal program will commence after one complete CLK cycle from RS↑. D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK cycle. E. Diagram shown is for definition purpose only. DEN, WE, and MEN are mutually exclusive. F. During a write cycle, RS may produce an invalid write address. interrupt timing CLKOUT tsu(INT) INT tf(INT) tw(INT) BIO timing CLKOUT tsu(IO) BIO tf(IO) tw(IO) 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C10, TMS320C10-14, TMS320C10-25 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 TYPICAL POWER VS. FREQUENCY GRAPHS 52 TA = – 40°C TA = 85°C I CC - Supply Current - mA 46 VCC = 5.5 V TA = – 40°C VCC = 5.0 V 40 TA = 85°C VCC = 4.5 V TA = – 40°C 34 TA = 85°C 28 22 16 10 1.2 4 8 12 16 20 24 28 24 28 fx - Crystal Frequency - MHz (a) – 40°C to 85°C Temperature Range 42 I CC - Supply Current - mA 36 30 With Load 24 18 Without Load 12 6 0 1.2 4 8 12 16 20 fx - Crystal Frequency - MHz (b) Voltage = 5 V; Temperature = 25°C Figure 4. Typical CMOS ICC vs Frequency POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 27 TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 Key Features: TMS320C14/E14/P14 • • • • • • • • • • • • • • 256 Words of On-Chip Data RAM 4K Words of On-Chip Program ROM (TMS320C14) 4K Words of On-Chip Program EPROM (TMS320E14/P14) 256-Word RAM Interrupt Data (16) 8K-Word ROM/ EPROM 32-Bit ALU/ACC One-Time Programmable (OTP) Windowless EPROM Version Available (′320P14) EPROM Code Protection for Copyright Security Multiplier Address (12) Shifters External Memory Expansion up to 4K-Words at Full Speed (Microprocessor Mode) 16 × 16-Bit Multipler With 32-Bit Product 0 to 16-Bit Barrel Shifter Seven Input and Seven Output External Ports Bit Selectable I/O Port (16 Pins) TMS320C14, TMS320E14/P14 FN/FZ Packages (Top View) 16-Bit Bidirectional Data Bus With Greater than 50-Mbps Transfer Rate Asynchronous Serial Port 15 Internal/External Interrupts Event Manager With Capture Inputs and Compare Outputs Four Independent Timers [Watchdog, General Purpose (2), Serial Port] Four-Level Hardware Stack TCLK/CLKR TCLK2/CLKX A8 A7 A6 WE REN RS INT CLKOUT A5 A4 NMI/MC/MP WDT CLKIN A3 A2 Packaging: 68-Pin PLCC (FN Suffix) or CLCC (FZ Suffix) Single 5-V Supply Operating Free-Air Temperature . . . 0°C to 70°C 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A1 A0 IOP15 IOP14 IOP13 IOP12 • • 160-ns Instruction Cycle 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 VCC1 VSS1 D15 D14 IOP11 IOP10 D13 D12 IOP9 IOP8 D11 • GND A9 CMP0 CMP1 A10 A11 VCC2 VSS2 CMP2 CMP3 CAP0 CAP1 AMP4/CAP2/FSR CMP5/CAP3/FSX D0 D1 D2 D3 • • • +5 V D4 D5 D6 D7 IOP0 IOP1 IOP2 IOP3 IOP4 IOP5 D8 D9 RXD/DATA TXD/CLK D10 IOP6 IOP7 TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 introduction The ′C14/E14/P14 are 16/32-bit single-chip digital signal processing (DSP) microcontrollers that combine the high performance of a DSP with on-chip peripherals. With a 160-ns instruction cycle, these devices are capable of executing up to 6.4 million instructions per second (MIPS). The ′C14/E14/P14 DSPs are ideal for applications such as automotive control systems, computer peripherals, industrial controls, and military command/control system applications. Control-specific on-chip peripherals include: An event manager with 6 channel PWM D/A/, 6-bit I/O pins, an asynchronous serial port, four 16-bit timers, and internal/external interrupts. With 4K-words of on-chip ROM, the ′C14 is a mask programmable device. Code is provided by the customer, and TI incorporates the customer’s code into the photomask. It is offered in a 68-pin plastic chip carrier package (FN suffix), rated for operation from 0°C to 70°C. The ′E14 is provided with a 4K-word on-chip EPROM. This EPROM version is excellent for prototyping and for customized applications. It is programmable with standard EPROM programmers. It is offered in a 68-pin (windowed) cerquad package (FZ suffix), rated for operation from 0°C to 70°C. The ′P14 features a one-time programmable 4K-word on-chip EPROM. The ′P14 is provided in an unprogrammed state and is programmed as if it were a blank ′E14. It is offered in a low-cost, volume-production-oriented, 68-pin plastic leaded chip carrier (PLCC) package (FN suffix), rated for operation from 0°C to 70°C. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 29 TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 Each device can execute programs form either internal (MC/MP=0) or external program memory (MC/MP=1). For proprietary code security, the ′E14 and ′P14 incorporate an EPROM protect bit (RBIT). If this bit is programmed, the device’s internal program memory cannot be accessed by any external means. TERMINAL FUNCTIONS PIN NAME A11 A10 A9 5 6 9 A8 A7 A6 A5 12 13 14 20 A4 A3 A2/PA2 A1/PA1 21 25 26 27 A0/PA0 28 D15 MSB D14 D13 35 36 39 D12 D11 D10 D9 40 43 46 49 D8 D7 D6 D5 50 57 58 59 D4 D3 D2 D1 60 61 62 63 D0 LSB DESCRIPTION I/O/Z† NO. ADDRESS/DATA BUSES O/Z Program memory address bus A11 (MSB) through A0 (LSB) and port addresses PA2 (MSB) through PA0 (LSB). Addresses A11 through A0 are always active and never go to high impedance except during reset. During execution of the IN and OUT instructions, pins 26, 27, and 28 carry the port addresses. Pins A3 through A11 are held high when port accesses are made on pins PA0 through PA2. I/O/Z Parallel data bus D15 (MSB) through D0 (LSB). The data bus is always in the high-impedance state except when WE is active (low). The data bus is also active when internal peripherals are written to. 64 INTERRUPT AND MISCELLANEOUS SIGNALS INT 18 I External interrupt input. The interrupt signal is generated by a high-to-low transition on this pin. NMI/MC/MP 22 I Non-maskable interrupt. When this pin is brought low, the device is interrupted irrespective of the state of the INTM bit in status register ST. Microcomputer/microprocessor select. This pin is also sampled when RS is low. If high during reset, internal program memory is selected. If low during reset, external memory will be selected. WE 15 O Write enable. When active low, WE indicates that device will output data on the bus. REN 16 O Read enable. When active low, REN indicates that device will accept data from the bus. RS 17 I Reset. When this pin is low, the device is reset and PC is set to zero. Continued next page. † Input/Output/High-impedance state. 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C10-14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 TERMINAL FUNCTIONS (concluded) PIN NAME DESCRIPTION I/O/Z† NO. CLKOUT SUPPLY/OSCILLATOR SIGNALS 19 O System clock output (one fourth CLKIN frequency). 4,33 I 5-V supply pins. 3,34 I Ground pins. CLKIN 24 I Master clock input from external clock source. RXD 48 I Asynchronous mode receive input. TXD 47 O/Z TCLK1 10 I Timer 1 clock. If external clock is selected, it serves as clock input to Timer 1. TCLK2 11 I Timer 2 clock. If external clock is selected, it serves as clock input to Timer 2. WDT 23 O Watchdog timer output. An active low is generated on this pin when the watchdog timer times out. VCC VSS SERIAL PORT AND TIMER SIGNALS Asynchronous mode transmit output. BIT I/O PINS IOP15 IOP14 IOP13 MSB 29 30 31 IOP12 IOP11 IOP10 IOP9 32 37 38 41 IOP8 IOP7 IOP6 IOP5 42 44 45 51 IOP4 IOP3 IOP2 IOP1 52 53 54 55 IOP0 LSB I/O 16 bit I/O lines that can be individually configured as inputs or outputs and also individually set or reset when configured as outputs. O Compare outputs. The states of these pins are determined by the combination of compare and action registers. Capture inputs. A transition on these pins causes the timer register to be captured in FIFO stack. 56 COMPARE AND CAPTURE SIGNALS CMP0 CMP1 CMP2 CMP3 8 7 2 CAP0 CAP1 68 67 I CMP4/CAP2 66 I/O This pin can be configured as compare output or capture input. CMP5/CAP3 65 I/O This pin can be configured as compare output or capture input. 1 † Input/Output/High-impedance state. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 31 TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 functional block diagram CLKIN CLKOUT 12 LSB 16 Controller WE REN RS 12 MUX 16 Watchdog Timer 12 PC (12) MUX A0-A11 PA0-PA2 12 Program ROM/EPROM (4K Words) Interrupt Controller BSR 16 16 D15-D0 16 16 16 Data Bus 16 16 ARP TCLK1.2 16 16 Program Bus NMI/ MC/MP INT Timers 1.2 16 MUX Stack 4 × 12 3 Instruction Address 12 12 WDT 7 1 16 DP AR1 (16) 16 Multiplier 8 8 16 P(32) CMP4, 5 / CAP2, 3 4 × 16 FIFO Stack (4) 4 CAP Detect (4) CAP0,1 16 MUX 32 32 Shifter (0–16) 8 CMP0-CMP3 ACT (6) 16 T(16) AR0 (16) CMPR (6) 16 6 MUX 32 16 32 Address Serial Port Timer 9 TBR TSR RBR RSR 9 ALU (32) Data (256 Words) Serial Port Controller TXD RXD 32 Data IOP ACC (32) 32 32 Shifter (0,1,4) 16 IOP0-IOP15 16 16 Data Bus Legend: ACC = Accumulator ACT = Action Register ALU = Arithmetic Logic Unit ARP = Auxiliary Register Point AR0 = Auxiliary Register 0 AR1 = Auxiliary Register 1 BSR = Bank Select Register CAP = Capture CMPR = Compare Register DP = Data Page Pointer IOP = Input/Output Port (Bit Selectable) PC = Program Counter P = P Register RBR = Receive Buffer Register RSR = Receive Shift Register T = T Register TBR = Transmit Buffer Register TSR = Transmit Shift Register architecture The ′C1x family utilizes a modified Harvard architecture for speed and flexibility. In a strict Harvard architecture, program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch and execution. The ′C1x family’s modification of a Harvard architecture allows transfers between program and data spaces, thereby increasing the flexibility of the device. This modification permits coefficients stored in program memory to be read into the RAM, eliminating the need for a separate coefficient ROM. It also makes available immediate instructions and subroutines based on computed values. 32-bit ALU/accumulator The ′C14/E14/P14 devices contain a 32-bit ALU and accumulator for support of double-precision, twos-complement arithmetic. The ALU is a general-purpose arithmetic unit that operates on 16-bit words taken from the data RAM or derived from immediate instructions. In addition to the usual arithmetic instructions, the ALU can perform Boolean operations, providing the bit manipulation ability required of a high-speed controller. 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 The accumulator stores the output from the ALU and is often an input to the ALU. It operates with a 32-bit wordlength. The accumulator is divided into a high-order word (bits 31 through 16) and a low-order word (bits 15 through 0). Instructions are provided for storing the high- and low- order accumulator words in memory. shifters Two shifters are available for manipulating data. The ALU barrel shifter performs a left-shift of 0 to16 places on data memory words loaded into the ALU. This shifter extends the high-order bit of the data word and zero-fills the low-order bits for twos-complement arithmetic. The accumulator parallel shifter performs a left-shift of 0, 1, or 4 places on the entire accumulator and places the resulting high-order accumulator bits into data RAM. Both shifters are useful for scaling and bit extraction 16 × 16-bit parallel multiplier The multiplier performs a 16 × 16-bit twos-complement multiplication with a 32-bit result in a single instruction cycle. The multiplier consists of three units: the T Register, P Register, and the multiplier array. The 16-bit T Register temporarily stores the multiplicand; the P Register stores the 32-bit product. Multiplier values either come from the data memory or are derived immediately from the MPYK (multiply immediate) instruction word. The fast on-chip multiplier allows the device to perform fundamental operations such as convolution, correlation, and filtering. data and program memory Since the ′C14/E14/P14 devices use a Harvard architecture, data and program memory reside in two separate spaces. These devices have 256 words of on-chip data RAM and 4K words of on-chip program ROM (′C14) or EPROM (′E14 and the OTP ′P14). The EPROM cell utilizes standard PROM programmers and is programmed identically to a 64K-bit CMOS EPROM (TMS27C64). program memory expansion The ′C1x devices are capable of executing up to 4K words of external memory at full speed for those applications requiring external program memory space. This allows for external RAM-based systems to provide multiple functionality. microcomputer/microprocessor operating modes The ′C14/E14/P14 devices offer two modes of operation defined by the state of the NMI/MC/MP pin during reset: the microcomputer mode (NMI/MC/MP is high) or the microprocessor mode (NMI/MC/MP is low). In the microcomputer mode, the on-chip ROM is mapped into the program memory space. In the microprocessor mode, all 4K words of memory are external. interrupts and subroutines The ′C14/E14/P14 devices contain a four-level hardware stack for saving the contents of the program counter during interrupts and subroutine calls. Instructions are available for saving the complete context of the device. PUSH and POP instructions permit a level of nesting restricted only by the amount of available RAM. The ′C14/E14/P14 have a total of 15 internal/external interrupts. Fourteen of these are maskable; NMI is the fifteenth. input/output The 16-bit parallel data bus can be utilized to access external peripherals. However, only the lower three address lines are active. The upper nine address lines are driven high. bit I/O The ′C14/E14/P14 has 16 pins of bit I/O that can be individually configured as inputs or outputs. Each of the pins can be set or cleared without affecting the others. The input pins can also detect and match patterns and generate a maskable interrupt signal to the CPU. serial port The ′C14/E14/P14 includes an I/O-mapped asynchronous serial port. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 33 TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 event manager An event manager is included that provides up to four capture inputs and up to six compare outputs. This peripheral operates with the timers to provide a form of programmable event logging/detection. The six compare outputs can also be configured to produce six channels of high precision PWM. timers 1 and 2 Two identical 16-bit timers are provided for general purpose applications. Both timers include a 16-bit period register and buffer latch, and can generate a maskable interrupt. serial port timer The serial port timer is a 16-bit timer primarily intended for baud rate generation for the serial port. Its architecture is the same as timers 1 and 2, therefore it can serve as a general purpose timer if not needed for serial communication. watchdog timer The ′C14/E14/P14 contain a 16-bit watchdog timer that can produce a timeout (WDT) signal for various applications such as software development and event monitoring. The watchdog timer also generates, at the point of the timeout, a maskable interrupt signal to the CPU. instruction set A comprehensive instruction set supports both numeric-intensive operations, such as signal processing, and general-purpose operations, such as high-speed control. All of the first-generation devices are object-code compatible and use the same 60 instructions. The instruction set consists primarily of single-cycle single-word instructions, permitting execution rates of more than six million instructions per second. Only infrequently used branch and I/O instructions are multicycle. Instructions that shift data as part of an arithmetic operation execute in a single cycle and are useful for scaling data in parallel with other operations. NOTE The BIO pin on other ′C1x devices is not available for use in the ′C14/E14/P14 devices. An attempt to execute the BIOZ (Branch on BIO low) instruction will result in a two cycle NOP action. Three main addressing modes are available with the instruction set: direct, indirect, and immediate addressing. direct addressing In direct addressing, seven bits of the instruction word concatenated with the 1-bit data page pointer from the data memory address. This implements a paging scheme in which each page contains 128 words. indirect addressing Indirect addressing forms the data memory address from the least-significant eight bits of one of the two auxiliary registers, AR0 and AR1. The Auxiliary Register Pointer (ARP) selects the current auxiliary register. The auxiliary registers can be automatically incremented or decremented and the ARP changed in parallel with the execution of any indirect instruction to permit single-cycle manipulation of data tables. Indirect addressing can be used with all instructions requiring data operands, except for the immediate operand instructions. immediate addressing Immediate instructions derive data from part of the instruction word rather than from part of the data RAM. Some useful immediate instructions are multiply immediate (MPYK), load accumulator immediate (LACK), and load auxiliary register immediate (LARK). 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 electrical specifications This section contains all the electrical specifications for the ′C14/E14/P14 devices, including test parameter measurement information. Parameters with PP subscripts apply only to the ′E14 and ′P14 in the EPROM programming mode. absolute maximum ratings over specified temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Supply voltage range, VPP (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 14 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 W Air temperature range above operating device: L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 °C to 70 °C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55 °C + 150 °C † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 6: All voltage values are with respect to VSS. recommended operating conditions VCC Supply voltage MIN NOM MAX UNIT Operating voltage 4.75 5 5.25 V Fast programming 5.75 6 6.25 V SNAP! Pulse programming 6.25 6.5 6.75 V VPP VPP Supply voltage for Fast programming (see Note 11) 12.25 12.5 12.75 V Supply voltage for SNAP! Pulse programming (see Note 11) 12.75 13 13.25 V VSS Supply voltage VIH High-level input voltage VIL IOH Low-level input voltage, all inputs 0.8 V High-level output current, all outputs – 300 µA IOL TA Low-level output current, all outputs 2 mA °C 0 CLKIN, CAP0, CAP1, CMP4/CAP2, CMP5/CAP3, RS 3 All remaining inputs 2 Operating free-air temperature 0 V V 70 NOTE 11: VPP can be applied only to programming pins designed to accept VPP as an input. During programming the total supply current is IPP + ICC. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 35 TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 electrical characteristics over specified temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage IOH = MAX IOH = 20 µA (see Note 7) VOL Low-level output voltage IOL = MAX MIN TYP† 2.4 3 0.3 – 20 All other inputs except CLKIN ± 20 CLKIN ± 50 II Input current VI = VSS to VCC ICC § IPP1 Supply current f = 25.6 MHz, VCC = 5.25 V, TA = 0°C to 70°C VPP = VCC = 5.5 V IPP2 VPP supply current VPP supply current (during program pulse) CI Input capacitance 70 VPP = 13 V 30 Data bus All others Data bus 0.5 20 VCC = MAX Output capacitance V VO = 2.4 V VO = 0.4 V Off-state output voltage f = 1 MHz, All other pins 0 V All others UNIT V VCC – 0.4† IOZ CO MAX V µA µA 90 mA 100 µA 50 mA 25‡ 15‡ pF 25‡ 10‡ pF † All typical values are at VCC = 5 V, TA = 25°C, except ICC at 70°C. ‡ Values derived from characterization data and not tested. § ICC characteristics are inversely proportional to temperature. NOTE 7: This voltage specification is included for interface to HC logic. However, note that all of the other timing parameters defined in this data sheet are specified for TTL logic levels and will differ for HC logic levels. PARAMETER MEASUREMENT INFORMATION 2.15 V RL = 825 Ω From Output Under Test Test Point CL = 100 pF Figure 5. Test Load Circuit EXTERNAL CLOCK REQUIREMENTS The TMS320C14/E14/P14 use an external frequency source for a clock. This source is applied to the CLKIN pin, and must conform to the specifications in the table below. PARAMETERS CLKIN 36 Input clock frequency POST OFFICE BOX 1443 • TEST CONDITIONS MIN TA = 0°C to 70°C 6.7 HOUSTON, TEXAS 77001 NOM MAX UNIT 25.6 MHz TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 CLOCK TIMING switching characteristics over recommended operating conditions PARAMETER tc(C) CLKOUT cycle time ‡ tr(C) CLKOUT rise time tf(C) TEST CONDITIONS MIN NOM 156.25 600 RL = 825 Ω, CL = 100 pF, (see Figure 2) CLKOUT fall time MAX UNIT ns 10† ns 8† ns 72† ns tw(CL) Pulse duration, CLKOUT low tw(CH) Pulse duration, CLKOUT high 70† ns Delay time CLKIN↑ to CLKOUT↓ 45† ns td(MCC) † Values were derived from characterization data and not tested. timing requirements over recommended operating conditions tc(MC) Master clock cycle time ‡ tr(MC) Rise time, master clock input tf(MC) Fall time, master clock input MIN NOM MAX 39.06 40 150 ns 5† 10† ns 5† 10† ns 0.55tc(MC)† ns 0.45tc(MC)† UNIT tw(MCP) Pulse duration, master clock tw(MCL) Pulse duration, master clock low 15† 130 ns tw(MCH) Pulse duration, master clock high 15† 130 ns † Values were derived from characterization data and not tested. ‡ tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 37 TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 MEMORY READ AND INSTRUCTION TIMING switching characteristics over recommended operating conditions TEST CONDITIONS PARAMETER MIN NOM MAX UNIT tsu(A)R Address bus valid before REN↓ 0.25 tc(C) – 39 ns tsu(A)W Address bus valid before WE↓ 0.50 tc(C) – 45 ns th(A) Address bus valid after REN↑ or WE↑ ten(D)W Data starts being driven before WE↓ tsu(D)W Data valid prior to WE↓ th(D)W Data valid after WE↑ tdis(D)W Data in high impedance after WE↑ tw(WEL) WE-low duration 0.50 tc(C) – 15 ns tw(RENL) REN-low duration 0.75 tc(C) – 15 ns trec(WE) Write recovery time, time between WE↑ and REN↓ 0.25 tc(C) – 5 ns trec(REN) Read recovery time, time between REN↑ and WE↓ 0.50 tc(C) – 10 ns 0.50 tc(C) – 15 ns 5† ns 0.25 tc(C)† RL = 825 Ω, CL = 100 pF, (see Figure 2) 0.25 tc(C) – 45 ns 0.25 tc(C) – 10 ns 0.25 tc(C) + 25† td(WE-CLK) Time from WE↑ to CLKOUT↑ ns ns † Values were derived from characterization data and not tested. timing requirements over recommended operating conditions TEST CONDITIONS tsu(D)R Data set-up prior to REN↑ th(D)R Data hold after REN↑ ta(A) Access time for read cycle data valid after valid address toe(REN) Access time for read cycle from REN↓ tdis(D)R Data in high impedance after REN↑ MIN NOM MAX UNIT 52 ns 0 ns RL = 825 Ω, CL = 100 pF, (see Figure 2) tc(C) – 90 ns 0.75 tc(C) – 60 ns 0.25 tc(C)† ns RESET (RS) TIMING switching characteristics over recommended operating conditions PARAMETER TEST CONDITIONS td(RS-RW) Delay from RS↓ to REN↑ and WE↑ tdis(RS-RW) Delay from RS↓ to REN and WE into high impedance tdis(RS-DB) Data bus disable after RS↓ tdis(RS-AB) Address bus disable after RS↓ ten(RS-AB) Address bus enable after RS↑ MIN NOM MAX UNIT 0.75 tc(C) + 20† ns 1.25 tc(C)† ns 1.25 tc(C)† ns tc(C)† tc(C)† ns RL = 825 Ω, CL = 100 pF, (see Figure 2) ns timing requirements over recommended operating conditions TEST CONDITIONS tsu(RS) RS setup prior to CLKOUT↓ (see Note 10) tw(RS) RS pulse duration RL = 825 Ω, CL = 100 pF, (see Figure 2) MIN POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 MAX UNIT 60 ns 5tc(C) ns NOTE 10: RS can occur anytime during the clock cycle. Time given is minimum to ensure synchronous operation. 38 NOM TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 MICROCOMPUTER/MICROPROCESSOR MODE (NMI/MC/MP) timing requirements over recommended operating conditions MIN th(MC/MP)‡ Hold time after RS high NOM MAX tc(C) UNIT ns † Values were derived from characterization data and not tested. ‡ Hold time to put device in microprocessor mode. INTERRUPT (INT)/NONMASKABLE INTERRUPT (NMI) timing requirements over recommended operating conditions MAX 15† UNIT Fall time, INT MIN tf(NMI) Fall time, NMI 15† ns tw(INT) Pulse duration, INT tc(C) ns tw(NMI) Pulse duration, NMI tc(C) ns tsu(INT) Setup time, INT before CLKOUT low (see Note 12) 60 ns tsu(NMI) Setup time, NMI before CLKOUT low (see Note 12) 60 ns tf(INT) NOM ns NOTE 12: INT and NMI are synchronous inputs and can occur at any time during the cycle. NMI and INT are edge triggered only. BIT I/O TIMING switching characteristics over recommended operating conditions PARAMETER trfo(IOP) Rise and fall time outputs td(IOP) CLKOUT low to data valid outputs TEST CONDITIONS MIN NOM RL = 825 Ω, CL = 100 pF, (see Figure 2) MAX 20† UNIT 0.75 tc(C) + 80 ns ns timing requirements over recommended operating conditions TEST CONDITIONS trfl(IOP) Rise and fall time inputs RL = 825 Ω, CL = 100 pF, (see Figure 2) tsu(IOP) Data setup time before CLKOUT time tw(IOP) MIN Input pulse duration NOM MAX 20† UNIT ns 40 ns tc(C) ns GENERAL PURPOSE TIMERS timing requirements over recommended operating conditions TEST CONDITIONS tr(TIM) TCLK1, TCLK2 rise time MAX 20† tf(TIM) TCLK1, TCLK2 fall time 20† twl(TIM) TCLK1, TCLK2 low time twh(TIM) TCLK1, TCLK2 high time tclk(TIM) Input pulse duration RL = 825 Ω, CL = 100 pF, (see Figure 2) MIN NOM UNIT ns ns tc(C) + 20 ns tc(C) + 20 ns 2tc(C) + 40 ns † Values were derived from characterization data and not tested. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 39 TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 WATCHDOG TIMER TIMING switching characteristics over recommended operating conditions PARAMETER tf(WDT) Fall time, WDT td(WDT) CLKOUT to WDT valid tw(WDT) WDT output pulse duration TEST CONDITIONS RL = 825 Ω, CL = 100 pF, (see Figure 2) MIN NOM MAX 20† 0.25 tc(C) + 20 UNIT ns ns 7 tc(C) ns EVENT MANAGER TIMER switching characteristics over recommended operating conditions PARAMETER tf(CMP) Fall time, CMP0-CMP5 tr(CMP) Rise time, CMP0-CMP5 TEST CONDITIONS MIN NOM RL = 825 Ω, CL = 100 pF, (see Figure 2) MAX UNIT 20† ns 20† ns timing requirements over recommended operating conditions TEST CONDITIONS tw(CAP) CAP0-CAP3 input pulse duration tsu(CAP) Capture input setup time before CLKOUT low RL = 825 Ω, CL = 100 pF, (see Figure 2) † Values were derived from characterization data and not tested. 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 MIN NOM MAX UNIT tc(C) + 20 ns 20† ns TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 TIMING DIAGRAMS Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2 volts, unless otherwise noted. clock timing tr(MC) tw(MCH) tw(MCP)† tc(MC) X2/CLKIN tw(MCL) tf(MC) tw(CH) td(MCC)† CLKOUT tr(C) tf(C) tw(CL) tc(C) † td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform. memory read timing REN tw(RENL) toe(REN) th(A) tsu(A)R Address Bus Valid A11-A0 ta(A) tsu(D)R th(D)R Instruction Input Valid D15-D0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 41 TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 TBLR instruction timing REN 1 2 3 4 7 8 tsu(A)R A11-A0 5 6 th(D)R ta(A) tsu(D)R 9 D15-D0 10 11 12 Legend: 1. 2. 3. 4. 5. 6. TBLR Instruction Prefetch Dummy Prefetch Data Fetch Next Instruction Prefetch Address Bus Valid Address Bus Valid 7. 8. 9. 10. 11. 12. Address Bus Valid Address Bus Valid Instruction Input Valid Instruction Input Valid Data Input Valid Instruction Input Valid TBLW instruction timing REN A11-A0 1 2 4 5 3 6 7 ten(D)W† WE tw(WEL) tsu(D)W† tdis(D)W th(D)W D15-D0 8 9 † Data valid prior to WE↓ Legend: 1. 2. 3. 4. 5. 6. 42 TBLW Instruction Prefetch Dummy Prefetch Next Instruction Prefetch Address Bus Valid Address Bus Valid Address Bus Valid 7. 8. 9. 10. 11. Address Bus Valid Instruction Input Valid Instruction Input Valid Data Output Valid Instruction Input Valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 10 11 TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 IN instruction timing REN 1 3 2 tsu(A)R 4 A11-A0 5 6 tsu(D)R ta(A) th(D)R 7 D15-D0 8 9 Legend: 1. 2. 3. 4. 5. IN Instruction Prefetch Data Fetch Next Instruction Prefetch Address Bus Valid Peripheral Address Valid 6. 7. 8. 9. Address Bus Valid Instruction Input Valid Data Input Valid Instruction Input Valid OUT instruction timing REN A11-A0 2 1 3 4 5 ten(D)W WE tw(WEL) D15-D0 6 7 tdis(D)W tsu(D)W th(D)W Legend: 1. 2. 3. 4. OUT Instruction Prefetch Next Instruction Prefetch Address Bus Valid Peripheral Address Valid 5. Address Bus Valid 6. Instruction Input Valid 7. Data Output Valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 43 TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 reset timing CLKOUT tsu(RS) tsu(RS) tdis(RS-RW) RS tw(RS) REN WE (see Note E) td(RS-RW) ten(RS-AB) tdis(RS-DB) Data Shown Relative To WE D15-D0 Data Out Data In From PC ADDR 0 tdis(RS-AB) ADDRESS BUS Data In From PC ADDR PC+1 AB = PC+1 AB = PC AB = PC = 0 AB = Address Bus NOTES: A. RS forces REN, and WE high and then places data bus D0-D15, REN, WE, and address bus A0-A11 in a high-impedance state. AB outputs (and program counter) are synchronously cleared to zero after the next complete CLK cycle from RS↑. B. RS must be maintained for a minimum of five clock cycles. C. Resumption of normal program will commence after one complete CLK cycle from RS↑. D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK cycle. E. Diagram shown is for definition purpose only. WE and REN are mutually exclusive. microcomputer/microprocessor mode timing CLKOUT RS th(MC/MP) NMI/MC/MP 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 interrupt timing CLKOUT tsu(INT), tsu(NMI) NMI or INT tf(INT), tf(NMI) tw(INT), tw(NMI) bit I/O timing CLKOUT IOP15-IOP0 (Output) trfo(IOP) tsu(IOP) IOP15-IOP0 (Input) tw(IOP) trfI(IOP) general purpose timers tclk(TIM) TCLK1, TCLK2 twh(TIM) tf(TIM) tr(TIM) twl(TIM) watchdog timer CLKOUT td(WDT) tw(WDT) WDT tf(WDT) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 45 TMS320C14, TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 event manager CLKOUT tsu(CAP) CAP3-CAP0 tw(CAP) CMP5-CMP0 tf(CMP) / tr(CMP) 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 PROGRAMMING THE TMS320E14/P14 EPROM CELL The ′E14 and ′P14 include a 4K × 16-bit industry-standard EPROM cell for prototyping and low-volume production. The ′C14 with a 4K-word masked ROM then provides a migration path for cost-effective production. An EPROM adapter socket (part # TMDX3270110), shown in Figure 5, is available to provide 68-pin to 28-pin conversion for programming the ′E14 and ′P14. Key features of the EPROM cell include the normal programming operation as well as verification. The EPROM cell also includes a code protection feature that allows code to be protected against copyright violations. The ′E14/P14 EPROM cells are programmed using the same family and device codes as the TMS27C64 8K × 8-bit EPROM. The TMS27C64 EPROM series are ultraviolet-light erasable, electrically programmable, read-only memories, fabricated using HVCMOS technology. They are pin compatible with existing 28-pin ROMs and EPROMs. These EPROMs operate from a 5-V supply in the read mode; however, a 12.5-V supply is needed for programming. All programming signals are TTL level. For programming outside the system, existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random. Figure 5. EPROM Adapter Socket The ′E14/P14 devices use 13 address lines to address the 4K-word memory in byte format (8K-byte memory). In word format, the most-significant byte of each word is assigned an even address and the least-significant byte an odd address in the byte format. Programming information should be downloaded to EPROM programmer memory in a high-byte to low-byte order for proper programming of the devices (see Figure 6). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 47 TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 TMS320C14 On-Chip Program Memory (Word Format) 0(0000h) 1(000Ah) 2(0002h) 3(0003h) . . . 1234h 5678h 9ABCh DEFOh . . . 4095(0FFh) TMS320E14 and TMS320P14 OnChip Program Memory (Byte Format) 0(0000h) 1(0001h) 2(0002h) 3(0003h) 4(0004h) 5(0005h) 6(0006h) 7(0007h) . . . 34h 12h 78h 56h BCh 9Ah FOh DEh . . . EPROM Programmer Memory Byte Format with Adapter Socket 12h 34h 56h 78h 9Ah BCh DEh FOh . . . 0(0000h) 1(0001h) 2(0002h) 3(0003h) 4(0004h) 5(0005h) 6(0006h) 7(0007h) . . . 8191(1FFFh) Figure 6. Programming Data Format Figure 7 shows the wiring conversion to program the ′E14 and ′P14 using the 28-pin pinout of the TMS27C64. The table of pin nomenclature provides a description of the TMS27C64 pins. CAUTION 4 5 6 7 8 9 10 11 12 13 14 A6 A5 A4 A3 A2 A1 A0 Q1 Q2 Q3 9 8 3.9 k Ω A10 A11 A12 PGM EPT VPP E GND TMS27C64 Pinout G CLKIN 7 6 5 4 3 2 A2 A3 A4 A5 A7 28 VCC 27 PGM 26 EPT 25 A8 24 A9 23 A11 22 G 21 A10 20 E 19 Q8 18 Q7 17 Q6 16 Q5 15 Q4 A6 A12 A7 3 VPP VCC VSS 2 A8 1 A9 The ′E14 and ′P14 do not support the signature mode available with some EPROM programmers. The signature mode places high voltage (12.5 Vdc) on pin A9. The ′E14 and ′P14 EPROM cells are not designed for this feature and will be damaged if subjected to it. A 3.9 kΩ resistor is standard on the TI programmer socket between pin A9 and programmer. This protects the device from unintentional use of the signature mode. 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 TMS320E14 TMS320P14 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 Q1 Q2 Q3 Q4 Q5 VCC V SS Q7 Q6 Q8 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Figure 7. TMS320E14/P14 EPROM Programming Conversion to TMS27C64 EPROM Pinout 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 A1 A0 TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 TERMINAL FUNCTIONS (TMS320E14/P14) NAME I/O A12(MSB)-A0(LSB) CLKIN E I I I On-chip EPROM programming address lines Clock oscillator input EPROM chip enable I I I I EPROM test mode select EPROM output enable Ground EPROM write/program select EPT G GND PGM Q8(MSB)-Q1(LSB) RS VCC VPP I/O I I I DEFINITION Data lines for byte-wide programming of on-chip 8K bytes of EPROM Reset for initializing the device 5-V to 6.5-V power supply 12.5-V to 13-V power supply Table 4 shows the programming levels required for programming, verifying, reading, and protecting the EPROM cell. Table 4. TMS320E14/P14 Programming Mode Levels SIGNAL NAME† TMS320E14/P14 PIN TMS27C64 PIN E 19 20 PROGRAM PROGRAM VERIFY READ EPROM PROTECT PROTECT VERIFY VIL PULSE VIL PULSE VIH VIH VIL VIL VIH VPP VIH VCC VIH VPP VIH VCCP G 23 22 VIL VIH PGM 16 27 PULSE VPP VCC VSS 18 1 4,33 28 3,34 14 VPP VCCP VSS VCCP VSS VCC VSS VCCP VSS VCCP VSS CLKIN 24 14 EPT 17 26 VSS VSS VSS VSS VSS VSS VSS VPP VSS VPP Q1-Q8 42, 41, 38, 37, 32-29 11–13, 15-19, Data In Data Out Data Out Q8 = PULSE Q8 = RBIT A12-A7 15, 11, 10, 8, 7, 2 2, 23, 21, 24, 25, 3 ADDR ADDR ADDR X X A6 1 4 ADDR ADDR ADDR X A5 68 5 ADDR ADDR ADDR X VIL X VIH X A4 67 6 ADDR ADDR ADDR A3-A0 66, 65, 56, 55 7-10 ADDR ADDR ADDR X X † Signal names shown for ′E14/P14 EPROM programming mode only. Legend: VIH VCC = DIN VCCP = TTL high level; VIL = TTL low level; ADDR = byte address bit; VPP = 12.5 V ± 0.25 V (FAST) or 13 V ± 0.25 V (SNAP! Pulse). 5 V ± 0.25 V; X = don’t care; PULSE = low-going TTL pulse. = byte to be programmed at ADDR; QOUT = byte stored at ADDR.; RBIT = ROM protect bit = 6 V ± 0.25 V (FAST) or 6.5 V ± 0.25 V (SNAP! Pulse). programming Since every memory in the cell is at a logic high, the programming operation reprograms selected bits to low. Once the ′320E14 is programmed, these bits can only be erased using ultraviolet light. The correct byte is placed on the data bus with VPP set to the 12.5-V level. The PGM pin is then pulsed low to program in the zeros. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 49 TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 erasure Before programming, the ′E14 must be erased by exposing it to ultraviolet light. The recommended minimum exposure dose (UV-intensity × exposure-time) is 15 W•s/cm2. A typical 12-mW•s/cm2, filterless UV lamp will erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After exposure, all bits are in the high state. verify/read To verify correct programming, the EPROM cell can be read using either the verify or read line definitions shown in Table 5, assuming the inhibit bit (RBIT) has not been programmed. program inhibit Programming may be inhibited by maintaining a high level input on the E pin or PGM pin. standard programming procedure Before programming, the ′E14 must first be completely erased. The device can then be programmed with the correct code. It is advisable to program unused sections with zeros as a further security measure. After the programming is complete, the code programmed into the cell should be verified. If the cell passes verification, the next step is to program the ROM protect bit (RBIT). Once the RBIT programming is verified, an opaque label should be placed over the window to protect the EPROM cell from inadvertent erasure by ambient light. At this point, the programming is complete, and the device is ready to be placed into its destination circuit. Refer to other appendices of the TMS320C1x User’s Guide for additional information on EPROM programming. recommended timing requirements for programming: VCC = 6 V and VPP = 12.5 V (FAST) or VCC = 6.5 V and VPP = 13 V (SNAP! PULSE), TA = 25°C (see Note 13) MIN Fast programming algorithm NOM MAX UNIT 0.95 1 1.05 ms 95 100 105 µs 78.75 ms tw(PGM) Initial program pulse duration tw(FPGM) tsu(A) Final pulse duration Address setup time 2 µs tsu(E) tsu(G) E setup time 2 µs G setup time 2 µs tsu(D) tsu(VPP) Data setup time 2 µs VPP setup time VCC setup time 2 µs 2 µs Address hold time 0 µs Data hold time 2 µs tsu(VCC) th(A) th(D) SNAP! Pulse programming algorithm Fast programming only 2.85 NOTE 13: For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V and VPP = 12.5 V ± 0.5 V during programming. 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320E14, TMS320P14 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 program cycle timing Verify Program A12-A0 Address Stable Address N+1 tsu(A) Q8-Q1 Data In Stable th(A) tdis(G)† tsu(D) VIL VIH/VOH Data Out Valid HI-Z VIH VIL/VOL VPP VPP tsu(VPP) VCC VCCP VCC tsu(VCC) VCC VIH E tsu(E) VIL th(D) VIH PGM ten(G)† tw(FPGM) VIL tsu(G) VIH G VIL † tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 51 TMS320C15, TMS320E15, TMS320LC15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 Key Features: TM320C15/E15/LC15/P15 • • • • • • • • • • • • +5 V or +3.3 V Instruction Cycle Timing: — 160-ns (TMS320C15-25/E15-25) — 200-ns (TMS320C15/E15/P15) — 250-ns (TMS320LC15) 256 Words of On-Chip Data RAM 256-Word RAM Interrupt Data (16) 4K Words of On-Chip Program ROM (TMS320C15/C15-25/LC15) 4K-Word ROM/EPROM 4K Words of On-Chip Program EPROM (TMS320E15/E15-25) 32-Bit ALU/ACC Multiplier One-Time Programmable (OTP) Windowless EPROM Version Available (TMS320P15) Address (12) Shifters EPROM Code Protection for Copyright Security External Memory up to 4K-Words at Full Speed 16 × 16-Bit Multiplier With 32-Bit Product 0 to 16-Bit Barrel Shifter On-Chip Clock Oscillator 3.3-V Low-Power Version Available (TMS320LC15) Device Packaging: — 40-Pin Dip (All Devices) — 44-Lead PLCC (TMS320C15/C15-25/LC15/P15) — 44-Lead-QUAD (TMS320E15/E15-25) TMS320C15/E15/LC15/P15 FN/FZ Package (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A2/PA2 A3 A4 A5 A6 A7 A8 MEN DEN WE VCC A9 A10 A11 D0 D1 D2 D3 D4 D5 6 5 4 3 2 1 44 43 42 41 40 CLKOUT X1 X2/CLKIN BIO NC VSS D8 D9 D10 D11 D12 POST OFFICE BOX 1443 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VCC D13 D14 D15 D7 D6 D5 D4 D3 D2 V CC A1/PA1 A0/PA0 MC/MP RS INT CLKOUT X1 X2/CLKIN BIO VSS D8 D9 D10 D11 D12 D13 D14 D15 D7 D6 INT RS MC/MP A0/PA0 A1/PA1 VSS A2/PA2 A3 A4 A5 A6 TMS320C15/E15/LC15/P15 N/JD Package (Top View) 52 GND • HOUSTON, TEXAS 77001 A7 A8 MEN DEN WE VCC A9 A10 A11 D0 D1 TMS320C15, TMS320E15, TMS320LC15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 functional block diagram X1 Program Bus 12 LSB Controller 16 12 12 PC (12) 12 12 MUX 3 A11-A0/ PA2-PA0 MUX 12 Stack 4 × 12 3 Instruction 16 MUX WE DEN MEN BIO MC/MP INT RS X2/CLKIN Address CLKOUT Program ROM/EPROM (4K Words) D15-D0 Program Bus 16 16 Data Bus 7 16 16 16 AR0 (16) ARP DP AR1 (16) 8 T(16) Shifter (0–16) Multiplier 8 MUX 8 P(32) 32 32 MUX Address 32 Legend: ACC ALU ARP AR0 AR1 DP P PC T 16 32 Data RAM (256 Words) ALU (32) = = = = = = = = = Accumulator Arithmetic Logic Unit Auxiliary Register Pointer Auxiliary Register 0 Auxiliary Register 1 Data Page Pointer P Register Program Counter T Register Data 32 ACC (32) 32 32 Shifter (0,1,4) 16 16 16 Data Bus POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 53 TMS320C15, TMS320E15, TMS320LC15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 TERMINAL FUNCTIONS (TMS320C15/E15/LC15/P15)† NAME I/O‡ DEFINITION A11-A0/PA2-PA0 BIO CLKOUT O I O External address bus. I/O port address multiplexed over PA2-PA0. External polling input System clock output, 1/4 crystal/CLKIN frequency D15-D0 DEN INT MC/MP I/O O I I 16-bit parallel data bus Data enable for device input data on D15-D0 External interrupt input Memory mode select pin. High selects microcomputer mode. Low selects microprocessor mode. MEN NC RS VCC O O I I Memory enable indicates that D15-D0 will accept external memory instruction. No connection Reset for initializing the device + 5 V supply VSS WE X1 X2/CLKIN I O O I Ground Write enable for device output data on D15-D0 Crystal output for internal oscillator Crystal input internal oscillator or external system clock input † See EPROM programming section. ‡ Input/Output/High-impedance state. 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C15, TMS320E15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 electrical specifications This section contains the electrical specifications for the ′C15/E15/P15 digital signal processors, including test parameter measurement information. Parameters with PP subscripts apply only to the ′E15/P15 in the EPROM programming mode (see Note 11). absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Supply voltage range, VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 14 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 mW Operating free-air temperature: L suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55 °C to 150 °C † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 6: All voltage values are with respect to VSS. recommended operating conditions VCC Supply voltage VPP VSS Supply voltage (see Note 11) EPROM devices All other devices MIN NOM MAX UNIT 4.75 5 5.25 V 4.5 5 5.5 V 12.25 12.5 12.75 V Supply voltage VIH High-level input voltage VIL Low-level input voltage IOH IOL High-level output current, all outputs TA Operating free-air temperature 0 V CLKIN 3 V All remaining inputs 2 V MC/MP 0.6 V All remaining inputs 0.8 V Low-level output current (All outputs except for TMS320LC15) – 300 µA 2 mA L suffix 0 70 °C A suffix – 40 85 °C NOTE 11: VPP can be applied only to programming pins designed to accept VPP as an input. During programming the total supply current is IPP + ICC. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 55 TMS320C15, TMS320E15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 electrical characteristics over specified temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage IOH = MAX IOH = 20 µA (see Note 8) VOL Low-level output voltage IOL = MAX IOZ Off-state output current II Input current ICC‡ Ci 2.4 3 VCC = MAX V 0.5 VO = 2.4 V VO = 0.4 V 20 – 20 All inputs except CLKIN ±20 CLKIN ±50 f = 20.5 MHz, VCC = 5.5 V, TA = 0°C to 70°C 45 55 TMS320C15-25 f = 25.6 MHz, VCC = 5.5 V, TA = 0°C to 70°C 50 65 TMS320E15 f = 20.5 MHz, VCC = 5.25 V, TA = – 40°C to 85°C 55 75 TMS320E15-25 f = 25.6 MHz, VCC = 5.25 V, TA = 0°C to 70°C 65 25‡ 85 Data bus µA µA mA pF 10‡ All others V pF 15‡ 25‡ f = 1 MHz, all other pins 0 V UNIT V TMS320C15 All other Output capacitance MAX VCC – 0.4 Data bus Input capacitance Co TYP† 0.3 VI = VSS to VCC Supply current MIN † All typical values are at VCC = 5 V, TA = 70°C and are used for thermal resistance calculations. ‡ ICC characteristics are inversely proportional to temperature. For ICC dependence on temperature, frequency, and loading, see Figure 3. NOTE 7: This voltage specification is included for interface to HC logic. However, note that all of the other timing parameters defined in this data sheet are specified for TTL logic levels and will differ for HC logic levels. CLOCK CHARACTERISTICS AND TIMING The TMS320C15/E15/P15 can use either its internal oscillator or an external frequency source for a clock. internal clock option The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and should be specified at a load capacitance of 20 pF. PARAMETER TMS320C15 Crystal frequency, fx TMS320E15/P15 TMS320C15-25/E15-25 C1, C2 56 POST OFFICE BOX 1443 TEST CONDITIONS MIN TA = 0°C to 70°C TA = – 40°C to 85°C 6.7 20.5 6.7 20.5 TA = 0°C to 70°C TA = 0°C to 70°C 6.7 • HOUSTON, TEXAS 77001 NOM MAX UNIT MHz 25.6 10 pF TMS320C15, TMS320E15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 external clock option An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left unconnected. The external frequency injected must conform to the specifications listed in the table below. switching characteristics over recommended operating conditions TMS320C15/E15/P15 PARAMETER tc(C) CLKOUT cycle time‡ tr(C) CLKOUT rise time tf(C) tw(CL) tw(CH) td(MCC) CLKOUT fall time Pulse duration, CLKOUT low TEST CONDITIONS MIN 195.12 RL = 825 Ω, CL = 100 pF (see Figure 2) Pulse duration, CLKOUT high NOM 200 TMS320C15-25/E15-25 MIN 156.25 NOM MAX UNIT 160 ns 10† 10† ns 8† 8† ns 92† 90† 72† 70† ns 25† Delay time, CLKIN↑ to CLKOUT↓ MAX 60† 25† ns 50† ns † Values derived from characterization data and not tested. ‡ tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 57 TMS320C15, TMS320E15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 timing requirements over recommended operating conditions TMS320C15/E15/P15 MIN tc(MC) Master clock cycle time TMS320C15-25/E15-25 NOM MAX MIN 50 150 39.06 10† 10† 48.78 tr(MC) Rise time, master clock input 5† tf(MC) Fall time, master clock input 5† tw(MCP)† Pulse duration, master clock tw(MCL) Pulse duration, master clock low 0.6tc(MC)† 20† 0.4tc(MC) MAX 40 150 ns 5† 10† ns 5† 10† ns 0.55tc(MC)† 15† ns 15† ns 0.45tc(MC) 20† tw(MCH) Pulse duration, master clock high † Values derived from characterization data and not tested. UNIT NOM ns MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions TEST CONDITIONS PARAMETER td1 Delay time, CLKOUT↓ to address bus valid td2 Delay time, CLKOUT↓ to MEN↓ td3 Delay time, CLKOUT↓ to MEN↑ td4 Delay time, CLKOUT↓ to DEN↓ td5 TMS320C15/E15/P15 MIN NOM TMS320C15-25/E15-25 MAX MIN 50 10‡ 10† NOM MAX UNIT 40 ns 1/4tc(C) – 5† –10† 1/4tc(C) +12 ns 12 ns 1/4tc(C) +12 ns 15 1/4tc(C) – 5† –10† 12 ns 1/2tc(C) +15 1/2tc(C) – 5† 1/2tc(C) +12 ns 12 ns 1/4tc(C) +52 ns 1/4tc(C) – 5† –10† 1/4tc(C) +15 1/4tc(C) +15 Delay time, CLKOUT↓ to DEN↑ 1/4tc(C) – 5† –10† td6 Delay time, CLKOUT↓ to WE↓ 1/2tc(C) – 5† td7 Delay time, CLKOUT↓ to WE↑ –10† td8 Delay time, CLKOUT↓ to data bus OUT valid td9 Time after CLKOUT↓ that data bus starts to be driven td10 Time after CLKOUT↓ that data bus stops being driven (TMS320C15/C15-25 only) 1/4tc(C) + 40† 1/4tc(C) + 40† ns td10 Time after CLKOUT↓ that data bus stops being driven (TMS320E15/E15-25 only) 1/4tc(C) + 70† 1/4tc(C) +70† ns tv Data bus OUT valid after CLKOUT↓ th(A-WMD) Address hold time after WE↑, MEN↑, or DEN↑ (see Note 15) tsu(A-MD) Address bus setup time prior to DEN↓ RL = 825 Ω, CL = 100 pF (see Figure 2) 15 15 –10† 1/4tc(C) +65 1/4tc(C) – 5† 1/4tc(C) – 5† 1/4tc(C) – 10 0† ns 1/4tc(C) – 10 2† 0† 1/4tc(C) – 45 ns 2† ns 1/4tc(C) – 35 ns † Values derived from characterization data and not tested. NOTE 14: Address bus will be valid upon WE↑, MEN↑, or DEN↑. timing requirements over recommended operating conditions TEST CONDITIONS tsu(D) Setup time, data bus valid prior to CLKOUT↓ th(D) Hold time, data bus held valid after CLKOUT↓ (see Note 9) RL = 825 Ω, CL = 100 pF (see Figure 2) TMS320C15/E15/P15 MIN NOM MAX POST OFFICE BOX 1443 • MIN NOM MAX UNIT 50 40 ns 0 0 ns NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓. 58 TMS320C15-25/E15-25 HOUSTON, TEXAS 77001 TMS320C15, TMS320E15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 RESET (RS) TIMING switching characteristics over recommended operating conditions PARAMETER TEST CONDITIONS td11 Delay time, DEN↑, WE↑, and MEN↑ from RS tdis(R) Data bus disable time after RS MIN TYP RL = 825 Ω, CL = 100 pF (see Figure 2) MAX UNIT 1/2tc(C) + 50† ns 1/4tc(C) + 50† ns † Values derived from characterization data and not tested. timing requirements over recommended operating conditions TMS320C15/E15/P15 MIN tsu(R) Reset (RS) setup time prior to CLKOUT (see Note 10) tw(R) RS pulse duration NOM TMS320C15-25/E15-25 MAX 50 MIN NOM MAX 40 5tc(C) UNIT ns 5tc(C) ns NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation. INTERRUPT (INT) TIMING timing requirements over recommended operating conditions TMS320C15/E15/P15 MIN tf(INT) Fall time, INT tw(INT) Pulse duration, INT tsu(INT) Setup time, INT↓ before CLKOUT↓ NOM TMS320C15-25/E15-25 MAX MIN NOM 15 MAX 15 UNIT ns tc(C) tc(C) ns 50 40 ns IO (BIO) TIMING timing requirements over recommended operating conditions TMS320C15/E15/P15 MIN tf(IO) Fall time, BIO tw(IO) Pulse duration, BIO tsu(IO) Setup time, BIO↓ before CLKOUT↓ NOM TMS320C15-25/E15-25 MAX MIN 15 POST OFFICE BOX 1443 • NOM MAX 15 UNIT ns tc(C) tc(C) ns 50 40 ns HOUSTON, TEXAS 77001 59 TMS320C15, TMS320E15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 TIMING DIAGRAMS Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. clock timing tr(MC) tw(MCH) tw(MCP)† tc(MC) X2/CLKIN tw(MCL) tf(MC) tw(CH) td(MCC)† CLKOUT tr(C) tf(C) tw(CL) tc(C) † td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform. memory read timing tc(C) CLKOUT td2 td3 MEN td1 A11-A0 tsu(A-MD) th(A-WMD) Address Bus Valid tsu(D) Instruction Valid D15-D0 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 th(D) TMS320C15, TMS320E15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 TBLR instruction timing CLKOUT td2 td3 MEN 1 2 td3 3 4 7 8 td1 A11-A0 5 6 th(D) tsu(D) 9 D15-D0 10 11 12 Legend: 1. 2. 3. 4. 5. 6. TBLR Instruction Prefetch Dummy Prefetch Data Fetch Next Instruction Prefetch Address Bus Valid Address Bus Valid 7. 8. 9. 10. 11. 12. Address Bus Valid Address Bus Valid Instruction Valid Instruction Valid Data Input Valid Instruction Valid TBLW instruction timing CLKOUT MEN A11-A0 1 2 4 5 3 6 7 td6 td7 WE td8 tv td9 D15-D0 8 9 10 td10 11 Legend: 1. 2. 3. 4. 5. 6. TBLW Instruction Prefetch Dummy Prefetch Next Instruction Prefetch Address Bus Valid Address Bus Valid Address Bus Valid 7. 8. 9. 10. 11. Address Bus Valid Instruction Valid Instruction Valid Data Output Valid Instruction Valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 61 TMS320C15, TMS320E15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 IN instruction timing CLKOUT MEN 1 2 tsu(A-MD) A11-A0 3 tsu(D) 4 5 td5 td4 DEN th(D) 6 D15-D0 7 8 Legend: 1. 2. 3. 4. IN Instruction Prefetch Next Instruction Prefetch Address Bus Valid Peripheral Address Valid 5. 6. 7. 8. Address Bus Valid Instruction Valid Data Input Valid Instruction Valid OUT instruction timing CLKOUT MEN 1 A11-A0 3 2 4 5 td6 td7 td9 WE td8 D15-D0 tv 6 td10 7 Legend: 1. 2. 3. 4. 62 IN Instruction Prefetch Next Instruction Prefetch Address Bus Valid Peripheral Address Valid 5. 6. 7. 8. Address Bus Valid Instruction Valid Data Output Valid Instruction Input Valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 8 TMS320C15, TMS320E15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 reset timing CLKOUT tsu(R) tsu(R) RS tw(R) DEN WE see MEN Note E tdis(R) Data In From PC ADDR 0 td11 Data In From PC ADDR PC+1 Data Shown Relative to WE D15-D0 MEN AB = PC+1 AB = Address Bus Address Bus AB = PC AB = PC = 0 AB = PC+1 NOTES: A. RS forces DEN, WE, and MEN high and places data bus D0 through D15 in a high-impedance state. AB outputs (and program counter) are synchronously cleared to zero after the next complete CLK cycle from RS↓. B. RS must be maintained for a minimum of five clock cycles. C. Resumption of normal program will commence after one complete CLK cycle from RS↑. D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK cycle. E. Diagram shown is for definition purpose only. DEN, WE, and MEN are mutually exclusive. F. During a write cycle, RS may produce an invalid write address. interrupt timing CLKOUT tsu(INT) INT tf(INT) tw(INT) BIO timing CLKOUT tsu(IO) BIO tf(IO) tw(IO) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 63 TMS320E15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 absolute maximum ratings over specified temperature range (unless otherwise noted)† Supply voltage range, VPP (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 6: All voltage values are with respect to VSS. recommended operating conditions VPP Supply voltage (see Note 11) MIN NOM MAX UNIT 12.25 12.5 12.75 V NOTE 11: VPP can be applied only to programming pins designed to accept VPP as an input. During programming the total supply current is IPP + ICC. electrical characteristics over specified temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IPP1 VPP supply current IPP2 VPP supply current (during program pulse) ‡ All typical values except for ICC are at VCC = 5 V, TA = 25°C. MIN VPP = VCC 5.5 V VPP = 12.75 V TYP‡ 30 MAX UNIT 100 V 50 V recommended timing requirements for programming, TA = 25°C, VCC = 6, VPP = 12.5 V, (see Note 13) MIN NOM MAX UNIT 0.95 1 1.05 ms 63 ms tw(IPGM) tw(FPGM) Initial program pulse duration Final pulse duration 3.8 tsu(A) tsu(E) Address setup time 2 µs E setup time 2 µs tsu(G) G setup time 2 µs tdis(G) Output disable time from G (see Note 15) 0 130§ ten(G) tsu(D) Output enable time from G 0 150§ Data setup time 2 µs tsu(VPP) tsu(VCC) VPP setup time VCC setup time 2 µs 2 µs th(A) th(D) Address hold time 0 µs Data hold time 2 µs ns ns § Values derived from characterization data and not tested. NOTES: 13. For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V and VPP = 12.5 V ± 0.5 V during programming. 15. Common test conditions apply for tdis(G) except during programming. 64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320E15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 PROGRAMMING THE TMS320E15/P15 EPROM CELL ′E15/P15 devices include a 4K × 16-bit industry-standard EPROM cell for prototyping, early field testing, and low-volume production. In conjunction with this EPROM, the ′E15/P15 with a 4K-word masked ROM, then, provide more migration paths for cost-effective production. EPROM adapter sockets are available that provide pin-to-pin conversions for programming any ′E15/P15 devices. One adapter socket (part number RTC/PGM320C-06), shown in Figure 8, converts a 40-pin DIP device into an equivalent 28-pin device. Another socket (part number RTC/PGM320A-06), not shown, permits 44- to 28-pin conversion. Figure 8. EPROM Adapter Socket (40-pin to 28-pin DIP Conversion) Key features of the EPROM cell include the normal programming operation as well as verification. The EPROM cell also includes a code protection feature that allows code to be protected against copyright violations. The ′E15/P15 EPROM cell is programmed using the same family and device pinout codes as the TMS27C64 8K × 8-bit EPROM. The TMS27C64 EPROM series are unltraviolet-light erasable, electrically programmable, read-only memories, fabricated using HVCMOS technology. They are pin-compatible with existing 28-pin ROMs and EPROMs. These EPROMs operate from a single 5-V supply in the read mode; however, a 12.5-V supply is needed for programming. All programming signals are TTL level. For programming outside the system, existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random. Figure 9 shows the wiring conversion to program the ′E15/P15 using the 28-pin pinout of the TMS27C64. Table 5 on pin nomenclature provides a description of the TMS27C64 pins. The code to be programmed into the device should be in serial mode. The ′E15/P15 devices use 13 address lines to address 4K-word memory in byte format. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 65 TMS320E15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 Q1 Q2 Q3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TMS27C64 PINOUT A1 A0(LSB) VPP RS EPT A2 A3 A4 A5 A6 A7 A8 CLKIN GND Q1(LSB) Q2 Q3 Q4 Q5 Q6 Q7 Q8(MSB) VCC A9 A10 A11 (MSB)A12 E G PGM TMS320E15/P15 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 3.9 kΩ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC PGM EPT A8 A9 A11 G A10 E Q8 Q7 Q6 Q5 Q4 TMS27C64 PINOUT CAUTION Although acceptable by some EPROM programmers, the signature mode cannot be used on any ′E1x device. The signature mode will input a high-level voltage (12.5 Vdc) onto pin A9. Since this pin is not designed for high voltage, the cell will be damaged. To prevent an accidental application of voltage, Texas Instruments has inserted a 3.9 kΩ resistor between pin A9 of the TI programmer socket and the programmer itself. Pin Nomenclature (TMS320E15/P15) NAME A0-A12 CLKIN E EPT G GND PGM Q1-Q8 RS VCC VPP I/O I I I I I I I I/O I I I DEFINITION On-chip EPROM programming address lines Clock oscillator input EPROM chip select EPROM test mode select EPROM read/verify select Ground EPROM write/program select Data lines for byte-wide programming of on-chip 8K bytes of EPROM Reset for initializing the device 5-V power supply 12.5-V power supply Figure 9. TMS320E15/P15 EPROM Programming Conversion to TMS27C64 EPROM Pinout 66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320E15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 Table 5 shows the programming levels required for programming, verifying, reading, and protecting the EPROM cell. Table 5. TMS320E15/P15 Programming Mode Levels SIGNAL NAME TMS320E15 PIN TMS27C64 PIN PROGRAM VERIFY READ PROTECT VERIFY EPROM PROTECT E 25 20 VIL VIL VIL VIL VIH G 24 22 VIH PULSE PULSE VIL VIH PGM 23 27 PULSE VIH VIH VIH VIH VPP 3 1 VPP VPP VCC VCC + 1 VPP VCC 30 28 VCC VCC VCC VCC + 1 VCC + 1 VSS 10 14 VSS VSS VSS VSS VSS CLKIN 8 14 VSS VSS VSS VSS VSS RS 4 14 VSS VSS VSS VSS VSS EPT 5 26 VSS VSS VSS VPP VPP Q1-Q8 11-18 11-13, 15-19 DIN QOUT QOUT Q8=RBIT Q8=PULSE A0-A3 2, 1, 40, 39 10-7 ADDR ADDR ADDR X X A4 38 6 ADDR ADDR ADDR X VIH A5 37 5 ADDR ADDR ADDR X X A6 36 4 ADDR ADDR ADDR VIL X A7-A9 35, 34, 29 3, 25, 24 ADDR ADDR ADDR X X A10-A12 28-26 21, 23, 2 ADDR ADDR ADDR X X Legend: VIH = TTL high level; VIL = TTL low level; ADDR = byte address bit VPP = 12.5 V ± 0.25 V; VCC = 5 V ± 0.25 V; X = don’t care PULSE = low-going TTL level pulse; DIN = byte to be programmed at ADDR QOUT = byte stored at ADDR; RBIT = ROM protect bit. programming Since every memory bit in the cell is a logic 1, the programming operation reprograms certain bits to 0. Once programmed, these bits can only be erased using ultraviolet light. The correct byte is placed on the data bus with VPP set to the 12.5 V level. The PGM pin is then pulsed low to program in the zeros. erasure Before programming, the device must be erased by exposing it to ultraviolet light. The recommended minimum exposure dose (UV-intensity × exposure-time) is 15 W•s/cm2. A typical 12-mW/cm2, filterless UV lamp will erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After exposure, all bits are in the high state. verify/read To verify correct programming, the EPROM cell can be read using either the verify or read line definitions shown in Table 5, assuming the inhibit bit has not been programmed. program inhibit Programming may be inhibited by maintaining a high level input on the E pin or PGM pin. read The EPROM contents may be read independent of the programming cycle, provided the RBIT (ROM protect bit) has not been programmed. The read is accomplished by setting E to zero and pulsing G low. The contents of the EPROM location selected by the value on the address inputs appear on Q8-Q1. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 67 TMS320E15, TMS320P15 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 output disable During the EPROM programming process, the EPROM data outputs may be disabled, if desired, by establishing the output disable state. This state is selected by setting G and E pins high. While output disable is selected, Q8-Q1are placed in the high-impedance state. EPROM protection To protect the proprietary algorithms existing in the code programmed on-chip, the ability to read or verify code from external accesses can be completely disabled. Programming the RBIT disables external access of the EPROM cell and disables the microprocessor mode, making it impossible to access the code resident in the EPROM cell. The only way to remove this protection is to erase the entire EPROM cell, thus removing the proprietary information. The signal requirements for programming this bit are shown in Table 5. The cell can be determined as protected by verifying the programming of the RBIT shown in the table. standard programming procedure Before programming, the device must first be completely erased. Then the device can be programmed with the correct code. It is advisable to program unused sections with zeroes as a further security measure. After the programming is complete, the code programmed into the cell should be verified. If the cell passes verification, the next step is to program the ROM protect bit (RBIT). Once the RBIT programming is verified, an opaque label should be placed over the window to protect the EPROM cell from inadvertent erasure by ambient light. At this point, the programming is complete, and the device is ready to be placed into its destination circuit. program cycle timing Verify Program A12-A0 Address Stable Address N+1 VIL tsu(A) Q8-Q1 VIH th(A) Data In Stable Data Out Valid HI-Z tsu(D) VIH/VOH VIL/VOL tdis(G) VPP VPP VCC tsu(VPP) VCC+1 VCC VCC tsu(VCC) VIH E VIL tsu(E) th(D) VIH PGM tsu(G) tw(IPGM) tw(FPGM) ten(G) VIL VIH G VIL 68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320LC15 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 absolute maximum ratings over specified temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.6 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.5 Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.5 Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mW Air temperature range above operating devices: L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40 °C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55 °C to +150°C † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 6: All voltage values are with respect to VSS. recommended operating conditions VCC VSS Supply voltage MIN NOM MAX 3.0 3.3 3.6 Supply voltage 0 UNIT V V All inputs except CLKIN 2.0 V CLKIN 2.5 V VIH High-level input voltage VIL IOH Low-level input voltage 0.55 V High-level output current (all outputs) – 300 µA IOL Low-level output current (all outputs) 1.5 mA TA Operating free-air temperature All inputs L version 0 70 °C A version – 40 85 °C electrical characteristics over specified temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = MAX IOH = 20 µA (see Note 7) VOH High-level output voltage VOL Low-level output voltage IOZ Off-state ouput current II Input current Ci Input capacitance IOL = MAX VCC = MAX, Output capacitance MAX 2.0 V 20 –20 All inputs except CLKIN ± 20 CLKIN ± 50 f = 1 MHz, All other pins 0 V Data bus All others UNIT V VCC – 0.4‡ 0.5 Data bus Co TYP† VO = VCC VO = VSS VI = VSS to VCC VI = VSS to VCC All others MIN V µA µA 25‡ 15‡ pF 25‡ 10‡ pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Values derived from characterization data and not tested. NOTE 7: This voltage specification is included for interface to HC logic. However, note that all of the other timing parameters defined in this data sheet are specified for TTL logic levels and will differ for HC logic levels. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 69 TMS320LC15 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 FN Package (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A2/PA2 A3 A4 A5 A6 A7 A8 MEN DEN WE VCC A9 A10 A11 D0 D1 D2 D3 D4 D5 6 5 4 3 2 1 44 43 42 41 40 CLKOUT X1 X2/CLKIN BIO NC VSS D8 D9 D10 D11 D12 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS D13 D14 D15 D7 D6 D5 D4 D3 D2 VSS A1/PA1 A0/PA0 MC/MP RS INT CLKOUT X1 X2/CLKIN BIO VSS D8 D9 D10 D11 D12 D13 D14 D15 D7 D6 INT RS MC/MP A0/PA0 A1/PA1 VSS A2/PA2 A3 A4 A5 A6 N Package (Top View) INTERNAL CLOCK OPTION ′320LC15 X1 X2/CLKIN Crystal C1 C2 PARAMETER MEASUREMENT INFORMATION 1.75 V RL = 825 Ω From Output Under Test Test Point CL = 100 pF Figure 10. Test Load Circuit 70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 A7 A8 MEN DEN WE VCC A9 A10 A11 D0 D1 TMS320LC15 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 CLOCK CHARACTERISTICS AND TIMING The ′LC15 can use either its internal oscillator or an external frequency source for a clock. internal clock option The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and be specified at a load capacitance of 20 pF. PARAMETER TEST CONDITIONS Crystal frequency fx MIN 4.0 TA = – 40°C to 85°C C1, C2 NOM MAX UNIT 16 MHz 10 pF external clock option An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left unconnected. The external frequency injected must conform to the specifications listed in the table below. switching characteristics over recommended operating conditions tc(C) tr(C) tf(C) tw(CL) PARAMETER † CLKOUT cycle time TEST CONDITIONS MIN NOM 250 CLKOUT rise time RL = 825 Ω, CLKOUT fall time CL = 100 pF, Pulse duration, CLKOUT low (see Figure 2) tw(CH) Pulse duration, CLKOUT high td(MCC) Delay time, CLKIN↑ to CLKOUT↓ MAX UNIT 1000 ns 10‡ 8‡ ns 117‡ 115‡ ns 20 ns ns 70 ns timing requirements over recommended operating conditions MIN NOM MAX UNIT tc(MC) Master clock cycle time 150 ns tr(MC) Rise time, master clock input 5‡ 10† ns Fall time, master clock input 5‡ 10† ns tf(MC) 62.5 0.4 t c(MC)‡ tw(MCP) Pulse duration, master clock 0.6 t c(MC)‡ ns tw(MCL) Pulse duration, master clock low at tc(MC) min 26 ns tw(MCH) Pulse duration, master clock high at tc(MC) min 26 ns † tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used) ‡ Values derived from characterization data and not tested. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 71 TMS320LC15 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 electrical characteristics over specified temperature range (unless otherwise noted) TYP† MAX ICC‡ f = 16.0 MHz, VCC = 3.6 V, TA = 0°C to 70°C 15 † All typical values are at TA = 70°C and are used for thermal resistance calculations. ‡ ICC characteristics are inversely proportional to temperature. For ICC dependence on frequency, see figure below. 20 PARAMETER TEST CONDITIONS MIN UNIT mA typical power vs. frequency graph (outputs unloaded)§ 20.0 15.0 I CC (mA) VCC = 3.5 V VCC = 3 V 10.0 5.0 0.0 0 2 4 6 10 8 12 CLKIN Frequency, MHz – 40 °C to 85°C Temperature Range § Device operation is not guaranteed below 4 MHz CLKIN. Graph is for device in RESET; i.e., only clock-out is driven. 72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 14 16 TMS320LC15 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions PARAMETER TEST CONDITIONS MIN 10† MAX UNIT 75 ns ns Delay time CLKOUT↓ to MEN↑ 1/4 tc(C)–5† 1/4 tc(C)+25 –10† 30 td4 Delay time CLKOUT↓ to DEN↓ 1/4 tc(C)–5† 1/4 tc(C)+25 ns td5 Delay time CLKOUT↓ to DEN↑ –10† 30 ns Delay time CLKOUT↓ to WE↓ 1/2 tc(C)–5† 1/2 tc(C)+25 ns td1 Delay time CLKOUT↓ to address bus valid td2 Delay time CLKOUT↓ to MEN↓ td3 td6 RL = 825Ω, CL = 100 pF, (see Figure 2) td7 Delay time CLKOUT↓ to WE↑ td8 Delay time CLKOUT↓ to data bus OUT valid td9 Time after CLKOUT↓ that data bus starts to be driven td10 Time after CLKOUT↓ that data bus stops being driven tv Data bus OUT valid after CLKOUT↓ 30 ns 1/4 tc(C)+75 ns 1/4 tc(C)–5† ns 1/4 tc(C)+60 1/4 tc(C)–10 th(A-WMD) Address hold time after WE↑, MEN↑, or DEN↑ (see Note 14) tsu(A-MD) –10† Address bus setup time to DEN↓ ns ns ns 0† ns – 4† ns † Values derived from characterization data and not tested. NOTE 14: Address bus will be valid upon WE↑, MEN↑, or DEN↑. timing requirements over recommended operating conditions TEST CONDITIONS tsu(D) Setup time data bus valid prior to CLKOUT↓ th(D) Hold time, data bus held valid after CLKOUT↓ (see Note 9) RL = 825Ω, CL = 100 pF, (see Figure 2) MIN NOM MAX UNIT 56 ns 0 ns NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 73 TMS320LC15 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 RESET (RS) TIMING switching characteristics over recommended operating conditions TEST CONDITIONS td11 Delay time, DEN↑, WE↑, and MEN↑ from RS tdis(R) Data bus disable time after RS MIN RL = 825Ω, CL = 100 pF, (see Figure 2) NOM MAX UNIT 1/2tc(C)+75 ns 1/4tc(C)+75 ns † These parameters do not apply to this device. timing requirements over recommended operating conditions MIN tsu(R) Reset (RS) setup time prior to CLKOUT (see Note 10) tw(R) RS pulse duration NOTE 10: NOM MAX 85 UNIT ns 5tc(C) ns RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation. INTERRUPT (INT) TIMING timing requirements over recommended operating conditions MIN tF(INT) Fall time, INT tw(INT) Pulse duration, INT NOM MAX 15 tsu(INT) Setup time, INT↓ before CLKOUT↓ UNIT ns tc(C) ns 85 ns I/O (BIO) TIMING timing requirements over recommended operating conditions MIN tf(IO) Fall time BIO tw(IO) Pulse duration BIO tsu(IO) Setup time BIO↓ before CLKOUT↓ 74 NOM MAX 15 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 UNIT ns tc(C) ns 85 ns TMS320LC15 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 clock timing tr(MC) tw(MCH) tw(MCP)† tc(MC) X2/CLKIN tw(MCL) tf(MC) tw(CH) td(MCC)† CLKOUT tr(C) tf(C) tw(CL) tc(C) † td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform. IN instruction timing CLKOUT MEN 1 2 tsu(A-MD) 3 PA2-PA0 tsu(D) 4 5 td5 td4 DEN th(D) 6 D15-D0 7 8 Legend: 1. 2. 3. 4. IN Instruction Prefetch Next Instruction Prefetch Address Bus Valid Peripheral Address Valid 5. 6. 7. 8. Address Bus Valid Instruction Valid Data Input Valid Instruction Valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 75 TMS320LC15 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 OUT instruction timing CLKOUT MEN 1 PA2-PA0 3 2 4 5 td6 td7 td9 WE td8 tv 6 D15-D0 td10 7 8 Legend: 1. 2. 3. 4. OUT Instruction Prefetch Next Instruction Prefetch Address Bus Valid Peripheral Address Valid 5. 6. 7. 8. Address Bus Valid Instruction Valid Data Output Valid Instruction Valid external memory read timing tc(C) CLKOUT td2 td3 MEN td1 A11-A0 tsu(A-MD) th(A-WMD) Address Bus Valid tsu(D) Instruction Valid D15-D0 76 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 th(D) TMS320LC15 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 TBLR instruction timing CLKOUT td2 td3 MEN 1 2 td3 3 4 7 8 td1 A11-A0 5 6 th(D) tsu(D) 9 D15-D0 10 11 12 Legend: 1. 2. 3. 4. 5. 6. TBLR Instruction Prefetch Dummy Prefetch Data Fetch Next Instruction Prefetch Address Bus Valid Address Bus Valid 7. 8. 9. 10. 11. 12. Address Bus Valid Address Bus Valid Instruction Valid Instruction Valid Data Input Valid Instruction Valid TBLW instruction timing CLKOUT MEN A11-A0 1 2 4 5 3 6 7 td6 td7 WE td10 td8 tv td9 D15-D0 8 9 10 11 Legend: 1. 2. 3. 4. 5. 6. TBLW Instruction Prefetch Dummy Prefetch Next Instruction Prefetch Address Bus Valid Address Bus Valid Address Bus Valid 7. 8. 9. 10. 11. Address Bus Valid Instruction Valid Instruction Valid Data Output Valid Instruction Valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 77 TMS320LC15 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 reset timing CLKOUT tsu(R) tsu(R) RS tw(R) DEN WE (see MEN Note E) tdis(R) Data In From PC ADDR 0 td11 Data In From PC ADDR PC+1 Data Shown Relative To WE D15-D0 MEN AB = PC+1 AB = Address Bus ADDRESS BUS AB = PC AB = PC = 0 AB = PC+1 NOTES: A. RS forces DEN, WE, and MEN high and places data bus D0 through D15 in a high-impedance state. AB outputs (and program counter) are synchronously cleared to zero after the next complete CLK cycle from RS↓. B. RS must be maintained for a minimum of five clock cycles. C. Resumption of normal program will commence after one complete CLK cycle from RS↑. D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK cycle. E. Diagram shown is for definition purpose only. DEN, WE, and MEN are mutually exclusive. F. During a write cycle, RS may produce an invalid write address. interrupt timing CLKOUT tsu(INT) INT tf(INT) tw(INT) BIO timing CLKOUT tsu(IO) BIO tf(IO) tw(IO) 78 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C16 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 Key Features: TMS320C16 • • • 114-ns Instruction Cycle Time 256 Words of On-Chip Data RAM 256-Word RAM 8K Words of On-Chip Program ROM Interrupt Data (16) 64K Words Total External Memory at Full Speed 8K-Word ROM 8 Level Stack 32-Bit ALU/ACC 32-Bit ALU/Accumulator 8-Level Stack 16 × 16-Bit Multiplier With 32-Bit Product 16-Bit Barrel Shifter Multiplier Address (12) Eight Input and Eight Output Channels Shifters Simple Memory and I/O Interface: — Memory Write Enable Signal MWE — I/O Write Enable Signal IOWE Single 5-V Supply 64-Pin Quad Flatpack (PG Suffix) PG Package (Top View) Operating Free-Air Temperature Range . . . 0°C to 70°C BIO INT MC/MP V SS V DD V DD V DD V DD MEN NC IOEN MWE IOWE • • • • • • GND 64 63 62 61 60 59 58 57 56 55 54 53 52 NC RS X1 X2/CLKIN VSS VSS VSS VSS CLKOUT D15 D14 NC D13 D12 D11 D10 D9 NC NC 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 NC NC A0/PA0 A1/PA1 A2/PA2 A3 A4 A5 A6 VSS A7 A8 A9 A10 A11 A12 A13 A14 NC 20 21 22 23 24 25 26 27 28 29 30 31 32 D8 D7 D6 D5 NC D4 VDD D3 D2 NC D1 D0 A15 • • • • +5 V POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 79 TMS320C16 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 TERMINAL FUNCTIONS PIN NAME DESCRIPTION I/O/Z† NO. A15 MSB A14 A13 32 34 35 A12 A11 A10 A9 36 37 38 39 A8 A7 A6 A5 40 41 43 44 A4 A3 A2/PA2 A1/PA1 45 46 47 48 A0/PA0 49 D15 MSB D14 D13 10 11 13 D12 D11 D10 D9 14 15 16 17 D8 D7 D6 D5 20 21 22 23 D4 D3 D2 D1 25 27 28 30 D0 LSB 31 ADDRESS/DATA BUSES I/O/Z Program memory address bus A15 (MSB) through A0 (LSB) and port addresses PA2 (MSB) through PA0 (LSB). Addresses A15 through A0 are always active and never go to high impedance. During execution of the IN and OUT instructions, pins A2 through A0 carry the port addresses. (Address pins A15 through A3 are always driven low on IN and OUT instruction. I/O/Z Parallel data bus D15 (MSB) through D0 (LSB). The data bus is always in the high-impedance state except when IOWE or MWE are active (low). † Input/Output/High-impedance state. 80 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C16 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 TERMINAL FUNCTIONS (concluded) PIN NAME NO. DESCRIPTION I/O/Z† INTERRUPT AND MISCELLANEOUS SIGNALS BIO 64 I External polling input. Polled by BIOZ instruction. If low, the device branches to the address specified by the instruction. IOEN 54 O Data enable for device input data. When active (low), IOEN indicates that the device will accept data from the data bus. IOEN is active only during the IN instruction. When IOEN is active, MEN, IOWE, and MWE will always be inactive (high). IOWE 52 O Write enable for device output data. When active (low), IOWE indicates that data will be output from the device on the data bus. IOWE is active only during the OUT instruction. When IOWE is active, MEN, IOEN, and MWE will always be inactive (high). INT 63 I External interrupt input. The interrupt signal is generated by applying a negative-going edge to the INT pin. The edge is used to latch the interrupt flag register (INTF) until an interrupt is granted by the device. An active low level will also be sensed. MC/MP 62 I Memory mode select pin. High selects the microcomputer mode, in which 8K words of on-chip program memory are available. A low on MC/MP pin enables the microprocessor mode. In this mode, the entire memory space is external; i.e., addresses 0 through 65535. MEN 56 O Memory enable. MEN is an active (low) control signal generated by the device to enable instruction fetches from program memory. MEN will be active on instructions fetched from both internal and external memory. When MEN is active, MWE, IOWE, and IOEN will be inactive (high). MWE 53 O Write enable for device output data. When active (low), MWE indicates that data will be output from the device on the data bus. MWE is active only during the TBLW instruction. When MWE is active, MEN, IOEN, and IOWE will always be inactive (high). 1, 12, 18, 19, 24, 29, 33, 50, 51, 55 — No connection. NC RS 2 I Schmitt-triggered input for initializing the device. When held active for a minimum of five clock cycles. IOEN, IOWE, MWE, and MEN are forced high; and, the data bus (D15 through D0) is not driven. The program counter (PC) and the address bus (A15 through A0) are then synchronously cleared after the next complete clock cycle from the falling edge of RS. Reset also disables the interrupt, clears the interrupt flag register, and leaves the overflow mode register unchanged. The device can be held in the reset state indefinitely. SUPPLY/OSCILLATOR SIGNALS PIN NAME CLKOUT NO. I/O/Z† DESCRIPTION 9 O System clock output (one-fourth crystal/CLKIN frequency). VDD 26, 57, 58, 59, 60 I 5-V suppy pins. VSS 5, 6, 7, 8, 42, 61 I Ground pins. X1 3 O Crystal output pin for internal oscillator. If the internal oscillator is not used, this pin should be left unconnected. X2/CLKIN 4 I Input pin to the internal oscillator (X2) from the crystal. Alternatively, an input pin for an external oscillator (CLKIN). † Input/Output/High-impedance state. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 81 TMS320C16 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 functional block diagram CLKOUT X1 X2/CLKIN IOEN MWE IOWE MEN BIO MC/MP INT RS Program Bus 16 LSB Controller 16 MUX 16 16 PC (16) 16 Instruction 16 Stack 8 × 16 3 MUX 16 Address MUX A15-A0/ PA2-PA0 Program ROM (8K Words) Program Bus 16 16 Data Bus 7 16 ARP 16 AR0 (16) DP AR1 (16) 8 16 T(16) Shifter (0–16) Multiplier 8 MUX P(32) 32 32 8 MUX Address 32 32 Data RAM (256 Words) ALU (32) Legend: ACC= ARP = AR0 = AR1 = DP = P = PC = T = DATA 32 Accumulator Auxiliary Register Pointer Auxiliary Register 0 Auxiliary Register 1 Data Page Pointer P Register Program Counter T Register ACC (32) 32 32 Shifter (0,1,4) 16 16 Data Bus 82 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 16 16 D15-D0 TMS320C16 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 W Operating free-air temperature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55 °C to 150 °C † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 6: All voltage values are with respect to VSS. recommended operating conditions VCC VSS VIH Supply voltage MIN NOM MAX UNIT 4.75 5 5.25 V Supply voltage 0 High-level input voltage VIL Low-level input voltage IOH IOL High-level output current, all outputs TA Operating free-air temperature All inputs except CLKIN 2 CLKIN 3 V V V All inputs except MC/MP 0.8 V MC/MP 0.6 V Low-level output current 0 –300 µA 2 mA 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage IOH = MAX IOH = 20 µA VOL Low-level output voltage IOL = MAX IOZ Off-state output current VCC = MAX II Input current VCC = VSS to VCC ICC Supply current f = 35 MHz, VCC = 5.25 V Ci Input capacitance Co Output capacitance TYP 2.4 3 MAX UNIT V VCC – 0.4 0.3 0.5 VO = 2.4 V VO = 0.4 V – 20 All inputs except CLKIN ±20 CLKIN ±50 Data bus All others MIN 20 60 75 V µA µA mA 25 f = 1 MHz, all other pins 0 V 15 Data bus 25 All others 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 pF pF 83 TMS320C16 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 internal clock option PARAMETER Crystal frequency, fx C1, C2 TEST CONDITIONS MIN TA = 0°C to 70°C TA = 0°C to 70°C 6.7 NOM MAX UNIT 35.1 MHz 10 pF timing requirements over recommended operating conditions MIN NOM MAX UNIT 28.49 28.57 150 ns Rise time, master clock input 5 10 ns tf(MC) Fall time, master clock input 5 10 ns tw(MCP) Pulse duration, master clock 0.55tc(C) ns tw(MCL) Pulse duration, master clock low 10 ns tw(MCH) Pulse duration, master clock high 10 ns tc(MC) Master clock cycle time tr(MC) 0.45tc(C) switching characteristics over recommended operating conditions PARAMETER MIN NOM MAX UNIT 113.96 114.3 600 ns tc(C) CLKOUT cycle time tr(C) CLKOUT rise time 10 ns tf(C) CLKOUT fall time 8 ns tw(CL) tw(CH) Pulse duration, CLKOUT low 49 47 ns td(MCC) Delay time, CLKIN↑ to CLKOUT↓ 84 Pulse duration, CLKOUT high 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 ns 50 ns TMS320C16 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions PARAMETER td1 MIN Delay time, MEN↑, MWE↑, IOEN↑, IOWE↑, to next address bus valid NOM 0 35 1/4tc(C) – 5 td2 Delay time, CLKOUT↓ to MEN↓ td3 Delay time, CLKOUT↓ to MEN↑ td4 Delay time, CLKOUT↓ to IOEN↓ td5 Delay time, CLKOUT↓ to IOEN↑ td6 Delay time, CLKOUT↓ to MWE↓, IOWE↓ td7 Delay time, CLKOUT↓ to MWE↑, IOWE↑ td8 Delay time, MWE↓, IOwE↓, data bus out valid MAX 1/4tc(C) +12 –3 6 1/4tc(C) – 5 1/4tc(C) +12 –3 6 1/2tc(C) – 5 1/2tc(C) +12 –3 UNIT ns ns ns ns ns ns 6 ns 0 ns 1/4tc(C) – 5 1/4tc(C) td9(CLK) Delay time, CLKOUT↓ to data bus starts to be driven td9(MEN) Delay time, MEN↑, to data bus starts to be driven ns td10(CLK) Delay time, CLKOUT↓ to data bus stops being driven td10(WE) Delay time, MWE↑, IOWE↑, data bus stops being driven tv Data bus OUT valid after MWE↑, IOWE↑ 5 10 ns th(A-WMD) Address bus hold time after MWE↑, MEN↑, IOWE↑, or IOEN↑ 0 2 ns tsu(A-MD) Address bus setup time prior to MEN↓, IOEN↓ 5 ns 15 ns 20 ns ns timing requirements over recommended operating conditions MIN tsu(D) Setup time, data bus valid prior to MEN↑, IOEN↑ th(D) Hold time, data bus held valid after MEN↑, IOEN↑ MAX UNIT 35 ns 0 ns RESET (RS) TIMING switching characteristics over recommended operating conditions PARAMETER td11 Delay time, IOEN↑, IOWE↑, MWE↑, and MEN↑ from RS tdis(R) Data bus disable time after RS MIN MAX 1/2tc(C) +50 1/4tc(C) +50 UNIT MAX UNIT ns ns timing requirements over recommended operating conditions MIN tsu(R) Reset (RS) setup time prior to CLKOUT tw(R) RS pulse duration POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 30 ns 5tc(C) ns 85 TMS320C16 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 INTERRUPT (INT) TIMING timing requirements over recommended operating conditions MIN tf(INT) Fall time, INT tw(INT) Pulse duration, INT tsu(INT) Setup time, INT↓ before CLKOUT↓ MAX 15 UNIT ns tc(C) ns 30 ns IO (BIO) TIMING timing requirements over recommended operating conditions MIN tf(IO) Fall time, BIO tw(IO) Pulse duration, BIO tsu(IO) Setup time, BIO↓ before CLKOUT↓ MAX 15 UNIT ns tc(C) ns 30 ns TIMING DIAGRAMS Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. clock timing tr(MC) tw(MCH) tw(MCP)† tc(MC) X2/CLKIN tw(MCL) tf(MC) tw(CH) td(MCC)† CLKOUT tr(C) tf(C) tw(CL) tc(C) † td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform. 86 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C16 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 memory read timing tc(C) CLKOUT td2 td3 MEN tsu(A-MD) td1 A15-A0 th(A-WMD) Address Bus Valid tsu(D) th(D) Instruction Input Valid D15-D0 IN instruction timing CLKOUT MEN 1 2 tsu(A-MD) A15-A0 3 4 5 tsu(D) td4 td5 IOEN th(D) D15-D0 6 7 8 Legend: 1. 2. 3. 4. IN instruction prefetch Next instruction prefetch Address bus valid Peripheral address valid 5. 6. 7. 8. Address bus valid Instruction input valid Data input valid Instruction input valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 87 TMS320C16 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 OUT instruction timing CLKOUT MEN 1 2 td6 3 A15-A0 4 5 td8 td7 IOWE td10(WE) td9(MEN) td9(CLK) D15-D0 tv 6 td10(CLK) 7 8 Legend: 1. 2. 3. 4. OUT instruction prefetch Next instruction prefetch Address bus valid Peripheral address valid 5. 6. 7. 8. Address bus valid Instruction valid Data output valid Instruction valid TBLR instruction timing CLKOUT td2 td3 MEN td1 A15-A0 th(D) tsu(D) D15-D0 TBLW instruction timing CLKOUT MEN td6 A15-A0 td8 td7 MWE td10(WE) td9(MEN) td9(CLK) D15-D0 88 tv 6 POST OFFICE BOX 1443 7 • HOUSTON, TEXAS 77001 td10(CLK) 8 TMS320C16 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 reset timing CLKOUT tsu(R) tsu(R) RS tw(R) IOEN, IOWE (see MEN, MWE Note E) D15-D0 tdis(R) Data Out Data In From PC ADDR 0 td11 Data In From PC ADDR PC+1 Data Shown Relative To IOWE MEN AB = PC+1 AB = Address Bus Address Bus AB = PC AB = PC = 0 AB = PC+1 NOTES: A. RS forces IOEN, IOWE, MWE, and MEN high and places data bus D0 through D15 in a high-impedance state. AB outputs (and program counter) are synchronously cleared to zero after the next complete CLK cycle from RS↓. B. RS must be maintained for a minimum of five clock cycles. C. Resumption of normal program will commence after one complete CLK cycle from RS↑. D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK cycle. E. Diagram shown is for definition purpose only. IOEN, IOWE, MWE, and MEN are mutually exclusive. F. During a write cycle, RS may produce an invalid write address. interrupt timing CLKOUT tsu(INT) INT tf(INT) tw(INT) BIO timing CLKOUT tsu(IO) BIO tf(IO) tw(IO) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 89 TMS320C16 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 design considerations for interfacing to SRAM, EPROM and peripherals The ′C16 differs somewhat from the other members of the ′C1x family of digital signal processors (DSPs). Additional control signals are available for easier interface to external memory or peripherals, and the memory write cycle timings have been changed. The discussion here will center around changes in tv and its impact upon SRAM, EPROM and peripherals/latches interfaces. Access time requirements for interface may be defined relative to : 1. Valid address (ta); 2. MEN/IOEN, [(ta(MEN)]; Figure 11 and the following examples summarize these timings at 35 MHz CLKIN. tc(C) tw(CH) tf(C) CLKOUT ta(CLKOUT) td2 ta(MEN) MEN td1 ta A15-A0 tsu(D) D15-D0 Figure 11. where: ta ta(MEN) : (access time from address valid) = tc(C) – td1 – tsu(D) = 44.3 ns : (access time from MEN valid) = tc(C) – td2 – tsu(D) + td3 = 35.73 ns and where (for 35 MHz CLKIN): tc(C) = 114.3 ns td1 = 35 ns td2 = [1/4 × (114.3) + 12] ns tsu(D) = 35 ns tw(CH) = 47 ns nominal tf(C) = 8 ns nominal 90 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C16 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 In addition to the above timings, tv must be taken into account. tv is the time that the data bus is guaranteed to be held after the rising edge of MWE or IOWE. In other ′C1x devices, the value of tv was referenced to CLKOUT↓ and not WE↑ (see Figure 12). For the ′C16, tv is a minimum of 5 ns. This implies that MWE and IOWE must be tied directly to the external device. If required, decode logic must be added to an input other than the read/write input — for example, the chip select on SRAMs. If the external device does not have two inputs, then transparent latches must be added to extend the time data is held on the data bus. These latches must be off the bus prior to the next instruction (see Figure 12). CLKOUT MWE or IOWE tv td10 D15-D0 Figure 12. where: tv = 5 ns (min) td10 = 15 ns (max) There is a potential for bus conflict on the prefetch and execution of a TBLW or an OUT instruction. Figure 13 details the timings to be considered. In addition to the timings for the ′C16, timing definitions for interface are also included. Dummy Prefetch Cycle TBLW or OUT Execution CLKOUT tddeco MEN tdmemh CE D15-D0 Memory Driven Data td9(MEN) tconf D15-D0 DSP Driven Data Figure 13. where: POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 91 TMS320C16 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 tconf (data bus conflict time) = tddeco + tdmemh – td9(MEN) with: tddeco tdmemh td9 td9 : decode delay time to make the CE or OE signal : memory data hold time from CE or OE : delay time, MEN to data bus starts being driven : (at 35 MHz CLKIN) = [1/4tc(C)] = [1/4(114.3)] = 28.58 ns If tconf is less than or equal to zero, data bus conflict does not occur. If tconf is greater than zero, data conflict occurs. Note that the following discussion is for CLKIN of 35 MHz. static memory with output enable and write enable/chip select The following SRAMs are able to interface directly to the ′C16, needing only to directly connect the ′C16 memory control signals MEN and MWE to the memory. Device select decode is accomplished with address decode and then input to the device chip select. PRODUCT TC55645-35 TC55328-35 TMS6789-35 TC5588-35 TMS6716-35 tdmemh tddeco 0 0 0 0 0 15 15 8 10 10 tdconf UNITS –13.58 –13.58 –20.58 –18.58 –18.58 ns ns ns ns ns MWE WE MEN OE SRAM With OE TMS320C16 A15-AXX CS ALS138 (Decoder) ADDR DATA D15-D0 Figure 14. 92 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C16 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 static memory with chip enable and write enable Without a separate output enable, a faster SRAM is required. Logic is added to decode address and memory control to perform a read/write cycle. The MWE signal is directly connected to the WE input of the SRAM to meet the tv specification (see Figure 15). Product CY7C164-25 tddeco tdmemh 7.5 10 tdconf – 11.08 Programmable Logic MWE ns WE 7.5 ns MEN Units CE TMS320C16 SRAM With CE A15-AXX ADDR DATA D15-D0 Figure 15. EPROM interface The following high-speed EPROMs can be used directly: Product CY7C291-35 TMS27C291-35 tddeco tdmemh tdconf Units 0 0 25 25 – 3.58 – 3.58 ns ns MEN CS1 VCC Fast EPROM TMS27C291-35 TMS320C16 A15-AXX CS2 Decoder 7.5 ns CS3 ADDR DATA D15-D0 Figure 16. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 93 TMS320C16 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 interfacing latches to the TMS320C16 As with the previous devices, the memory control signal must be directly connected to the latch and the latch needs to have a separate chip select. There are several devices with this feature, including the SN74ALS996. The SN74ALS996 is an 8-bit D-type edge-triggered read-back latch with three-state outputs, connected to the ′C16 as illustrated in Figure 17. D15-D0 D15-D0 IOWE CLK IOEN RD TMS320C16 A2 ALS 138 Decoder A1 EN A0 Figure 17. 94 ALS996A x 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C17, TMS320E17, TMS320LC17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 Key Features: TMS320C17/E17/LC17/P17 • • • • • • Data (16) 278-ns Instruction Cycle Timing (TMS320LC17) ′320C17 or ′320E17 256 Words of On-Chip Data RAM 4K Words of On-Chip Program ROM (TMS320C17/LC17) Coprocessor Interface Serial Interface µ-Law/A-Law Hardware Address (3) Timer 4K Words of On-Chip Program EPROM (TMS320E17/P17) • One-Time Programmable (OTP) Windowless EPROM Version Available (TMS320P17) EPROM Code Protection for Copyright Security Dual-Channel Serial Port for Full-Duplex Serial Communication • Serial Port Timer for Standalone Serial Communication • On-Chip Companding Hardware for µ-law/A-law PCM Conversions • Device Packaging: — 40-Pin DIP (All Devices) — 44-Lead PLCC (TMS320C17/LC17/P17 — 44-Lead CER-QUAD (TMS320E17) 3.3 -V Low-Power Version Available (TMS320LC17) Operating Free-Air Temperature Range . . . 0°C to 70°C 16-Bit Coprocessor Interface for Common 4/8/16/32-Bit Microcomputers/Microprocessors TMS320C17/E17/LC17/P17 N/JD Package TMS320C17, TMS320E17 FN/FZ Packages (Top View) (Top View) PA1/RBLE PA0/HI/LO MC RS EXINT CLKOUT X1 X2/CLKIN BIO VSS D8/LD8 D9/LD9 D10/LD10 D11/LD11 D12/LD12 D13/LD13 D14/LD14 D15/LD15 D7/LD7 D6/LD6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PA2/TBLF FSR FSX FR DX1 DX0 SCLK DRI DEN/RD WE/RD VCC DR0 XF MC/PM D0/LD0 D1/LD1 D2/LD2 D3/LD3 D4/LD4 D5/LD5 POST OFFICE BOX 1443 PAO/HI/LO PA1/RBLE VSS PA2/TBLF FSR FSX FR DX1 • • Dua-Channel Serial Port Interrupt EXINT RS MC • 200-ns Instruction Cycle Timing (TMS320C17/E17/P17) 6 5 4 3 2 1 44 43 42 41 40 CLKOUT X1 X2/CLKIN BIO NC VSS D8 D9 D10 D11 D12 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 DX0 SCLK DR1 DEN/RD WE/WR VCC DR0 XF MC/PM D0/LD0 VSS 18 19 20 21 22 23 24 25 26 27 28 VSS D13/LD13 D14/LD14 D15/LD15 D7/LD7 D6/LD6 D5/LD5 D4LD4 D3/LD3 D2/LD2 D1/LD1 • • HOUSTON, TEXAS 77001 95 TMS320C17, TMS320E17, TMS320LC17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 architecture The ′C17/E17/LC17/P17 consists of five major functional units: the ′C15 microcomputer, a system control register, a full-duplex dual-channel serial port, companding hardware, and a coprocessor port. Three of the I/O ports are used by the serial port, companding hardware, and the coprocessor port. Their operation is determined by the 32 bits of the system control register (see Table 6 for the control register bit definitions). Port 0 accesses control register 0 and consists of the lower 16 register bits (CR15-CR0), and is used to control the interrupts, serial port connections, and companding hardware operation. Port 1 accesses control register 1, consisting of the upper 16 control bits (CR31-CR16), as well as both serial port channels, the companding hardware, and the coprocessor port channels. Communication with the control register is via IN and OUT instructions to ports 0 and 1. Interrupts fully support the serial port interface. Four maskable interrupts (EXINT, FR, FSX, and FSR) are mapped into I/O port 0 via control register 0. When disabled, these interrupts may be used as single-bit logic inputs polled by software. serial port The dual-channel serial port is capable of full-duplex serial communication and offers direct interface to two combo-codecs. Two receive and two transmit registers are mapped into I/O port 1, and operate with 8-bit data samples. Internal and external framing signals for serial port transfers (MSB first) are selected via the system control register. The serial port clock, SCLK, provides the bit timing for transfers with the serial port, and may be either an input or output. As an input, an external clock provides the timing for data transfers and framing pulse synchronization. As an output, SCLK provides the timing for standalone serial communication and is derived from the ′C17/E17/P17 system clock, X2/CLKIN, and system control register bits CR27-CR24 (see Table 7 for the available divide ratios). The internal framing (FR) pulse frequency is derived from the serial port clock (SCLK) and system control register bits CR23-CR16. This framing pulse signal provides framing pulses for combo-codecs, for a sample clock for voice-band systems, or for a timer used in control applications. µ-law/A-law companding hardware The ′C17/E17/LC17/P17 features hardware companding logic and can operate in either µ-law or A-law format with either sign-magnitude or twos-complement numbers. Data may be companded in either a serial mode for operation on serial port data or a parallel mode for computation inside the device. The companding logic operation is selected through CR14. No bias is required when operating in twos-complement. A bias of 33 is required for sign-magnitude in µ-law companding. Upon reset, the device is programmed to operate in sign-magnitude mode. This mode can be changed by modifying control bit 29 (CR29) in control register 1. For further information on companding, see the TCM29C13/TCM29C14/TCM29C16/TCM29C17 Combined Single-Chip PCM Codec and Filter Data Sheet, and the application report, “Companding Routines for the TMS32010/TMS32020,” in the book Digital Signal Processing Applications with the TMS320 Family (SPRA012A), both documents published by Texas Instruments. In the serial mode, sign-magnitude linear PCM (13 magnitude bits plus 1 sign bit for µ-law format or 12 magnitude bits plus 1 sign bit for A-law format) is compressed to 8-bit sign-magnitude logarithmic PCM by the encoder and sent to the transmit register for transmission on an active framing pulse. The decoder converts 8-bit sign-magnitude log PCM from the serial port receive registers to sign-magnitude linear PCM. In the parallel mode, the serial port registers are disabled to allow parallel data from internal memory to be encoded or decoded for computation inside the device. In the parallel encode mode, the encoder is enabled and a 14-bit sign-magnitude value written to port 1. The encoded value is returned with an IN instruction from port 1. In the parallel decode mode, the decoder is enabled and an 8-bit sign-magnitude log PCM value is written to port 1. On the successive IN instruction from port 1, the decoded value is returned. At least one instruction should be inserted between an OUT and the successive IN when companding is performed with twos-complement values. 96 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C17, TMS320E17, TMS320LC17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 Table 6. Control Register Configuration FR Pulse Widt h Port 1 Port 0 Frame Counter Modulus Interrupt Mask Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 I/O Control Serial Clock Prescale Control 9 8 7 6 5 4 3 Serial-Port Configuration Companding Hardware Control 2 1 0 Interrupt Flags Reserved BIT 0 1 DESCRIPTION AND CONFIGURATION EXINT Interrupt flag† FSR interrupt flag† 3 FSX interrupt flag† FR interrupt flag† 4 EXINT interrupt enable mask. When set to logic 1, an interrupt on EXINT activates device interrupt circuitry. 5 FSR interrupt enable mask. Same as EXINT control. 6 FSX interrupt enable mask. Same as EXINT control. 7 FR interrupt enable mask. Same as EXINT control. 8 Port 1 configuration control: 0 = port 1 connects to either serial-port registers or companding hardware. 1 = port 1 accesses CR31-CR16. 9 External framing enable: 0 = serial-port data transfers controlled by active FR. 1 = serial-port data transfers controlled by active FSX/FSR. 10 XF external logic output flag latch 11 0 = Parallel companding mode; serial port disabled. Serial-port enable: 1 = serial companding mode; serial port registers enabled. 12 µ-law/A-law encoder enable: 0 = disabled. 1 = data written to port 1 is µ-law or A-law encoded. 13 µ-law/A-law decoder enable: 0 = disabled. 1 = data written to port 1 is µ-law or A-law decoded. 14 µ-law/A-law decoder encode/decoded select: 2 0 = companding hardware performs µ-law conversion. 1 = companding hardware performs A-law conversion. 23-16 0 = SCLK is an output, derived from the prescaler in timing logic. Serial clock control: 1 = SCLK is an input that provides the clock for serial port and frame counter in timing logic. Frame counter modulus. Controls FR frequency = SCLK/(CNT + 2) where CNT is binary value fo CR23-CR16‡ 27-24 SCLK prescale cotnrol bits. (See Table 7 for divide ratios.) 15 28 FR pulse-width control: 29 30 31 0 = fixed-data rate; FR is 1 SCLK cycle wide. 1 = variable-data rate; FR is 8 SCLK cycles wide. 0 = sign-magnitude companding 1 = twos-complement companding Two’s-complement µ-law/A-law conversion enable: 0 = 8-bit byte length 1 = 16-bit word length 8/16-bit length coprocessor mode select: Reserved for future expansion: Should be set to zero. † Interrupt flag is cleared by writing a logic 1 to the bit with an OUT instruction to port 0. ‡ All ones in CR23-CR16 indicate a degenerative state and should be avoided. Bits are operational whether SCLK is an input or an output. CNT must be greater than 7. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 97 TMS320C17, TMS320E17, TMS320LC17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 Table 7. Serial Clock (SCLK) Divide Ratios (X2/CLKIN = 20.48 MHz) CR27 CR26 CR25 CR24 DIVIDE RATIO SCLK FREQUENCY UNIT 0 0 0 0 32 0.640 MHz 0 0 0 1 28 0.731 MHz 0 0 1 0 24 0.853 MHz 0 1 0 0 20 1.024 MHz 1 0 0 0 16 1.280 MHz 1 0 0 1 14 1.463 MHz 1 0 1 0 12 1.706 MHz 1 1 0 0 10 2.048 MHz The specification for µ-law and A-law log PCM coding is part of the CCITT G.711 recommendation. The following diagram shows a ′C17/E17/P17 interface to two codecs as used for µ-law or A-law companding format. TMS320C17/E17/P17 TCM29C13 VSS DX0 PCM In DR0 PCM Out SCLK +5 V VCC Analog Out Analog In CLKR/X FR FSX FSR MC MC/PM TCM29C13 X2 DX1 PCM In DR1 PCM Out X1 Analog Out Analog In CLKR/X FSX FSR coprocessor port The coprocessor port, accessed through I/O port 5 using IN and OUT instructions, provides a direct connection to most 4/8-bit microcomputers and 16/32-bit micorprocessors. The coprocessor interface allows the ′C17/E17/P17 to act as a peripheral (slave) microcomputer to a microprocessor, or a master to a peripheral microcomputer such as TMS7042. The coprocessor port is enabled by setting MC/PM and MC low. The microcomputer mode is enabled by setting these two pins high. (Note that MC/PM ≠ MC is undefined.) In the microcomputer mode, the 16 data lines are used for the 6 parallel 16-bit I/O ports. In the coprocessor mode, the 16-bit coprocessor port is reconfigured to operate as a 16-bit latched bus interface. Control bit 30 (CR30) in control register 1 is used to configure the coprocessor port to either an 8-bit or a 16-bit length. When CR30 is high, the coprocessor port is 16 bits wide thereby making all 16 bits of the data port available for 16-bit transfers to 16 and 32-bit microprocessors. When CR30 is low, the port is 8-bits wide and mapped to the low byte of the data port for interfacing to 8-bit microcomputers. When operating in the 8-bit mode, both halves of the 16-bit latch can be addressed using the HI/LO pin, thus allowing 16-bit transfers over 8 data lines. When not in the coprocessor mode, port 5 can be used as a generic I/O port. 98 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C17, TMS320E17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 coprocessor port (continued) The external processor recognizes the coprocessor interface in which both processors run asynchronously as a memory-mapped I/O operation. The external processor lowers the WR line and places data on the bus. It next raises the WR line to clock the data into the on-chip latch. The rising edge of WR automatically creates an interrupt to the ′C17/E17/P17, and the falling edge of WR clears the RBLE (receive buffer latch empty) flag. When the ′C17/E17/P17 reads the coprocessor port, it causes the RBLE signal to transition to a logic low state that clears the data in the latch, and allows the interrupt condition to be cleared internally. Likewise, the external processor reads form the latch by driving the RD line active low, thus enabling the output latch to drive the latched data. When the data has been read, the external device will again bring the RD line high. This activates the BIO line to signal that the transfer is complete and the latch is available for the next transfer. The falling edge of RD resets the TBLF (transmit buffer latch full) flag. Note that the EXINT and BIO lines are reserved for coprocessor interface and cannot be driven externally when in the coprocessor mode. An example of the use of a coprocessor interface is shown in Figure 18, in which the ′C17/E17/P17 are DSPs interfaced to the TMS70C42, an 8-bit microcontroller. TMS320C17/E17/P17 MC MC/PM HI/LO CLKOUT WR RBLE TMS70C42 3 27 2 6 17 31 7 1 6 32 9 40 8 19 19 20 20 21 21 22 22 23 23 24 24 25 26 26 27 RD TBLF LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 XTAL2 A1 A0 A3 A2 D7 D6 D5 D4 D3 D2 D1 D0 Figure 18. Coprocessor Interface POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 99 TMS320C17, TMS320E17, TMS320LC17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 TERMINAL FUNCTIONS† NAME I/O‡ DEFINITION BIO CLKOUT D15/LD15-D0/LD0 I O I/O External polling input System clock output, 1/4 crystal/CLKIN frequency 16-bit parallel data bus/data lines for coprocessor latch DEN/RD DR1, DR0 DX1, DX0 EXINT I/O I O I Data enable for device input data/external read for output latch Serial-port receive-channel inputs Serial-port transmit-channel outputs External interrupt input FR FSR FSX MC O I I I Internal serial-port framing output External serial-port receive framing input External serial-port transmit framing input Microcomputer select (must be same state as MC/PM) MC/PM PA0/HI/LO PA1/RBLE PA2/TBLF I I/O O O Microcomputer/peripheral coprocessor select (must be same state as MC) I/O port address output/latch byte select pin I/O port address output/receive buffer latch empty flag I/O port address output/transmit buffer latch full flag RS SCLK VCC VSS I I/O I I Reset for initializing the device Serial-port clock + 5 V Supply Ground WE/WR X1 X2/CLKIN XF O O I O Write enable for device output data/external write for input latch Crystal output for internal oscillator Crystal input for internal oscillator or external oscillator system clock input External-flag output pin † See EPROM programming section. ‡ Input/Output/High-impedance state. 100 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C17, TMS320E17, TMS320LC17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 functional block diagram CLKOUT FSR INT/EXINT X2/CLKIN X1 Program Bus 16 Controller MC MC/PM WR/WE RD/DEN BIO RS HI/LO RBLE TBLF FSX FR Interrupt Latch and Multiplexer 12 LSB MUX 12 12 12 Serial-port Timing and Framing Control PC (12) 12 Instruction 16 Stack 4 × 12 3 Program ROM/EPROM (4K Words) D15-D0 MUX MUX 12 PA2–PA0 SCLK MUX Address 3 Data Latch Data Latch Program Bus 16 16 MUX Data Bus 16 7 16 16 16 16 16 System Control 16 AR0 (16) ARP DP AR1 (16) T(16) Shifter (0–16) 16 Register 16 16 Multiplier 8 XF 8 µ-Law/A-Law 16 Encoder P(32) 8 MUX 14 32 8 32 Address 8 µ-Law/A-Law MUX Decoder MUX 8 32 Data RAM (256 Words) 8 32 8 Data 32 Legend: ACC PC ARP P AR0 T AR1 TR DP RR = = = = = = = = = = Accumulator Program Counter Auxiliary Register Pointer P Register Auxiliary Register 0 T Register Auxiliary Register 1 Transmit Register Data Page Pointer Receive Register MUX 8 8 ALU (32) TR0/TS0 DX0 TR1/TS1 DX1 ACC (32) 32 RR0/RS0 DR0 RR1/RS1 DR1 32 Shifter (0,1, 4) 16 16 16 Data Bus POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 101 TMS320C17, TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 electrical specifications This section contains the electrical specifications for all versions of the ′C17/E17/P17 digital signal processors, including test parameter measurement information. Parameters with PP subscripts apply only to the ′E17/P17 in the EPROM programming mode (see Note 11). absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC, except for the ′320LC17 (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Supply voltage range, VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 14 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 W Operating free-air temperature: L suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55 °C to 150 °C † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 6: All voltage values are with respect to VSS. recommended operating conditions VCC Supply voltage VPP VSS Supply voltage (see Note 11) VIH High-level input voltage MIN NOM MAX UNIT EPROM devices 4.75 5 5.25 V All other devices 4.5 5 5.5 V 12.25 12.5 12.75 V Supply voltage 0 All inputs except CLKIN 2 CLKIN 3 All inputs except MC/MP V V V 0.8 V VIL Low-level input voltage 0.6 V IOH IOL High-level output current, all outputs –300 µA Low-level output current (All outputs) 2 mA TA Operating free-air temperature MC/MP L suffix 0 70 °C A suffix – 40 85 °C NOTE 11: VPP can be applied only to programming pins designed to accept VPP as an input. During programming the total supply current is IPP + ICC. 102 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C17, TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 electrical characteristics over specified temperature range (unless otherwise noted) PARAMETER ICC‡ Supply current TEST CONDITIONS MIN TYP† MAX TMS320C17 f = 20.5 MHz, VCC = 5.5 V, TA = 0°C to 70°C 50 65 TMS320E17/P1 7 f = 25.6 MHz, VCC = 5.5 V, TA = – 40°C to 85°C 55 75 UNIT mA † All typical values are at TA = 70°C and are used for thermal resistance calculations. ‡ ICC characteristics are inversely proportional to temperature. For ICC dependance on temperature, frequency, and loading, see Figure 3. CLOCK CHARACTERISTICS AND TIMING The ′C17/E17/P17 can use either its internal oscillator or an external frequency source for a clock. internal clock option The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and should be specified at a load capacitance of 20 pF. PARAMETER Crystal frequency, fx TMS320C17 TMS320E17/P1 7 TEST CONDITIONS MIN TA = 0°C to 70°C TA = – 40°C to 85°C 6.7 20.5 6.7 20.5 C1, C2 TA = 0°C to 70°C NOM MAX 10 UNIT MHz pF external clock option An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left unconnected. The external frequency injected must conform to the specifications listed in the table below. switching characteristics over recommended operating conditions PARAMETER tc(C) TEST CONDITIONS CLKOUT cycle time§ tr(C) CLKOUT rise time tf(C) CLKOUT fall time tw(CL) tw(CH) Pulse duration, CLKOUT low td(MCC) Delay time, CLKIN↑ to CLKOUT↓ MIN 195.12 RL = 825 Ω, CL = 100 pF (see Figure 2) Pulse duration, CLKOUT high 25¶ NOM MAX UNIT 200 ns 10¶ ns 8¶ ns 92¶ 90¶ ns ns 60¶ ns § tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used). ¶ Values derived from characterization data and not tested. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 103 TMS320C17, TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 timing requirements over recommended operating conditions MIN NOM MAX UNIT 50 150 ns Rise time, master clock input 5† 10† ns Fall time, master clock input 5† 10† ns tc(MC) Master clock cycle time tr(MC) tf(MC) tw(MCP) 48.78 0.6tc(MC)† 0.45tc(MC)† Pulse duration, master clock tw(MCL) Pulse duration, master clock low 20† tw(MCH) Pulse duration, master clock high 20† ns ns ns † Values derived from characterization data and not tested. MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions PARAMETER TEST CONDITIONS td1 Delay time, CLKOUT↓ to address bus valid td4 Delay time, CLKOUT↓ to DEN↓ td5 MIN 10† TYP MAX UNIT 50 ns 1/4tc(C) + 15 Delay time, CLKOUT↓ to DEN↑ 1/4tc(C) – 5† –10† Delay time, CLKOUT↓ to WE↓ 1/2tc(C) – 5† 1/2tc(C) + 15 td7 Delay time, CLKOUT↓ to WE↑ –10† td8 Delay time, CLKOUT↓ to data bus OUT valid td9 Time after CLKOUT↓ that data bus starts to be driven td10 Time after CLKOUT↓ that data bus stops bieng driven tv Data bus OUT valid after CLKOUT↓ th(A-WMD) Address hold time after WE↑, or DEN↑ (see Note 14) tsu(A-MD) Address bus setup time prior to DEN↓ td6 RL = 825 Ω CL = 100 pF, (see Figure 2) 15 15 1/4tc(C) + 65 1/4tc(C) – 5† ns ns ns ns ns 1/4tc(C)+70† 1/4tc(C) – 10 0† ns ns ns 2† ns 1/4tc(C) – 45 ns † Values derived from characterization data and not tested. NOTE 14: Address bus will be valid upon WE↑, MEN↑, or DEN↑. timing requirements over recommended operating conditions TEST CONDITIONS tsu(D) Setup time, data bus valid prior to CLKOUT↓ th(D) Hold time, data bus held valid after CLKOUT↓ (see Note 16) RL = 825 Ω, CL = 100 pF (see Figure 2) NOTE 16: Data may be removed from the data bus upon DEN↑ preceding CLKOUT↓. 104 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 MIN NOM MAX UNIT 50 ns 0 ns TMS320C17, TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 RESET (RS) TIMING switching characteristics over recommended operating conditions PARAMETER TEST CONDITIONS td11 Delay time, DEN↑, and WE↑ from RS tdis(R) Data bus disable time after RS td12 Delay time from RS↓ to high-impedance SCLK td13 MIN RL 825 Ω, CL = 100 pF, (see Figure 2) TYP MAX UNIT 1/2tc(C) +50† 1/4tc(C) +50† ns 200† ns 200† ns MAX UNIT Delay time from RS↓ to high-impedance DX1, DX0 ns † Values derived form characterization data and not tested. timing requirements over recommended operating conditions MIN tsu(R) Reset (RS) setup time prior to CLKOUT (see Note 10) tw(R) RS pulse duration NOM 50 ns 5tc(C) ns NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation. INTERRUPT (EXINT) TIMING timing requirements over recommended operating conditions MIN tf(INT) Fall time, EXINT tw(INT) Pulse duration, EXINT tsu(INT) Setup time, EXINT↓ before CLKOUT↓ NOM MAX 15 UNIT ns tc(C) ns 50 ns IO (BIO) TIMING timing requirements over recommended operating conditions MIN tf(IO) Fall time, BIO tw(IO) Pulse duration, BIO tsu(IO) Setup time, BIO↓ before CLKOUT↓ NOM MAX 15 UNIT ns tc(C) ns 50 ns switching characteristics over recommended operating conditions PARAMETER td(XF) TEST CONDITIONS RL 825 Ω, CL = 100 pF, (see Figure 2) Delay time CLOCKOUT↑ to valid XF MIN 5† TYP MAX 115 UNIT ns † Values derived form characterization data and not tested. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 105 TMS320C17, TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 SERIAL PORT TIMING switching characteristics over recommended operating conditions PARAMETER MIN NOM MAX 70 UNIT td(CH-FR) Internal framing (FR) delay from SCLK rising edge td(DX1-XL) DX bit 1 valid before SCLK falling edge 20 ns td(DX2-XL) DX bit 2 valid before SCLK falling edge 20 ns th(DX) DX hold time after SCLK falling edge tc(SCLK)/2 ns ns timing requirements over recommended operating conditions MIN MAX UNIT 4770 ns Serial port clock (SCLK) fall time 30† ns tr(SCLK) Serial port clock (SCLK) rise time 30† ns tw(SCLKL) Serial port clock (SCLK) low-pulse duration (see Note 17) 185 2500 ns tw(SCLKH) Serial port clock (SCLK) high-pulse duration (see Note 17) 185 2500 ns tsu(FS) FSX/FSR setup time before SCLK falling edge 100 ns tsu(DR) DR setup time before SCLK falling edge 20 ns th(DR) DR hold time after SCLK falling edge 20 ns tc(SCLK) tf(SCLK) Serial port clock (SCLK) cycle time (see Note 17) NOM 390 † Values derived from characterization data and not tested. NOTES: 17. Minimum cycle time is 2tc(C) where tc(C) is CLKOUT cycle time. 18. The duty cycle of the serial port clock must be within 45 to 55 percent. COPROCESSOR INTERFACE TIMING switching characteristics over recommended operating conditions PARAMETER td(R-A) MIN NOM MAX UNIT RD low to TBLF high 75 ns td(W-A) WR low to RBLE high 75 ns ta(RD) RD low to data valid 80 ns th(RD) Data hold time after RD high 25 ns timing requirements over recommended operating conditions MIN NOM MAX UNIT th(HL) HI/LO hold time after WR or RD high 25 ns tsu(HL) HI/LO setup time after WR or RD low 40 ns tsu(WR) Data setup time prior to WR high 30 ns th(WR) Data hold time after WR high 25 ns tw(RDL) RD low-pulse duration 80 ns tw(WRL) WR low-pulse duration 60 ns 106 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C17, TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 TIMING DIAGRAMS Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2 volts, unless otherwise noted. clock timing tr(MC) tw(MCH) tw(MCP)† tc(MC) X2/CLKIN tw(MCL) tf(MC) tw(CH) td(MCC)† CLKOUT tr(C) tf(C) tw(CL) tc(C) † td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform. memory read timing tc(C) CKKOUT td2 td3 MEN tsu(A-MD) th(A–WMD) td1 A11-A0 Address Bus Valid tsu(D) th(D) Instruction Input Valid D15-D0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 107 TMS320C17, TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 IN instruction timing CLKOUT MEN 1 2 tsu(A-MD) 3 A11-A0 tsu(D) 4 5 td5 td4 DEN th(D) 6 D15-D0 7 8 Legend: 1. 2. 3. 4. IN Instruction Prefetch Next Instruction Prefetch Address Bus Valid Peripheral Address Valid 5. 6. 7. 8. Address Bus Valid Instruction Input Valid Data Input Valid Instruction Valid OUT instruction timing CLKOUT MEN 1 A11-A0 3 2 4 5 td6 td7 td9 WE td8 tv 6 D15-D0 td10 7 Legend: 1. 2. 3. 4. 108 OUT Instruction Prefetch Next Instruction Prefetch Address Bus Valid Peripheral Address Valid 5. 6. 7. 8. Address Bus Valid Instruction Input Valid Data Output Valid Instruction Valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 8 TMS320C17, TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 reset timing CLKOUT tsu(R) tsu(R) RS tw(R) DEN WE td11 tdis(R) Data Out D15-D0 td12 SCLK td13 DX1, DX0 PA = Port Address PA2-PA0 Valid PC3 = 3 LSB of PC PC = 0 PA = PC3 = 0 Valid PC = 1 PA = PC3 + 1 = 1 interrupt timing CLKOUT tsu(INT) INT tf(INT) tw(INT) BIO timing CLKOUT tsu(IO) BIO tf(IO) tw(IO) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 109 TMS320C17, TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 XF timing CLKOUT 1 PA2-PA0 td7 td6 WE td9 td10 tv td8 D15-D0 2 3 4 td(XF) XF XF Valid Legend: 1. Port Address Valid 2. Out Opcode Valid 3. Port Data Valid 4. Next Instruction Opcode Valid external framing: transmit timing tr(SCLK) tw(SCLKH) SCLK 1 2 3 8 tsu(FS) tw(SCLKL) tsu(FS) tf(SCLK) FSX th(DX) td(DX1-CL) DX1, DX0 td(DX2-CL) 1 2 3 NOTES: A. Data valid on transmit output until SCLK rises. B. The most significant bit is shifted first. 110 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 8 TMS320C17, TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 external framing: receive timing 1 SCLK 2 3 8 tsu(FS) tsu(FS) FSR tsu(DR) th(DR) DR1, DR0 1 2 3 8 NOTE: The most significant bit is shifted first. internal framing: variable-data rate SCLK td(CH-FR) td(CH-FR) FR td(DX2-CL) td(DX1-CL) 1 DX1, DX0 3 2 8 tsu(DR) th(DR) DR1, DR0 1 2 3 8 NOTE: The most significant bit is shifted first. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 111 TMS320C17, TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 internal framing: fixed-data rate K td(CH-FR) td(CH-FR) R td(DX2-CL) 1 0 2 3 8 td(DX1-CL) th(DR) 1 0 2 3 8 tsu(DR) NOTE: The most significant bit is shifted first. coprocessor timing: external write to coprocessor port HI/LO tw(WRL) tw(WRL) th(HL) tsu(HL) tsu(HL) th(HL) WR th(WR) tsu(WR) Valid DATA IN Valid td(W-A) RBLE Only necessary for operation of 8-bit mode constructing 16-bit data 112 tsu(WR) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 th(WR) TMS320C17, TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 coprocessor timing: external read to coprocessor port HI/LO tw(RDL) tsu(HL) tw(RDL) tsu(HL) th(HL) th(HL) RD th(RD) ta(RD) DATA OUT th(RD) ta(RD) Valid Valid td(R-A) TBLF Only necessary for operation of 8-bit mode constructing 16-bit data POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 113 TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 EPROM PROGRAMMING absolute maximum ratings over specified temperature range (unless otherwise noted)† Supply voltage range, VPP (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 6: All voltage values are with respect to GND. recommended operating conditions MIN VPP Supply voltage (see Note 11) NOM MAX UNIT 12.5 12.75 V NOTE 11: VPP can be applied only to programming pins designed to accept VPP as an input. During programming the total supply current is IPP + ICC. electrical characteristics over specified temperature range (unless otherwise noted) PARAMETER IPP1 IPP2 TEST CONDITIONS VPP supply current VPP supply current (during program pulse) MIN VPP = VCC = 5.5 V VPP = 12.75 V, VCC = 5.5 V TYP† 30 MAX UNIT 100 µA 50 mA recommended timing requirements for programming, TA = 25°C, VCC = 6 V, VPP = 12.5 V, (see Note 13) MIN NOM MAX UNIT 0.95 1 1.05 ms 63 ms tw(IPGM) Initial program pulse duration tw(FPGM) Final pulse duration 3.8 tsu(A) Address setup time 2 µs tsu(E) E setup time 2 µs tsu(G) G setup time 2 0 µs 130‡ ns 150‡ ns tdis(G) Output disable time from G (see Note 15) ten(G) Output enable time from G tsu(D) Data setup time 2 µs tsu(VPP) VPP setup time 2 µs tsu(VCC) VCC setup time 2 µs th(A) Address hold time 0 µs th(D) Data hold time 2 µs † Values derived from characterization data and not tested. NOTES: 13. For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V and VPP = 12.5 V ± 0.25 V during programming. 15. Common test conditions apply for tdis(G) except during programming. 114 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 PROGRAMMING THE TMS320E17/P17 EPROM CELL Each ′E17/P17 devices include a 4K × 16-bit industry-standard EPROM cell for prototyping, early field testing, and low-volume production. In conjunction with this EPROM, the TMS320C17 with a 4K-word masked ROM, then, provides more migration paths for cost-effective production. Note: The TMS320P17 is a one-time programmable (OTP) EPROM device. EPROM adapter sockets are available that provide pin-to-pin conversions for programming any ′E17/P17 devices. One adapter socket (part number RTC/PGM320C-06), shown in Figure 19, converts a 40-pin DIP into an equivalent 28-pin device. Another socket (part number RTC/PGM320C-06), not shown, permits 44- to 28-pin conversion. Figure 19. EPROM Adapter Socket (40-Pin to 28-Pin DIP Conversion) Key features of the EPROM cell include the normal programming operation as well as verification. The EPROM cell also includes a code protection feature that allows code to be protected against copyright violations. The ′E17/P17 EPROM cell is programmed using the same family and device pinout codes as the TMS27C64 8K × 8-bit EPROM. The TMS27C64 EPROM series are unltraviolet-light erasable, electrically programmable, read-only memories, fabricated using HVCMOS technology. They are pin-compatible with existing 28-pin ROMs and EPROMs. These EPROMs operate from a single 5-V supply in the read mode; however, a 12.5-V supply is needed for programming. All programming signals are TTL level. For programming outside the system, existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random. Figure 20 shows the wiring conversion to program the ′E17/P17 using the 28-pin pinout of the TMS27C64. Table 8 on pin nomenclature provides a description of the TMS27C64 pins. The code to be programmed into the device should be in serial mode. The ′E17/P17 devices use 13 address lines to address 4K-word memory in byte format. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 115 TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 Q1 Q2 Q3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TMS27C64 PINOUT A1 A0(LSB) VPP RS EPT A2 A3 A4 A5 A6 A7 A8 CLKIN GND Q1(LSB) Q2 Q3 Q4 Q5 Q6 Q7 Q8(MSB) VCC A9 A10 A11 (MSB)A12 E G PGM TMS320E17/P17 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 3.9 kΩ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC PGM EPT A8 A9 A11 G A10 E Q8 Q7 Q6 Q5 Q4 TMS27C64 PINOUT CAUTION Although acceptable by some EPROM programmers, the signature mode cannot be used on any TMS320E1x device. The signature mode will input a high-level voltage (12.5 Vdc) onto pin A9. Since this pin is not designed for high voltage, the cell will be damaged. To prevent an accidental application of voltage, Texas Instruments has inserted a 3.9 kΩ resistor between pin A9 of the TI programmer socket and the programmer itself. Pin Nomenclature (TMS320E17/P17) NAME A0-A12 CLKIN E EPT G GND PGM Q1-Q8 RS VCC VPP I/O I I I I I I I I/O I I I DEFINITION On-chip EPROM programming address lines Clock oscillator input EPROM chip select EPROM test mode select EPROM read/verify select Ground EPROM write/program select Data lines for byte-wide programming of on-chip 8K bytes of EPROM Reset for initializing the device 5-V power supply 12.5-V power supply Figure 20. TMS320E17/P17 EPROM Programming Conversion to TMS27C64 EPROM Pinout 116 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 Table 8 shows the programming levels required for programming, verifying, reading, and protecting the EPROM cell. Table 8. TMS320E17/P17 Programming Mode Levels SIGNAL NAME TMS320E17 PIN TMS27C64 PIN PROGRAM VERIFY READ PROTECT VERIFY EPROM PROTECT E 25 20 VIL VIL VIL VIL VIH G 24 22 VIH PULSE PULSE VIL VIH PGM 23 27 PULSE VIH VIH VIH VIH VPP 3 1 VPP VPP VCC VCC + 1 VPP VCC 30 28 VCC VCC VCC VCC + 1 VCC + 1 VSS 10 14 VSS VSS VSS VSS VSS CLKIN 8 14 VSS VSS VSS VSS VSS RS 4 14 VSS VSS VSS VSS VSS EPT 5 26 VSS VSS VSS VPP VPP Q1-Q8 11-18 11-13, 15-19 DIN QOUT QOUT Q8=RBIT Q8=PULSE A0-A3 2, 1, 40, 39 10-7 ADDR ADDR ADDR X X A4 38 6 ADDR ADDR ADDR X VIH A5 37 5 ADDR ADDR ADDR X X A6 36 4 ADDR ADDR ADDR VIL X A7-A9 35, 34, 29 3, 25, 24 ADDR ADDR ADDR X X A10-A12 28-26 21, 23, 2 ADDR ADDR ADDR X X Legend: VIH = TTL high level; VIL = TTL low level; ADDR = byte address bit VPP = 12.5 V ± 0.25 V; VCC = 5 V ± 0.25 V; X = don’t care PULSE = low-going TTL level pulse; DIN = byte to be programmed at ADDR QOUT = byte stored at ADDR; RBIT = ROM protect bit. programming Since every memory bit in the cell is a logic 1, the programming operation reprograms certain bits to 0. Once programmed, these bits can be erased only by using ultraviolet light. The correct byte is placed on the data bus with VPP set to the 12.5 V level. The PGM pin is then pulsed low to program in the zeroes. erasure Before programming, the device must be erased by exposing it to ultraviolet light. The recommended minimum exposure dose (UV-intensity × exposure-time) is 15 W•s/cm2. A typical 12-mW/cm2, filterless UV lamp will erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After exposure, all bits are in the high state. verify/read To verify correct programming, the EPROM cell can be read using either the verify or read line definitions shown in Table 8 assuming the inhibit bit has not been programmed. program inhibit Programming may be inhibited by maintaining a high level input on the E pin or PGM pin. read The EPROM contents may be read independent of the programming cycle, provided the RBIT (ROM protect bit) has not been programmed. The read is accomplished by setting E to zero and pulsing G low. The contents of the EPROM location selected by the value on the address inputs appear on Q8-Q1. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 117 TMS320E17, TMS320P17 DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 output disable During the EPROM programming process, the EPROM data outputs may be disabled, if desired, by establishing the output disable state. This state is selected by setting G and E pins high. While output disable is selected, Q8-Q1are placed in the high-impedance state. EPROM protection To protect the proprietary algorithms existing in the code programmed on-chip, the ability to read or verify code from external accesses can be completely disabled. Programming the RBIT disables external access of the EPROM cell, making it impossible to access the code resident in the EPROM cell. The only way to remove this protection is to erase the entire EPROM cell, thus removing the proprietary information. The signal requirements for programming this bit are shown in Table 8. The cell can be determined as protected by verifying the programming of the RBIT shown in the table. standard programming procedure Before programming, the device must first be completely erased. The device can then be programmed with the correct code. It is advisable to program unused sections with zeroes as a further security measure. After the programming is complete, the code programmed into the cell should be verified. If the cell passes verification, the next step is to program the ROM protect bit (RBIT). Once the RBIT programming is verified, an opaque label should be placed over the window to protect the EPROM cell from inadvertent erasure by ambient light. At this point, the programming is complete, and the device is ready to be placed into its destination circuit. program cycle timing Verify Program A12-A0 Address Stable Address N+1 VIL tsu(A) Q8-Q1 VIH th(A) Data In Stable Data Out Valid HI-Z tsu(D) VIH/VOH VIL/VOL tdis(G) VPP VPP VCC tsu(VPP) VCC+1 VCC VCC tsu(VCC) VIH E VIL tsu(E) th(D) VIH PGM tsu(G) VIL tw(IPGM) ten(G) tw(FPGM) VIH G VIL 118 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320LC17 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 absolute maximum ratings over specified temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.6 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC to 0.5 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC to 0.5 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mW Air temperature range above operating devices: L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40 °C to 85°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55 °C to +150°C † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 6: All voltage values are with respect to VSS. recommended operating conditions VCC VSS Supply voltage MIN NOM MAX 3.0 3.3 3.6 Supply voltage 0 UNIT V V All inputs except CLKIN 2.0 V CLKIN 2.5 V VIH High-level input voltage VIL IOH Low-level input voltage 0.55 V High-level output current (all outputs) – 300 µA IOL Low-level output current (all outputs) 1.5 mA TA Operating free-air temperature All inputs L version 0 70 °C A version – 40 85 °C MAX UNIT electrical characteristics over specified temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = MAX IOH = 20 µA (see Note 19) VOH High-level output voltage VOL Low-level output voltage IOZ Off-state ouput current II Input current Ci Input capacitance Co IOL = MAX VCC = MAX, TYP§ 2.0 VCC – 0.4¶ V V 0.5 VO = VCC VO = VSS 20 –20 ± 20 VI = VSS to VCC, All inputs except CLKIN VI = VSS to VCC, CLKIN Data bus All others Output capacitance MIN Data bus f = 1 MHz, All other pins 0 V All others ± 50 V µA µA 25¶ 15¶ pF 25¶ 10¶ pF § All typical values are at VCC = 3.3 V, TA = 25°C. ¶ Values derived from characterization data and not tested. NOTE 19: This voltage specification is included for interface to HC logic. All other timing parameters defined in this data sheet are specified for the test load circuit shown in Figure 2. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 119 TMS320LC17 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 TMS320LC17 FN PACKAGE (TOP VIEW) EXINT RS MC PA0/HI/LO PA1/RBLE VSS PA2/TBLF FSR FSX FR DX1 TMS320LC17 N PACKAGE (TOP VIEW) PA1/RBLE PA0/HI/LO MC RS EXINT CLKOUT X1 X2/CLKIN BIO VSS D8/LD8 D9/LD9 D10/LD10 D11/LD11 D12/LD12 D13/LD13 D14/LD14 D15/LD15 D7/LD7 D6/LD6 6 5 4 3 2 1 44 43 42 41 40 CLKOUT X1 X2/CLKIN BIO NC VSS D8/LD8 D9/LD9 D10/LD10 D11/LD11 D12/LD12 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 DX0 SLCK DR1 DEN/RD WE/WR VCC DR0 XF MC/PM D0/LD0 VSS VSS D13/LD13 D14/LD14 D15/LD15 D7/LD7 D6/LD6 D5/LD5 D4/LD4 D3/LD3 D2/LD2 D1/LD1 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PA2/TBLF FSR FSX FR DX1 DX0 SCLK DR1 DEN/RD WE/WR VCC DR0 XF MC/PM D0/LD0 D1/LD1 D2/LD2 D3/LD3 D4/LD4 D5/LD5 electrical characteristics over specified ranges (unless otherwise noted) PARAMETER ICC‡ TEST CONDITIONS Supply current MIN f = 14.4 MHz, VCC = 3.6 V, TA = 0°C to 70°C TYP† MAX 15 20 UNIT mA † All typical values are at TA = 70°C and are used for thermal resistance calculations. ‡ ICC characteristics are inversely proportional to temperature. For ICC dependence on frequency, see Figure 3. clock characteristics and timing The TMS320LC17 can use either its internal oscillator or an external frequency source for a clock. internal clock option The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and be specified at a load capacitance of 20 pF. PARAMETER Crystal frequency fx TEST CONDITIONS MIN TA = – 40°C to 85°C 4.0 C1, C2 120 NOM 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 MAX UNIT 14.4 MHz pF TMS320LC17 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 external clock option An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left unconnected. The external frequency injected must conform to the specifications listed in the table below. switching characteristics over recommended operating conditions PARAMETER tc(C) CLKOUT cycle time§ tr(C) CLKOUT rise time TEST CONDITIONS MIN NOM 277.78 tf(C) CLKOUT fall time tw(CL) Pulse duration, CLKOUT low tw(CH) Pulse duration, CLKOUT high RL = 825 Ω, CL = 100 pF, (see Figure 2) td(MCC) Delay time CLKIN↑ to CLKOUT↓ MAX UNIT 1000 ns 10¶ ns 8¶ ns 131 ns 129 ns 25 75 ns § tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used). ¶ Values derived from characterization data and not tested timing requirements over recommended operating conditions MIN tc(MC) Master clock cycle time NOM 69.5 tr(MC) Rise time, master clock input 5† tf(MC) Fall time, master clock input 5† 0.4 t c(MC)† tw(MCP) Pulse duration, master clock MAX UNIT 150 ns 10† ns 10† ns 0.6 t c(MC)† ns tw(MCL) Pulse duration, master clock low at tc(MC) min 30 ns tw(MCH) Pulse duration, master clock high at tc(MC) min 30 ns † Values derived from characterization data and not tested. MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions PARAMETER TEST CONDITIONS td1 td4 Delay time CLKOUT↓ to address bus valid td5 td6 Delay time CLKOUT↓ to DEN↑ td7 td8 Delay time CLKOUT↓ to WE↑ td9 td10 Time after CLKOUT↓ that data bus starts to be driven Delay time CLKOUT↓ to DEN↓ Delay time CLKOUT↓ to WE↓ RL = 825 Ω, CL = 100 pF, (see Figure 2) Delay time CLKOUT↓ to data bus OUT valid MAX UNIT 100 ns 1/4 tc(C)–5† 1/4 tc(C)+25 –10† 30 † 1/2 tc(C)–5 1/2 tc(C)+25 ns –10† Time after CLKOUT↓ that data bus stops being driven Address bus setup time or DEN↓ 0 ns ns 1/4 tc(C)+130 ns ns 1/4 tc(C)+90 1/4 tc(C)–10 0† ns 30 1/4 tc(C)–5 † tv Data bus OUT valid after CLKOUT↓ th(A-WMD) Address hold time after WE↑, MEN↑, or DEN↑ (see Note 14) tsu(A-MD) MIN 10† ns ns ns ns † Values derived from characterization data and not tested. NOTE 14: Address bus will be valid upon WE↑, MEN↑, or DEN↑. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 121 TMS320LC17 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 timing requirements over recommended operating conditions TEST CONDITIONS tsu(D) Setup time data bus valid prior to CLKOUT↓ th(D) Hold time data bus held valid after CLKOUT↓ (see Note 9) RL = 825 Ω, CL = 100 pF, (see Figure 2) MIN NOM MAX UNIT 80 ns 0 ns NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓. RESET (RS) TIMING switching characteristics over recommended operating conditions PARAMETER TEST CONDITIONS td11 Delay time DEN↑, WE↑, and MEN↑ from RS tdis(R) Data bus disable time after RS td12 Delay time from RS↓ to high-impedance SCLK td13 MIN RL = 825 Ω, CL = 100 pF, (see Figure 2) NOM MAX UNIT 1/2tc(C)+75 ns 1/4tc(C)+75 200† ns 200† ns Delay time from RS↓ to high-impedance DX1, DX0 ns † These values were derived from characterization data and not tested. timing requirements over recommended operating conditions MIN tsu(R) Reset (RS) setup time prior to CLKOUT (see Note 10) tw(R) RS pulse duration NOTE 10: NOM MAX 85 UNIT ns 5tc(C) ns RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation. INTERRUPT (EXINT) TIMING timing requirements over recommended operating conditions MIN tf(INT) Fall time EXINT tw(INT) Pulse duration EXINT tsu(INT) Setup time EXINT↓ before CLKOUT↓ NOM MAX 15 UNIT ns tc(C) ns 85 ns I/O (BIO) TIMING timing requirements over recommended operating conditions MIN tf(IO) Fall time BIO tw(IO) Pulse duration BIO tsu(IO) Setup time BIO↓ before CLKOUT↓ 122 NOM MAX 15 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 UNIT ns tc(C) ns 85 ns TMS320LC17 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 I/O (BIO) TIMING switching characteristics over recommended operating conditions PARAMETER td(XF) TEST CONDITIONS RL = 825 Ω, CL = 100 pF, (see Figure 2) Delay time CLKOUT↓ to valid XF MIN NOM 5† MAX 115 UNIT ns † Values derived from characterization data and not tested. SERIAL PORT TIMING switching characteristics over recommended operating conditions MIN td(CH-FR) NOM Internal framing (FR) delay from SCLK rising edge MAX UNIT 120 ns td(DX1-CL) DX bit 1 valid before SCLK falling edge 20 ns td(DX2-CL) DX bit 2 valid before SCLK falling edge 20 ns th(DX) DX hold time after SCLK falling edge tc(SCLK)/2 ns timing requirements over recommended operating conditions MIN MAX UNIT 8000 ns Serial port clock (SCLK) fall time 30† ns tr(SCLK) Serial port clock (SCLK) rise time 30† ns tw(SCLK) Serial port clock (SCLK) low, pulse duration§ 250 4400 ns tw(SCLKH) Serial port clock (SCLK) high, pulse duration§ 250 4400 ns tsu(FS) FSX/FSR setup time before SCLK falling edge 130 ns tsu(DR) DR setup time before SCLK falling edge 20 ns th(DR) DR hold time after SCLK falling edge 20 ns tc(SCLK) tf(SCLK) Serial port clock (SCLK) cycle time‡ 555 NOM † Values derived from characterization data and not tested. ‡ Minimum cycle time is 2tc(C) where tc(C) is CLKOUT cycle time. § The duty cycle of the serial port clock must be within 45 to 55%. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 123 TMS320LC17 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 COPROCESSOR INTERFACE TIMING switching characteristics over recommended operating conditions MIN NOM MAX UNIT td(R-A) RD low to TBLF high 150 ns td(W-A) WR low to RBLF high 150 ns ta(RD) RD low to data valid 150 ns th(RD) Data hold time after RD high MAX UNIT 25 timing requirements over recommended operating conditions MIN NOM th(HL) HI/RD hold time after WR or RD high 25 ns tsu(HL) HI/RD setup time prior to WR or RD low 40 ns tsu(WR) Data setup time prior to WR high 50 ns th(WR) Data hold time after WR high 35 ns tw(RDL) Pulse duration, RD low 150 ns tw(WRL) Pulse duration, WR low 150 ns 124 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320LC17 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 clock timing tr(MC) tw(MCH) tw(MCP)† tc(MC) X2/CLKIN tw(MCL) tf(MC) tw(CH) td(MCC)† CLKOUT tr(C) tf(C) tw(CL) tc(C) † td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform. IN instruction timing CLKOUT MEN 1 2 tsu(A-MD) 3 PA2-PA0 tsu(D) 4 5 td5 td4 DEN th(D) 6 D15-D0 7 8 Legend: 1. 2. 3. 4. IN Instruction Prefetch Next Instruction Prefetch Address Bus Valid Peripheral Address Valid 5. 6. 7. 8. Address Bus Valid Instruction Valid Data Input Valid Instruction Valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 125 TMS320LC17 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 OUT instruction timing CLKOUT MEN 1 PA2-PA0 3 2 4 5 td6 td7 td9 WE td8 tv 6 D15-D0 td10 7 8 Legend: 1. 2. 3. 4. OUT Instruction Prefetch Next Instruction Prefetch Address Bus Valid Peripheral Address Valid 5. 6. 7. 8. Address Bus Valid Instruction Valid Data Output Valid Instruction Valid reset timing CLKOUT tsu(R) tsu(R) RS tw(R) DEN WE td11 tdis(R) D15-D0 Data Out td12 SCLK td13 DX1, DX0 PA = Port Address PA2-PA0 126 Valid PC = 0 PC3 = 3 LSB of PC PA = PC3 = 0 Valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 PC = 1 PA = PC3 + 1 = 1 TMS320LC17 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 interrupt timing CLKOUT tsu(INT) INT tf(INT) tw(INT) BIO timing CLKOUT tsu(IO) BIO tf(IO) tw(IO) XF timing CLKOUT PA2-PA0 1 td7 td6 WE td9 td10 tv td8 D15-D0 2 3 4 td(XF) XF Valid XF Legend: 1. Port Address Valid 2. Out Opcode Valid 3. Port Data Valid 4. Next Instruction Opcode Valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 127 TMS320LC17 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 external framing: transmit timing tr(SCLK) tw(SCLKH) SCLK 1 2 3 8 tsu(FS) tw(SCLKL) tsu(FS) tf(SCLK) FSX th(DX) td(DX1-CL) td(DX2-CL) 1 DX1, DX0 2 3 8 NOTES: A. Data valid on transmit output until SCLK rises. B. The most significant bit is shifted first. external framing: receive timing 1 SCLK 2 3 8 tsu(FS) tsu(FS) FSR tsu(DR) th(DR) DR1, DR0 1 2 3 NOTE B: The most significant bit is shifted first. 128 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 8 TMS320LC17 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 internal framing: variable-data rate SCLK td(CH-FR) td(CH-FR) FR th(DX) td(DX2-CL) td(DX1-CL) 1 DX1, DX0 3 2 8 tsu(DR) th(DR) DR1, DR0 1 2 3 8 NOTE: The most significant bit is shifted first. internal framing: fixed-data rate SCLK td(CH-FR) td(CH-FR) FR td(DX2-CL) th(DX) 1 DX1, DX0 3 2 8 td(DX1-CL) th(DR) DR1, DR0 1 2 3 8 tsu(DR) NOTE: The most significant bit is shifted first. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 129 TMS320LC17 DIGITAL SIGNAL PROCESSOR SPRS009C – JANUARY 1987 – REVISED JULY 1991 coprocessor timing: external write to coprocessor port HI/LO tw(WRL) tw(WRL) th(HL) tsu(HL) th(HL) tsu(HL) WR th(WR) tsu(WR) DATA IN Valid th(WR) tsu(WR) Valid td(W-A) RBLE Only necessary for operation of 8-bit mode constructing 16-bit data coprocessor timing: external read to coprocessor port HI/LO tw(RDL) tsu(HL) tw(RDL) tsu(HL) th(HL) th(HL) RD th(RD) ta(RD) DATA OUT Valid Valid td(R-A) TBLF Only necessary for operation of 8-bit mode constructing 16-bit data 130 POST OFFICE BOX 1443 th(RD) ta(RD) • HOUSTON, TEXAS 77001 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 THERMAL RESISTANCE CHARACTERISTICS Commercial Devices Device/Package Thermal Resistance Junction To Case DEVICE RθJC (°C/W) PDIP (N) CDIP (JD) PLCC (FN) TMS320C10 26 17 TMS320C10-14 26 17 TMS320C10-25 26 17 TMS320C14 CLCC (FZ) 11 TMS320E14 8 TMS320P14 11 TMS320C15 26 TMS320C15-25 26 17 17 TMS320E15 8 8 TMS320E15-25 8 8 TMS320LC15 26 17 TMS320P15 13 13 TMS320C16 TMS320C17 QFP (PG) 25 26 TMS320E17 17 8 8 TMS320LC17 26 17 TMS320P17 13 13 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 131 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 THERMAL RESISTANCE CHARACTERISTICS Commercial Devices Device/Package Thermal Resistance Junction To Ambient DEVICE RθJA (°C/W) PDIP (N) CDIP (JD) PLCC (FN) TMS320C10 84 60 TMS320C10-14 84 60 TMS320C10-25 84 60 TMS320C14 CLCC (FZ) 46 TMS320E14 49 TMS320P14 46 TMS320C15 84 TMS320C15-25 84 60 60 TMS320E15 40 64 TMS320E15-25 40 64 TMS320LC15 84 60 TMS320P15 40 55 TMS320C16 TMS320C17 120 84 TMS320E17 132 QFP (PG) 60 40 64 TMS320LC17 84 60 TMS320P17 40 55 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 MECHANICAL DATA 40-pin plastic dual-in-line package 53,1 (2.090) Max 40 21 1 21 Either or Both Index Marks " 0,25 " 0.010) 15,24 (0.600 CL CL 0,51 (0.020) Min 5,08 (0.200) Max Seating Plane 105° 90° 2,92 (0.115) Min 0,457 ± 0,076 (0.018 ± 0.003) 0,28 ± 0,08 (0.011 ± 0.003) 0,84 (0.033) Min 2,54 (0.100) T.P. Pin Spacing (See Note A) 2,41 (0.095) 1,40 (0.055) 1,52 (0.060) Nom ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTE A: Each pin centerline is located within 0,254 (0.010) of its true longitudinal position. 40-pin windowed ceramic dual-in-line package 51,31 (2.020) Max 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 15,0 (0.590) Nom Index Dot CL CL " 0,25 " 0.010) 15,24 (0.600 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 4,70 (0.185) Max 0,508 (0.020) Min 105° 90° 0,25(0.010) Nom Seating Plane " 0,508 " 0.020) 1,27 (0.050 2,54 (0.100) T.P. Pin Spacing (see Note A) " 0,254 " 0.010) 1,27 (0.050 0,457 (0.018 " 0,076 " 0.003) " 0,762 " 0.030) 3,81 (0.150 ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTE A: Each pin centerline is located within 0,254 (0.010) of its true longitudinal position. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 133 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 44-lead plastic chip carrier (FN suffix) 16,66 (0.656) 16,51 (0.650) 17,65 (0.695) 17,40 (0.685) Index Dot 1,14 (0.045) × 45° Typ 4,57 (0.180) 4,19 (0.165) 16,66 (0.656) 16,51 (0.650) 17,65 (0.695) 17,40 (0.685) 3,05 (0.120) 2,29 (0.090) 0,51 (0.020) Min 0,533 (0.021) 0,330 (0.013) 16,00 (0.630) 14,99 (0.590) 1,27 (0.050) Typ ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES 134 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 64-pin quad flat pack (PG suffix) (TMS320C16) 24,0 (0.945) 23,2 (0.913) 20,0 (0.787) Nom 51 33 52 32 18,0 (0.709) 17,2 (0.677) 14,0 (0.552) Nom 64 20 1 19 1,0 (0.039) Typ C L C L 0,20 (0.008) 0,10 (0.004) 0°-10° 0,35 (0.0014) Typ 3,10 (0.122) Max 1,0 (0.040) 0,6 (0.024) 0,1 (0.004) Min ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 135 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 MECHANICAL DATA 68-lead plastic chip carrier package (FN suffix) 1,35 (0.053) 1,19 (0.047) 45 ° 2,79 (0.110) 2,41 (0.095) ÏÏ ÏÏ 0,25 (0.010) R Max in 3 places 24,33 (0.956) 24,13 (0.950) (see Note A) 4,50 (0.177) 4,24 (0.167) 25,27 (0.995) 25,02 (0.985) 23,62 (0.930) 23,11 (0.910) (At Seating Plane) 1,27 (0.050) T.P. (see Note B) 24,33 (0.956) 24,13 (0.950) (see Note A) 0,94 (0.037) R 0,69 (0.027) 1,22 (0.048) 1,07 (0.042) 45 ° 25,27 (0.995) 25,02 (0.985) Seating Plane 0,81 (0.032) 0,66 (0.026) 1,52 (0.060) Min 0,64 (0.025) Min 0,51 (0.020) 0,36 (0.014) Lead Detail NOTES: A. Centerline of center pin, each side, is within 0,10 (0.004) of package centerline as determined by this deminsion. B. Location of each pin is within 0,27 (0.005) of true position with respect to center pin on each side. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES 136 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 MECHANICAL DATA 68-lead ceramic chip carrier package (FZ suffix) 4,57 (0.180) 3,94 (0.155) A (see Note A) A 3,55 (0.140) 3,05 (0.120) B 1.02 (0.040) × 45° 1,27 (0.05) Typ (see Note B) 0,81 (0.032) 0,66 (0.026) B 0,51 (0.020) 0,36 (0.014) 0,64 (0.025) R Max Typ, 3 Places Optional EPROM Window C (at Seating Plane) 1.016 (0.040) Min 3,05 (0.120) 2,29 (0.090) Seating Plane (see Note C) A B C MIN MAX MIN MAX MIN MAX M0-087AA 28 12,32 (0.485) 12,57 (0.495) 10,92 (0.430) 11,56 (0.455) 10,41 (0.410) 10.92 (0.430) M0-087AB 44 17,40 (0.685) 17,65 (0.695) 16,00 (0.630) 16,64 (0.655) 15,49 0.610) 16,00 (0.630) M0-087AD 68 25,02 (0.985) 25,27 (0.995) 23,62 (0.930) 24,26 (0.955) 23.11 (0.910) 23,62 (0.930) NOTES: A. Centerline of center pin each side is within 0,10 (0.004) of package centerline as determined by dimension B. B. Location of each pin is within 0,27 (0.005) of true position with respect to center pin on each side. C. The lead contact points are planar within 0,15 (0.006) ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 137 TMS320C1x DIGITAL SIGNAL PROCESSORS SPRS009C – JANUARY 1987 – REVISED JULY 1991 INDEX accumulator/ALU . . . . . . . . . . . . . . . . . . . . . . 5 key features (TMS320C1x) . . . . . . . . . . . . . . TMS320C10 . . . . . . . . . . . . . . . . . . . . . . . TMS320C14 . . . . . . . . . . . . . . . . . . . . . . . TMS320C15 . . . . . . . . . . . . . . . . . . . . . . . TMS320C16 . . . . . . . . . . . . . . . . . . . . . . . TMS320C17 . . . . . . . . . . . . . . . . . . . . . . . architecture (TMS320C1x family) . . . . . . 5, 6 TMS320C14 . . . . . . . . . . . . . . . . . . . . . . . 32 TMS320C17 . . . . . . . . . . . . . . . . . . . . . . . 96 functional block diagram TMS320C10 . . . . . . . . . . . . . . . . . . . . . . . TMS320C14 . . . . . . . . . . . . . . . . . . . . . . . TMS320C15 . . . . . . . . . . . . . . . . . . . . . . . TMS320C16 . . . . . . . . . . . . . . . . . . . . . . . TMS320C17 . . . . . . . . . . . . . . . . . . . . . . . 13 32 53 82 95 mechanical data . . . . . . . . . . . . . . . 133 – 137 memory (TMS320C1x) . . . . . . . . . . . . . 2, 3, 5 TMS320C10 . . . . . . . . . . . . . . . . . . . . . . . 11 TMS320C14 . . . . . . . . . . . . . . . . . . . . . . . 28 TMS320C15 . . . . . . . . . . . . . . . . . . . . . . . 52 TMS320C16 . . . . . . . . . . . . . . . . . . . . . . . 79 TMS320C17 . . . . . . . . . . . . . . . . . . . . . . . 95 codec interface TMS320C17 . . . . . . . . . . . . . . 3, 6, 96 – 98 companding hardware TMS320C17 . . . . . . . . . . . . . . . . . . 3, 96, 97 control register TMS320C17 . . . . . . . . . . . . . . . . . . . . . . . 97 coprocessor interface . . . . . . . . . . . . . . . . . 98 microcomputer/microprocessor mode . . 5, 33 microcomputer/coprocessor . . . . . . . . . . 7, 98 multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 data memory . . . . . . . . . . . . . . . . . . 2, 3, 5, 33 description TMS320C10 . . . . . . . . . . . . . . . . . . . 2, 3, 11 TMS320C14 . . . . . . . . . . . . . . . 2, 3, 28, 29 TMS320C15 . . . . . . . . . . . . . . . . . . . 2, 3, 52 TMS320LC15 . . . . . . . . . . . . . . . . . . 2, 3, 70 TMS320C16 . . . . . . . . . . . . . . . . . . . 2, 3, 79 TMS320C17 . . . . . . . . . . . . . . . . . . . 2, 3, 95 TMS320LC17 . . . . . . . . . . . . . . . . . 2, 3, 120 package types (TMS320C1x) . . . . . . . . . . . . 4 pinout/nomenclature TMS320C10 . . . . . . . . . . . . . . . . . . . . . 4, 11 TMS320C14 . . . . . . . . . . . . . . . . . . . . . 4, 28 TMS320C15 . . . . . . . . . . . . . . . . . . . . . 4, 52 TMS320LC15 . . . . . . . . . . . . . . . . . . . . 4, 70 TMS320C16 . . . . . . . . . . . . . . . . . . . . . 4, 79 TMS320C17 . . . . . . . . . . . . . . . . . . . . . 4, 95 TMS320LC17 . . . . . . . . . . . . . . . . . . . 4, 120 electrical specifications TMS320C10 . . . . . . . . . . . . . . . . . . . . . . . 14 TMS320C14 . . . . . . . . . . . . . . . . . . . . . . . 35 TMS320C15 . . . . . . . . . . . . . . . . . . . . . . . 55 TMS320LC15 . . . . . . . . . . . . . . . . . . . . . . 69 TMS320C16 . . . . . . . . . . . . . . . . . . . . . . . 83 TMS320C17 . . . . . . . . . . . . . . . . . . . . . . 102 TMS320LC17 . . . . . . . . . . . . . . . . . . . . . 120 serial port TMS320C17/E17 . . . . . . . . . . . . . . . . . 6, 96 shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 terminal functions TMS320C10 . . . . . . . . . . . . . . . . . . . . . . . 12 TMS320C14 . . . . . . . . . . . . . . . . . . . . . . . 30 TMS320C15 . . . . . . . . . . . . . . . . . . . . . . . 54 TMS320C16 . . . . . . . . . . . . . . . . . . . . . . . 80 TMS320C17 . . . . . . . . . . . . . . . . . . . . . . 100 EPROM programming TMS320E14/P14 . . . . . . . . . . . . . . . . . . . 47 TMS320E15/P15 . . . . . . . . . . . . . . . . . . . 65 TMS320E17/P17 . . . . . . . . . . . . . . . . . . 114 thermal data . . . . . . . . . . . . . . . . . 27, 131, 132 timing diagrams TMS320C10 . . . . . . . . . . . . . . . . . . . 23 – 26 TMS320C14 . . . . . . . . . . . . . . . 41 – 46, 51 TMS320C15 . . . . . . . . . . . . . . . 60 – 63, 68 TMS320LC15 . . . . . . . . . . . . . . . . . . 75 – 78 TMS320C16 . . . . . . . . . . . . . . . . . . . 86 – 91 TMS320C17 . . . . . . . . . . . . 107 – 113, 118 TMS320LC17 . . . . . . . . . . . . . . . 125 – 130 framing pulses TMS320C17/LC17/E17/P17 . . . . . . . . . 97 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 33 interfacing to SRAM/EPROM/peripherals TMS320C16 . . . . . . . . . . . . . . . . . . . . . . . 90 I/O channels . . . . . . . . . . . . 2, 3, 6, 28, 79, 95 138 1 11 28 52 79 95 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 PACKAGE OPTION ADDENDUM www.ti.com 5-Dec-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8763308QA ACTIVE CDIP SB JD 40 1 TBD Call TI Level-NC-NC-NC 5962-8763308YA ACTIVE JLCC FJ 44 1 TBD Call TI Level-NC-NC-NC Lead/Ball Finish MSL Peak Temp (3) SMJ320C15-25FJM ACTIVE JLCC FJ 44 1 TBD Call TI Level-NC-NC-NC SMJ320C15-25JDM ACTIVE CDIP SB JD 40 1 TBD Call TI Level-NC-NC-NC TMS320C10FNA OBSOLETE TBD Call TI Call TI TBD CU SNPB Level-3-220C-168HR TBD CU SNPB Level-3-220C-168HR TBD CU SNPB Level-NC-NC-NC 44 TMS320C10FNL OBSOLETE PLCC FN 44 TMS320C10FNL25 NRND PLCC FN 44 TMS320C10NA OBSOLETE PDIP N 40 26 TMS320C10NL NRND PDIP N 40 9 TBD CU SNPB Level-NC-NC-NC TMS320C10NL-25 NRND PDIP N 40 9 TBD CU SNPB Level-NC-NC-NC TMS320C10NL25 OBSOLETE 0 TBD Call TI Call TI TMS320C14FNL NRND PLCC FN 68 TBD Call TI Call TI TMS320C15FNA OBSOLETE PLCC FN 44 TBD Call TI Call TI TMS320C15FNL OBSOLETE PLCC FN 44 TBD Call TI Call TI TMS320C15FNL25 OBSOLETE PLCC FN 44 TBD Call TI Call TI TMS320C15NA OBSOLETE PDIP N 40 TBD Call TI Call TI TMS320C15NL OBSOLETE PDIP N 40 TBD Call TI Call TI TMS320C15NL-25 OBSOLETE PDIP N 40 TBD Call TI Call TI TMS320C15NL25 OBSOLETE PLCC NL 40 TBD Call TI Call TI TMS320C15PEL OBSOLETE QFP PE 44 TBD Call TI Call TI TMS320C16PGL OBSOLETE QFP PG 64 TBD Call TI Call TI TMS320C17FNL OBSOLETE PLCC FN 44 TBD Call TI Call TI TMS320C17NL OBSOLETE PDIP N 40 TBD Call TI Call TI TMS320LC15FNL OBSOLETE PLCC FN 44 TBD Call TI Call TI TMS320LC15NL OBSOLETE PDIP N 40 TBD Call TI Call TI TMS320P14FNL OBSOLETE PLCC FN 68 TBD CU SNPB TMS320P15FNL OBSOLETE PLCC FN 44 TBD Call TI Call TI TMS320P15FNL25 OBSOLETE PLCC FN 44 TBD Call TI Call TI TMS320P15NA OBSOLETE PDIP N 40 TBD Call TI Call TI TMS320P15NL OBSOLETE PDIP N 40 TBD Call TI Call TI TMS320P15NL25 OBSOLETE PDIP N 40 TBD Call TI Call TI TMS320P17FNA OBSOLETE PLCC FN 44 TBD Call TI Call TI TMS320P17FNL OBSOLETE PLCC FN 44 TBD Call TI Call TI TMS320P17FNLR OBSOLETE PLCC FN 44 TBD Call TI Call TI TMS320P17NL OBSOLETE PDIP N 40 TBD Call TI Call TI TMS320SS16NL OBSOLETE PDIP N 40 TBD Call TI Call TI (1) Level-3-220C-168HR The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 5-Dec-2005 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MCDI005 – JANUARY 1998 JD (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE 24 PINS SHOWN A 24 13 0.590 (15,00) TYP 1 12 0.065 (1,65) 0.045 (1,14) 0.620 (15,75) 0.590 (14,99) 0.175 (4,45) 0.140 (3,56) 0.075 (1,91) MAX (4 Places) Seating Plane 0.020 (0,51) MIN 0.021 (0,53) 0.015 (0,38) 0.100 (2,54) PINS ** DIM A MAX 0°– 15° 0.125 (3,18) MIN 0.012 (0,30) 0.008 (0,20) 24 28 40 48 52 1.250 (31,75) 1.450 (36,83) 2.050 (52,07) 2.435 (61,85) 2.650 (67,31) 4040087/B 04/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package is hermetically sealed with a metal lid. The terminals are gold-plated. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDI008 – OCTOBER 1994 N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 24 PIN SHOWN A 24 13 0.560 (14,22) 0.520 (13,21) 1 12 0.060 (1,52) TYP 0.200 (5,08) MAX 0.610 (15,49) 0.590 (14,99) 0.020 (0,51) MIN Seating Plane 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.125 (3,18) MIN 0.010 (0,25) M PINS ** 0°– 15° 0.010 (0,25) NOM 24 28 32 40 48 52 A MAX 1.270 (32,26) 1.450 (36,83) 1.650 (41,91) 2.090 (53,09) 2.450 (62,23) 2.650 (67,31) A MIN 1.230 (31,24) 1.410 (35,81) 1.610 (40,89) 2.040 (51,82) 2.390 (60,71) 2.590 (65,79) DIM 4040053 / B 04/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Falls within JEDEC MS-011 Falls within JEDEC MS-015 (32 pin only) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MQFP008 – JULY 1998 PG (R-PQFP-G64) PLASTIC QUAD FLATPACK 0,45 0,25 1,00 51 0,20 M 33 52 32 12,00 TYP 64 14,20 13,80 18,00 17,20 20 1 19 0,15 NOM 18,00 TYP 20,20 19,80 24,00 23,20 Gage Plane 0,25 0,10 MIN 2,70 TYP 0°– 10° 1,10 0,70 Seating Plane 3,10 MAX 0,10 4040101 / B 03/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Contact field sales office to determine if a tighter coplanarity requirement is available for this package. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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