ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE D Imaging D Communications D Baseband Digitization FEATURES D ADS5102 (65 MSPS) ADS5103 (40 MSPS) D Differential Input D 1.8 V Analog/Digital Supply D Digital Outputs Compatible With 1.8 V or 3.3 V D D D D DESCRIPTION The ADS5102/3 are low-power CMOS, 10-bit, analogto-digital converters (ADC) that operate from a single 1.8-V supply. The internal reference can be bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the application. A 10-bit parallel output data bus is provided with 3-state outputs. For power sensitive systems, a standby mode is provided which reduces power consumption to 336 µW. Also, if using external voltage reference, then the internal VREF circuit can be powered down. The analog input is differential, which provides excellent common-mode noise rejection as well as superior performance from the ADS5102/3. Logic Signal-to-Noise: 58 dB at 20 MHz (ADS5103) Spurious Free Dynamic Range: 71 dB at 20 MHz (ADS5102) 105-mW Power Dissipation (ADS5103) 336 µW Power-Down Mode APPLICATIONS D Ultrasound D Digital Cameras FUNCTIONAL BLOCK DIAGRAM AVDD STBY DRVDD DVDD Timing Circuitry CLK AIN+ Sample and Hold AIN– 3-State Output Buffers 10 Bit ADC D[0–9] OE CM NC Internal Reference Circuit RBIAS NC AGND BG PDREF REFT REFB CML DRGND DGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com 1 ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 D4 D5 D6 D7 D8 D9 NC NC D0 D1 D2 D3 PFB PACKAGE (TOP VIEW) 36 35 34 33 32 31 30 29 28 27 26 25 DRGND NC DVDD DGND AVDD AGND AIN– AIN+ AGND AVDD NC NC 37 24 38 23 39 22 40 21 41 20 42 19 43 18 44 17 45 16 46 15 47 14 48 13 2 3 4 5 6 7 8 9 10 11 12 NC AVDD AGND REFT REFB CML BG NC AGND NC NC NC 1 DRVDD NC DVDD DGND CLK STBY OE PDREF NC NC RBIAS NC NC – No internal connection ORDERING INFORMATION TA 48-TQFP (PFB) Tape and Reel 40 MSPS 2 48-TQFP (PFB) Tray 40 MSPS 48-TQFP (PFB) Tape and Reel 65 MSPS 48-TQFP (PFB) Tray 65 MSPS 0°C to 70°C ADS5103CPFBR ADS5103CPFB ADS5102CPFBR ADS5102CPFB –40°C to 85°C ADS5103IPFBR ADS5103IPFB ADS5102IPFBR ADS5102IPFB Evaluation module ADS5103EVM ADS5103EVM ADS5102EVM ADS5102EVM www.ti.com ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AVDD AGND 2, 41, 46 I Analog supply, 1.8V ±5% 3, 9, 42, 45 I Analog ground REFT 4 I/O Reference top REFB 5 I/O Reference bottom CML 6 O Common mode level output—nominally 1.0 V BG 7 O Band-gap decoupling—decouple with 1 µF to GND and 100 kΩ to AVDD (refer to Figure 30) PDREF 17 I Powerdown reference when using external voltage reference 0 = internal VREF, 1 = external VREF. In external VREF mode, connect pins BG and REFT together. RBIAS 14 O Connect a resistor between this pin and AGND. This resistor value is determined by speed grade selected and is used to set amplifier internal bias currents. (see Table 2) OE 18 I 1 = 3-state the data outputs , 0 = data bus enable STBY 19 I 0 = power down mode, 1 = normal operation mode CLK 20 I Clock Input DGND 21, 40 I Digital ground DVDD 22, 39 I Digital supply—1.8 V nominally DRVDD D9 24 I Driver digital supply—1.8 V or 3.3 V nominally 25 O Digital Bit 9 (MSB) D8 26 O Digital Bit 8 D7 27 O Digital Bit 7 D6 28 O Digital Bit 6 D5 29 O Digital Bit 5 D4 30 O Digital Bit 4 D3 31 O Digital Bit 3 D2 32 O Digital Bit 2 D1 33 O Digital Bit 1 D0 34 O Digital Bit 0 (LSB) DRGND 37 I Driver digital ground AIN+ 44 I Positive analog input AIN– 43 I Negative analog input 1,8,10,11,12, 13,15,16,23,35, 36, 38,47,48 NA NC No internal connection on this pin www.ti.com 3 ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage: VDD to AGND, DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.2 V DRVDD to DRGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 0.3 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2.2 V to 2.2 V Reference voltage input range REFT, REFB, to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V CML, analog input voltage range AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V Clock input CLK to DRGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DRVDD + 0.3 V Digital inputs to DRGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DRVDD + 0.3 V Digital outputs to DRGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DRVDD + 0.3 V Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN TYP MAX UNIT Analog Inputs Analog input voltage (AIN+, AIN–) REFB Input voltage, differential full scale Input common-mode voltage, (REFT+REFB)/2 0.8 Input capacitance (Ci), measured to ground Overvoltage recovery time, 1.8-V input voltage Analog input bandwidth Input impedance (switch capacitor) REFT 1 1.1 V Vpp V 5 pF 10 ns 950 MHz ADS5102 38.5 ADS5103 62.5 kΩ Supplies and References 85 °C 1.80 2.00 V 1.80 2.00 V 1.80 3.6 V 1.34 1.39 V 0.78 0.81 0.84 V Common-mode voltage, VCML 0.85 1.05 1.15 V Bandgap voltage, VBG 1.22 1.27 1.32 V Operating free-air temperature, TA –40 Analog supply voltage, AVDD 1.65 Digital supply voltage, DVDD 1.65 Digital driver supply voltage, DRVDD 1.65 Reference top voltage, VREFT 1.30 Reference bottom voltage, VREFB Clock Inputs CLK Sampling rate 4 ADS5102 1 65 ADS5103 1 40 www.ti.com MSPS ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 electrical characteristics over recommended operating conditions, AVDD = DVDD = 1.8 V, DRVDD = 3.3 V, Fs = 40, 65 MSPS (as appropriate)/50% duty cycle, –1 dBFS input span, CL = 10 pF at D0–D9, internal reference, T(min) to T(max), typical data at 25°C (unless otherwise noted) internal reference voltages MIN TYP MAX UNIT VREFT Reference top voltage PARAMETER 1.30 1.34 1.39 V VREFB Reference bottom voltage 0.78 0.81 0.84 V VCML Common-mode voltage 0.85 1.05 1.15 V VBG Bandgap voltage 1.22 1.27 1.32 V external reference voltages MIN TYP MAX UNIT REFT Reference input voltage (top) PARAMETER 1.15 1.25 1.35 V REFB Reference input voltage (bottom) 0.70 0.75 0.85 V REFT–REFB Differential input 0.45 0.50 0.55 Input resistance V Ω 200 digital outputs PARAMETER TEST CONDITIONS MIN VOH High level output voltage High-level IOH = 50 µA A DRVDD = 1.8 V DRVDD = 3.3 V VOL Low level output voltage Low-level IOL = 50 µA A DRVDD = 1.8 V DRVDD = 3.3 V CL External load capacitance TYP MAX DRVDD – 0.1 DRVDD – 0.2 UNIT V 0.1 0.2 15 V pF digital inputs PARAMETER TEST CONDITIONS VIH High level input voltage High-level DRVDD = 1.8 V DRVDD = 3.3 V VIL Low level input voltage Low-level DRVDD = 1.8 V DRVDD = 3.3 V IIH IIL High-level input current Low-level input current MIN TYP MAX 0.8 × DRVDD UNIT V 0.8 × DRVDD 0.2 × DRVDD 0.2 × DRVDD V ±5 µA ±5 µA VIH = DRVDD VIL = 0 V dc accuracy PARAMETER (INL) (DNL) Integral nonlinearity Differential nonlinearity TEST CONDITIONS MIN TYP MAX UNIT ADS5102 ±1 ±2.5 LSB ADS5103 ±0.5 ±1.5 LSB ADS5102 ±0.5 ±1 LSB ±0.4 ±0.8 LSB ADS5103 Missing code No missing code assured Offset error REFT = 1.25 V, REFB = 0.75 V ±0.4 ±1.5 %FSR Gain error REFT = 1.25 V, REFB = 0.75 V ±1.4 ±2 %FSR www.ti.com 5 ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 electrical characteristics over recommended operating conditions, AVDD = DVDD = 1.8 V, DRVDD = 3.3 V, Fs = 40, 65 MSPS (as appropriate)/50% duty cycle, –1 dBFS input span, CL = 10 pF at D0–D9, internal reference, T(min) to T(max), typical data at 25°C (unless otherwise noted) (continued) dynamic performance PARAMETER TEST CONDITIONS f = 3.5 MHz ADS5102 ENOB Effective number of bits SFDR Spurious free dynamic range ADS5102 THD Total harmonic distortion ADS5103 SNR Signal to noise ratio Signal-to-noise SINAD Signal to noise and distortion Signal-to-noise dBc 71 64 69 –71 f = 20 MHz –71 f = 3.5 MHz –65 f = 20 MHz –68 56 f = 20 MHz dBc –55 dBc –62 dBc 58 dBc 57 57 f = 20 MHz 59 dBc 58 54 f = 20 MHz f = 3.5 MHz ADS5103 Bits 73 f = 3.5 MHz f = 3.5 MHz ADS5102 Bits 9.2 58 58 dBc 57 56 f = 20 MHz UNIT 9.3 66 f = 3.5 MHz ADS5103 9.0 f = 20 MHz f = 3.5 MHz ADS5102 MAX 9 f = 20 MHz f = 3.5 MHz ADS5103 9.2 f = 20 MHz f = 3.5 MHz ADS5102 TYP 8.7 f = 20 MHz f = 3.5 MHz ADS5103 MIN 58 dBc 57 power supply† PARAMETER Operating O erating voltage I(AVDD) Analog supply current I(DVDD) Digital supply current I(DRVDD) Output driver supply current I(TOTAL) Total current consumption PD Power dissipation MIN TYP MAX AVDD DVDD TEST CONDITIONS 1.65 1.8 2 1.65 1.8 2 DRVDD ADS5102 1.65 1.8 3.6 70 80 45 53 8 9 5 7 ADS5103 ADS5102 ADS5103 ADS5102 ADS5103 ADS5102 ADS5103 ADS5102 ADS5103 Standby power AVDD = DVDD = 1.8 1 8 V, V DRVDD = 3 3.3 3V 1 8 V, V AVDD = DVDD= 1.8 DRVDD = 3.3 33V AVDD = DVDD = 1.8 1 8 V, V DRVDD = 3 3.3 3V 1 8 V, V AVDD = DVDD = 1.8 DRVDD = 3 3V 3.3 AVDD = DVDD = 1.8 1 8 V, V DRVDD = 3 3.3 3V CLK running Power supply rejection † Sinewave input, fi = 3.5 MHz, –1 dBFS input span 6 6.5 8 4.8 5.5 84 97 54 66 160 188 105 126 336 390 0.25 www.ti.com UNIT V mA mA mA mA mW µW %FS ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 electrical characteristics over recommended operating conditions, AVDD = DVDD = 1.8 V, DRVDD = 3.3 V, Fs = 40, 65 MSPS (as appropriate)/50% duty cycle, –1 dBFS input span, CL = 10 pF at D0–D9, internal reference, T(min) to T(max), typical data at 25°C (unless otherwise noted) (continued) timing characteristics PARAMETER TEST CONDITIONS MIN TYP MAX 50 ±10 Clock duty cycle UNIT % td(o) t(en) Output propagation delay 9 OE ↓ to outputs enabled time 6 12 ns ns tdis td(latency) OE ↑ rising to outputs 3-state disable time 10 ns Pipeline latency 5.5 cyc td(ap) Aperture delay 1 ns Aperture uncertainty 2 ps rms timing diagram S1 S2 S3 1 2 3 Analog 4 5 6 7 8 10 9 CLK td(latency) OE t(en) td(o) D[0–9] S1 www.ti.com tdis S2 S3 7 ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 TYPICAL CHARACTERISTICS ADS5102 ADS5103 ANALOG SUPPLY CURRENT vs TEMPERATURE ANALOG SUPPLY CURRENT vs TEMPERATURE 50.0 78 49.5 Analog Supply Current – mA Analog Supply Current – mA 77 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 65 MHz fi = 32.49 MHz at –1 dBFS 76 75 74 73 49.0 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 40 MHz fi = 19.99 MHz at –1 dBFS 48.5 48.0 47.5 47.0 46.5 46.0 72 45.5 45.0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 71 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 T – Temperature – °C T – Temperature – °C Figure 1 Figure 2 ADS5102 ADS5103 DIGITAL SUPPLY CURRENT vs TEMPERATURE DIGITAL SUPPLY CURRENT vs TEMPERATURE 20.0 Digital Supply Current – mA 19.0 14 13 Digital Supply Current – mA 19.5 15 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 65 MHz fi = 32.49 MHz at –1 dBFS 18.5 18.0 17.5 17.0 16.5 16.0 12 11 10 9 8 7 15.5 6 15.0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 5 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 T – Temperature – °C T – Temperature – °C Figure 3 8 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 40 MHz fi = 19.99 MHz at –1 dBFS Figure 4 www.ti.com ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 TYPICAL CHARACTERISTICS ADS5102 ADS5103 INTEGRAL NONLINEARITY vs TEMPERATURE INTEGRAL NONLINEARITY vs TEMPERATURE 2.05 INL – Integral Nonlinearity – LSB 1.85 1.65 1.45 1.25 1.05 0.85 0.65 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 40 MHz 1.65 1.45 1.25 1.05 0.85 0.65 0.45 0.45 0.25 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 0.25 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 T – Temperature – °C T – Temperature – °C Figure 5 Figure 6 ADS5102 DNL – Differential Nonlinearity – LSB INL – Integral Nonlinearity – LSB 1.85 2.05 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 65 MHz DIFFERENTIAL NONLINEARITY 0.4 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 65 MHz 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 Code Figure 7 www.ti.com 9 ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 TYPICAL CHARACTERISTICS DNL – Differential Nonlinearity – LSB ADS5103 DIFFERENTIAL NONLINEARITY 0.3 0.2 0.1 0 –0.1 –0.2 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 40 MHz –0.3 –0.4 –0.5 0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 Code Figure 8 ADS5102 INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY 0.8 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 65 MHz 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 1024 Code Figure 9 ADS5103 INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY 0.8 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 40 MHz 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0 64 128 192 256 320 384 448 512 Code Figure 10 10 www.ti.com 576 640 704 768 832 896 960 1024 ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 TYPICAL CHARACTERISTICS ADS5102 ADS5102 INTERNAL VREF VALUES vs ANALOG SUPPLY VOLTAGE INTERNAL VREF VALUES vs TEMPERATURE 2.00 2.00 1.75 1.50 Internal Vref Values – V Internal Vref Values – V 1.75 DVDD = 1.8 V DRVDD = 3.3 V Fclk = 65 MHz fi = 32.49 MHz at –1 dBFS REFT 1.25 1.00 REFB 0.75 1.50 REFT 1.25 1.00 REFB 0.75 REFT-REFB REFT-REFB 0.50 0.50 0.25 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 0.25 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 T – Temperature – °C Analog Supply Voltage – V Figure 11 Figure 12 ADS5102 ADS5103 SPURIOUS FREE DYNAMIC RANGE vs ANALOG INPUT LEVEL SPURIOUS FREE DYNAMIC RANGE vs ANALOG INPUT LEVEL 80 75 SFDR – Spurious Free Dynamic Range – dBc 80 SFDR – Spurious Free Dynamic Range – dBc AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 65 MHz fi = 32.49 MHz at –1 dBFS AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 65 MHz fi = 32.49 MHz 70 65 60 55 50 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 75 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 40 MHz fi = 19.99 MHz 70 65 60 55 50 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 Analog Input Level – dB Analog Input Level – dB Figure 13 Figure 14 www.ti.com 11 ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 TYPICAL CHARACTERISTICS ADS5102 ADS5103 TOTAL HARMONIC DISTORTION vs ANALOG INPUT FREQUENCY TOTAL HARMONIC DISTORTION vs ANALOG INPUT FREQUENCY –60 THD – Total Harmonic Distortion – dBc THD – Total Harmonic Distortion – dBc –66 –68 –70 –72 –74 –76 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 65 MHz fi = 1–32 MHz at –1 dBFS –78 –80 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 40 MHz fi = 1–19.99 MHz at –1 dBFS –62 –64 –66 –68 –70 0 4 8 12 16 20 24 28 32 0 2 Analog Input Frequency – MHz 4 6 Figure 15 12 14 16 ADS5102 ADS5103 SIGNAL-TO-NOISE RATIO vs ANALOG INPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs ANALOG INPUT FREQUENCY 18 20 18 20 61 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 65 MHz fi = 1–32 MHz at –1 dBFS 60 SNR – Signal-to-Noise Ratio – dBc SNR – Signal-to-Noise Ratio – dBc 10 Figure 16 61 59 58 57 56 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 40 MHz fi = 1–19.99 MHz at –1 dBFS 60 59 58 57 56 0 4 8 12 16 20 24 28 32 Analog Input Frequency – MHz 0 2 4 6 8 10 12 14 16 Analog Input Frequency – MHz Figure 17 12 8 Analog Input Frequency – MHz Figure 18 www.ti.com ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 ADS5102 ADS5103 SIGNAL-TO-NOISE RATIO and DISTORTION vs ANALOG INPUT FREQUENCY SIGNAL-TO-NOISE RATIO and DISTORTION vs ANALOG INPUT FREQUENCY 61 SINAD – Signal-to-Noise Ratio and Distortion – dBc SINAD – Signal-to-Noise Ratio and Distortion – dBc TYPICAL CHARACTERISTICS AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 65 MHz fi = 1–32 MHz at –1 dBFS 60 59 58 57 56 0 4 8 12 16 20 24 28 61 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 40 MHz fi = 1–19.99 MHz at –1 dBFS 60 59 58 57 56 32 0 2 Analog Input Frequency – MHz 4 6 Figure 19 10 12 14 16 18 20 18 20 Figure 20 ADS5102 ADS5103 EFFECTIVE NUMBER OF BITS vs ANALOG INPUT FREQUENCY EFFECTIVE NUMBER OF BITS vs ANALOG INPUT FREQUENCY 11.0 11.0 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 65 MHz fi = 1–32 MHz at –1 dBFS 10.5 ENOB – Effective Number of Bits – Bits ENOB – Effective Number of Bits – Bits 8 Analog Input Frequency – MHz 10.0 9.5 9.0 8.5 8.0 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 40 MHz fi = 1–19.99 MHz at –1 dBFS 10.5 10.0 9.5 9.0 8.5 8.0 0 4 8 12 16 20 24 28 32 0 2 4 6 8 10 12 14 16 Analog Input Frequency – MHz Analog Input Frequency – MHz Figure 21 Figure 22 www.ti.com 13 ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 TYPICAL CHARACTERISTICS ADS5102 ADS5103 SPURIOUS FREE DYNAMIC RANGE vs ANALOG INPUT FREQUENCY SPURIOUS FREE DYNAMIC RANGE vs ANALOG INPUT FREQUENCY 70 SFDR – Spurious Free Dynamic Range – dBc SFDR – Spurious Free Dynamic Range – dBc 80 78 76 74 72 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 65 MHz fi = 1–32 MHz at –1 dBFS 70 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 40 MHz fi = 1–19.99 MHz at –1 dBFS 69 68 67 66 65 64 63 62 61 60 68 0 4 8 12 16 20 24 28 0 32 2 4 6 8 10 12 14 16 18 20 Analog Input Frequency – MHz Analog Input Frequency – MHz Figure 23 Figure 24 ADS5102 ADS5103 SFDR, SINAD vs CLOCK DUTY CYCLE SFDR, SINAD vs CLOCK DUTY CYCLE 75 80 75 70 SFDR SFDR SFDR, SINAD – dBc SFDR, SINAD – dBc 70 65 SINAD 60 55 50 45 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 65 MHz fi = 3.58 MHz at –1 dBFS 40 60 SINAD 55 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 40 MHz fi = 3.58 MHz at –1 dBFS 50 45 35 30 35 40 45 50 55 60 65 70 30 35 40 45 50 55 Clock Duty Cycle – % Clock Duty Cycle – % Figure 25 14 65 Figure 26 www.ti.com 60 65 70 ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 TYPICAL CHARACTERISTICS ADS5102 ADS5103 SFDR, SINAD vs CLOCK DUTY CYCLE SFDR, SINAD vs CLOCK DUTY CYCLE 80 75 75 SFDR SFDR 70 SFDR, SINAD – dBc SFDR, SINAD – dBc 70 65 SINAD 60 55 50 45 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 65 MHz fi = 32.49 MHz at –1 dBFS 40 65 60 SINAD 55 AVDD = DVDD = 1.8 V DRVDD = 3.3 V Fclk = 40 MHz fi = 19.99 MHz at –1 dBFS 50 35 45 30 35 40 45 50 55 60 65 70 30 35 Clock Duty Cycle – % 40 45 50 55 60 65 70 Clock Duty Cycle – % Figure 27 Figure 28 PRINCIPLES OF OPERATION analog-to-digital converter The ADS5102/3 is designed using a switched capacitor pipeline architecture fabricated in CMOS process. The pipeline architecture is implemented with 10 stages, thus allowing for high conversion speed and exceptionally low power. Each of these 10 stages produces one digital bit per stage. Both rising and falling edges of the clock are used so the signal propagates thru the pipeline every half clock or five total clocks. Digital error correction uses another 1/2 clock cycle at the end; thus the total pipeline latency is 5.5 clocks. (Refer to timing diagram on page 7) 10-stage operation The signal is sampled by the SHA. The first stage is digitized by 1.5 bits and sent to the digital error correction block. This digitized value is then applied to a DAC, which recreates the analog value that has been digitized. This value is then fed into a summing junction with the original input signal. The summing junction subtracts the converted value from the original signal. This is known as the residue voltage. This residue voltage is then amplified by a factor of 2x and transferred to the next stage. This is repeated for each of the 10 stages. Each of the 10 pipeline stages, as well as the sample and hold amplifier, is differential in nature. This allows rejection of any common mode signal. Thus a signal seen on Ain+ and Ain– is differentially seen as 0 V on the output. This fully differential architecture allows higher ac performance of the ADC by reducing noise susceptibility. www.ti.com 15 ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 PRINCIPLES OF OPERATION analog input sample and hold amplifier circuit The sample and hold amplifier is implemented using switch capacitor techniques. A simplified functional block diagram is shown in Figure 29. The SHA is in sample mode when CLK is high and in hold mode when CLK is low. In sample mode, the input switches, P1, are closed and the differential input signal is sampled onto caps Cs. An internal common-mode voltage is applied to the sampling caps (Cs) when the two P1P switches are closed. As the CLK falling edge occurs, the SHA is now placed into hold or amplification mode. In this mode, P1 switches are now opened and switches P2 are closed. This is the amplification state and the signal is transferred to the output of the amplifier with a nominal gain of 1. CL of Figure 29 represents the load capacitance of the following stage. R-C values of the input determine the analog input bandwidth of the SHA (and therefore the whole ADC) which is 950 MHz for the ADS5102/3. This wide bandwidth assures no distortion to the Nyquist frequency of 32.5 MHz. In under sampling applications, it is common to require the analog input bandwidth to be 5 times greater than the IF Nyquist frequency. As such, the ADS5102/3 supports IF frequencies approaching 200 MHz in under sampling applications. P2 P1 VINP CS + _ P1P VC P1 CL _ + CS CI VIN CL P1 P2 Figure 29. Simplified Functional Block Diagram Because the input to the sample and hold amplifier is a switched capacitor circuit, the input resistance is dynamic and based on the sampling rate of the converter. The impedance of each input is defined by the equation: 1 Z + I F Cs Where: Cs = Sampling capacitor = 0.4 pF typical F = CLK frequency in Hz The key for selecting an amplifier to correctly drive the ADS5102/3 is to ensure that the output frequency of the amplifier is much lower than the input impedance of the ADS5102/3, which at 65 MSPS is 38.46 kΩ . For system accuracy comparable to 1 LSB, this means selecting an amplifier with output impedance of ~ 31 Ω for sampling rates of 65 MSPS. reference configurations The ADS5102/3 provides an internal voltage reference which should be suitable for most 10 bit systems. The typical full scale voltage for the device is determined by VFS = VREFT – VREFB. Since the input is fully differential, the full scale input is twice the single ended value or 1 V differential. It is recommended to externally de-couple both VREFT and VREFB with a 0.1 µF capacitor to bypass all high frequency noise to ground. It is necessary to connect BG and AVDD with a 100 kΩ resistor and decouple with a 1 µF capacitor to AGND (refer to Figure 30 for correct configuration). 16 www.ti.com ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 PRINCIPLES OF OPERATION AVDD 100 kΩ BG 1 µF Figure 30. BG Reference Configuration For systems that require more absolute accuracy or lower temperature coefficient drift than provided by the internal VREF, an external voltage reference can be applied to the VREFB and VREFT inputs. To use external reference, connect the PDREF pin to a logic high and this internally disconnects the VREF from the ADC. In this mode it is also necessary to connect the BG and REFT pins together on the PWB. It is recommended to use the input levels of VREFB = 0.75 V and VREFB = 1.25 V to achieve optimum ADC performance. It is also recommended to apply a common-mode voltage to the input of 1 V. clock input The clock input is designed for 1.8 V or 3.3 V CMOS logic levels (depends on DRVDD) and it is recommended to use standard CMOS logic levels as inputs. The logic threshold internally is set to DRVDD/2 or nominally 1.65 V. Since both edges of the clock are used in the switch capacitor architecture, it is important to provide a clock with (ideally) a 50% duty cycle. The performance variation with clock duty cycle can be examined from Figures 25, 26, 27 and 28. Clock jitter is also important for performance of the ADC to be maintained. Any clock jitter appears as noise when sampling input frequencies. Clock Jitter reduces the signal to noise ratio (SNR) and is more severe as the input frequency increases. The theoretical SNR limits based on clock jitter can be calculated as follows: Theoretical SNR (clock jitter) (dB) + 20 log ǒ 2 p 1 F I CLK (jitter) Ǔ Where: FI = Highest input frequency to the ADC in Hz CLK(jitter) = the amount of jitter on the clock in sec Therefore for a Nyquist frequency input of 32.5 MHz and a design trying to achieve the most available performance from the ADS5102/3, the clock jitter must be less than 3.98 ps rms. In under sampling applications, the same equations apply and clock jitter becomes more critical and may be the limiting factor in system performance. The aperture jitter of the SHA also contributes to overall jitter. For worst case designs, the jitter of clock and aperture can be considered to add in quadrature, i.e. Total Jitter = Square root of ( CLKjitter2 + Aperturejitter 2) The aperture jitter of the ADS5103 is 2 ps rms and at frequencies approaching Nyquist, the total jitter should be accounted for. www.ti.com 17 ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 PRINCIPLES OF OPERATION digital outputs The outputs of the ADS5102/3 are also CMOS and are programmable for either 3.3 V or 1.8 V CMOS logic levels. This is controlled by the DRVDD supply. Either 3.3 V or 1.8 V can be applied to DRVDD with excellent results. The output format is offset binary with D0 (LSB) and D9 (MSB). See Table 1 for output coding with a differential input signal applied. There is a 5.5 clock latency from the sampling to valid data output on D0–D9. The outputs can be placed into active mode by taking OE low or 3-state by taking OE high. The timing relations between OE and output bus enable/disable times are shown in the timing diagram (refer to page 7). The capacitive loading on the digital outputs is very important to achieve best performance. The total load capacitance is typically made up of two sources, next stage input capacitance and PWB etch run capacitance. The total capacitance of these two loads should be held to less than 15 pF. If for some reason, this cannot be met, it is recommended to use logic buffers such as ‘244 placed physically very close to the ADC output. This isolates the ADC output from the load capacitance and performance specs are achieved. Another technique is to place a small resistor in series with the outputs. This resistance dampens the current spikes into the capacitive loads and thus improve ADC performance. The value of this resistor varies with sampling rate but generally 22 Ω is a good value. Again this depends on the load capacitance. The digital output of these devices is offset binary and follows the following format. Table 1. Output Coding DIGITAL OUTPUT CODE ANALOG INPUT IN + SIGNAL VOLTAGE IN – STEP REFT† REFB† 1023 1 1 1 1 1 1 1 1 1 1 • • • • • • • • • • • • • (REFT – REFB) / 2 (REFT – REFB) / 2 512 1 0 0 0 0 0 0 0 0 0 • • 511 0 1 1 1 1 1 1 1 1 1 • • • • • • • • • • • • • REFB REFT 0 0 0 0 0 0 0 0 0 0 † Where there is either an internal voltage reference or an external voltage reference applied to the REFT and REFB pins. 0 MSB LSB driving the analog input Since many real world signals are single ended and most modern high speed ADC’s employ differential inputs, it is necessary in many cases to perform single ended to differential conversion prior to the ADC. Also, the ADC performs optimally if a differential signal is applied to the inputs. In some cases, signal conditioning is required in the form of the amplification or filtering. The two preferred techniques for driving the ADC input are: 1) With an active amplifier specifically designed to drive ADC’s; 2) With an RF transformer. driving the analog input with a differential amplifier Texas Instruments has developed a family of high quality operational amplifiers that have been designed specifically for driving the input stage of modern ADC’s. These devices allow for amplification and filtering prior to the ADC. This stage can be used to set the maximum signal voltage to match the full scale input of the ADC. The best solution for driving the ADS5102/3 ADC’s is the THS4501 amplifier. Figure 31 shows how to use this device with a gain of 2. The ADC common mode output voltage can be directly connected to the op amp to provide the proper levels. The THS4501 provides optimum matching of op amp output to the input of the ADS5102/3. This configuration provides signal amplification, filtering, and single-ended to differential conversion. It is recommended to provide de-coupling capacitors of 0.1 µF and 0.001 µF on the CML output. This filters out any high frequency noise prior the ADC input. 18 www.ti.com ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 PRINCIPLES OF OPERATION 750 Ω 49.9 Ω THS4501 V(source) 374 Ω + 374 Ω AIN– 68 pF VO– VO+ _ VOCM ADS5102, ADS5103 49.9 Ω AIN+ Digital Outputs CML 750 Ω 68 pF 0.1 µF 0.001 µF Figure 31. Driving the ADS5102/3 With Differential Amp (Gain = 2) driving the analog input with a transformer When little or no signal conditioning is required, a simple transformer is an excellent way to drive the input of the ADS5102/3 family. The transformer provides single-ended to differential conversion and at frequencies under 200 MHz produces very little distortion of the incoming signal. Figure 32 shows the preferred circuit diagram for implementing a transformer-coupled input. The signal source is ac-coupled and fed to the primary side of the RF transformer. Since the ADC input must be biased to the correct common mode voltage, the CML output of the ADC is connected to the secondary center tap. It is recommended to provide decoupling capacitors of 0.1 µF and 0.001 µF on the CML output. This filters out any high frequency noise prior the ADC input. 0.1 µF V(source) AIN– ADS5102, ADS5103 49.9 Ω AIN+ Digital Outputs CML T1 – 1T-KK81 Mini-Circuits 0.001 µF 0.1 µF Figure 32. Driving the ADS5102/3 With a Transformer www.ti.com 19 ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 PRINCIPLES OF OPERATION REFT 3 kΩ 3 kΩ AIN+ AIN+ ADS5102 ADS5103 AIN– AIN– 3 kΩ 3 kΩ REFB Figure 33. Driving the Analog Inputs setting the bias resistor—RBIAS Each device in this family requires an external resistor be connected from pin 14 to ground. The value of this resistor is determined by which device is being used. Refer to Table 2 for the correct resistor value. This resistor only dissipates less than 1 mW of power. The resistor accuracy of 1% is adequate. Table 2. Resistor Value 20 DEVICE RBIAS VALUE ADS5103 8.25 kΩ ADS5102 4.42 kΩ www.ti.com CONNECT FROM Pin 14 to AGND ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 DEFINITION OF SPECIFICATIONS Analog Input Bandwidth—The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay—The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Uncertainity (Jitter)—The sample-to-sample variation in aperture delay. Differential Nonlinearity (DNL)—The maximum deviation of any single LSB transition at the digital output from an ideal 1 LSB step at the analog input. Ideally, each transition step is 1 LSB wide. DNL is the measured error from theoretical in step size. A DNL of less than –1 LSB implies no missing codes. Integral Nonlinearity (INL)—is the summation of the differential nonlinearity errors and indicates the worst case deviation from an best fit straight line that is drawn from 1/2 LSB of the first transition to 1/2 LSB above the last transition. The best fit is determined using the least squares curve fitting method. Duty Cycle—is the ratio of the clock time high over the full clock period (time high plus time low) and then also the time low over the total clock period. At a given clock rate, these specs define the acceptable duty cycle allowed on the clock. Sampling Rate (Fs)—The rate at which the converter tested to ensure conversion of analog signals to digital. The maximum rate specified is the rate and which the device is production tested to ensure performance specs are met. Expressed in mega samples per second (MSPS). Output Propagation Delay—The delay between the 50% point of the falling edge of clock signal and the time when all output data bits are within valid logic levels. Offset Error—In an ideal ADC the first transition from 0000000000 should occur at 1/2 LSB above REFB. Offset Error is defined as the difference between this ideal first transition and the voltage level where the first transition actually occurs. Expressed in % full scale range (%FSR) but may also be expressed in volts. This can be thought of as shifting the transfer function either left or right along the X-axis. Overvoltage Recovery Time—The amount of time required for the converter to recover to 0.2% accuracy after an analog input signal 150% of full scale is reduced to midscale. Power Supply Rejection Ratio—The ratio of a change in input offset voltage to a change in power supply voltage. Total Harmonic Distortion (THD)—The ratio of the peak signal amplitude to the summation of the harmonic components. This is expressed in – dB. THD = 20 Log [input amplitude/(summation of harmonic bins)]. For calculation purposes, the first 7 harmonics are included in the calculations. Signal To Noise Distortion (SINAD)—The ratio of the rms signal amplitude (set 1 dB below full scale) to rms value of the sum of all other spectral noise and harmonic components, but excluding dc. Signal to Noise Ratio (SNR)—The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the the sum of all other spectral components, excluding the first five harmonics and dc. Reported in dB. Spurious Free Dynamic Range (SFDR)—The difference between the peak amplitude of a fundamental input sine wave and the largest peak spurious component that appears, excluding dc and the input. The peak spurious component may or may not be a harmonic frequency. May be reported in dBc (i.e., degrades as signal levels is lowered), or in dBFS (always related back to converter full scale). www.ti.com 21 ADS5102 ADS5103 SLAS351B – OCTOBER 2001 – REVISED DECEMBER 2001 MECHANICAL DATA PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°–ā7° 1,05 0,95 Seating Plane 1,20 MAX 0,75 0,45 0,08 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 22 www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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