STM6510 Dual push-button Smart ResetTM with capacitor-adjustable delays Features ■ Dual Smart Reset™ push-button inputs with capacitor-adjustable extended reset setup delay (tSRC) ■ Capacitor-adjustable reset pulse duration (tREC) ■ Power-on reset – RST active-low, open-drain ■ Factory-programmable thresholds to monitor VCC in the range of 1.575 to 4.625 V typ. ■ Operating voltage 1.0 V (active-low output valid) to 5.5 V ■ Low supply current (1.4 µA) ■ Operating temperature: industrial grade –40 °C to +85 °C ■ Mobile phones, smartphones ■ TDFN8 package: 2 mm x 2 mm x 0.75 mm ■ e-books ■ RoHS compliant ■ MP3 players ■ Games ■ Portable navigation devices ■ Any application that requires delayed reset push-button(s) response for improved system stability February 2010 TDFN8 (DG) 2 mm x 2 mm Applications Doc ID 16788 Rev 2 1/26 www.st.com 1 Contents STM6510 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Smart Reset™ devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 STM6510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.1 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.2 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.3 Smart Reset™ push-button inputs (SR0, SR1) . . . . . . . . . . . . . . . . . . . . 9 1.3.4 Adjustable delay of Smart Reset™ input (SRC pin) . . . . . . . . . . . . . . . . 9 1.3.5 Reset output (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3.6 Adjustable reset timeout (TRECADJ pin) . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2/26 Doc ID 16788 Rev 2 STM6510 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 tSRC programmed by an ideal external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 tREC programmed by an ideal external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Possible VCC voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . 18 Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 19 Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Doc ID 16788 Rev 2 3/26 List of figures STM6510 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. 4/26 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Single-button Smart Reset™ typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Dual-button Smart Reset™ typical hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply current (ICC) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Smart Reset™ delay (tSRC) vs. temperature, CSRC = 0.56 µF . . . . . . . . . . . . . . . . . . . . . . 11 Reset timeout period (tREC) vs. temperature, CtREC = 0.01 µF . . . . . . . . . . . . . . . . . . . . . 12 Reset threshold (VRST) vs. temperature, “S” threshold option, VCC falling. . . . . . . . . . . . . 12 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline . . . . . . . . . . . . . . . . . . . . . 18 Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 19 Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package marking, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Doc ID 16788 Rev 2 STM6510 Description 1 Description 1.1 Smart Reset™ devices The Smart Reset™ device family STM65xx provides a useful feature that ensures inadvertent short reset push-button closures do not cause system resets. This is done by implementing an extended Smart Reset™ input delay (tSRC). Once the valid Smart Reset™ input levels and setup delay are met, the device generates an output reset pulse with userprogrammable timeout period (tREC). The typical application hookup shows that the dual Smart Reset™ inputs can be also connected to the applications interrupt to allow the control of both the interrupt pin and the hard reset functions. If the push-buttons are closed for a short time, the processor is only interrupted. If the system still does not respond properly, holding the push-buttons for the extended setup time (tSRC) causes a hard reset of the processor through the reset output. The Smart Reset™ feature helps significantly increase system stability. The STM65xx family of Smart Reset™ devices consists of low-current microprocessor reset circuits targeted at applications such as MP3 players, portable navigation devices or mobile phones, generally any application that requires delayed reset push-button(s) response for improved system stability. The STM65xx devices feature single or dual Smart Reset™ inputs (SRx). The delayed Smart Reset™ setup time (tSRC) options are adjustable by adding an external capacitor on the SRC pin or selectable by three-state logic. The delayed setup period ignores switch closures shorter than tSRC, thus preventing undesired resets. The STM65xx devices have active-low (optionally active-high) open-drain reset (RST) output(s) with or without an internal pull-up resistor or push-pull as output options, with or without the power-on reset function. Some devices also have an undervoltage monitoring feature: the reset output is also asserted when the monitored supply voltage VCC drops below the specified threshold. The reset output remains asserted for the reset timeout period (tREC) after the monitored supply voltage goes above the specified threshold. 1.2 STM6510 The STM6510 has two combined Smart Reset™ inputs (SR0 and SR1) with Smart Reset™ setup delay (tSRC) programmed by an external capacitor on the SRC pin. An additional STM6510 feature is adjustable output reset pulse time tREC by adding an external capacitor (CtREC). Additionally, the VCC is monitored and if it drops below the selected VRST threshold, the reset output goes active and remains active while VCC is below the VRST threshold, plus the defined duration of the reset pulse tREC. Doc ID 16788 Rev 2 5/26 Description STM6510 Figure 1. Logic diagram VCC SR0 RST STM6510 SR1 TRECADJ SRC VSS Figure 2. AM00389a Pin connections RST 1 8 VCC VSS 2 7 SR0 SR1 3 6 TRECADJ NC 4 5 SRC STM 6510 AM00390 Table 1. Symbol Input/output RST Output SR0 Input Primary push-button Smart Reset™ input. Active-low, internal 65 kΩ pull-up resistor to VCC. SR1 Input Secondary push-button Smart Reset™ input. Active-low, internal 65 kΩ pull-up resistor to VCC. SRC Input Smart Reset™ input delay setup control. Connect an external capacitor to this pin to adjust the delay setup time (tSRC). TRECADJ Input Input pin for tREC reset pulse duration adjustment. Connect an external capacitor (CtREC) to this pin to determine tREC. VCC Supply Supply voltage input. Power supply for the device and an input for the monitored supply voltage. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between VCC and VSS pins. VSS Supply Ground NC 6/26 Signal names Description Reset output, active-low (open-drain). No connect (not bonded); should be connected to VSS. Doc ID 16788 Rev 2 STM6510 Description Figure 3. Block diagram VCC 65 kΩ VRST COMPARE 65 kΩ tREC generator SR0 SR1 Logic RST TRECADJ CtREC SRC AM00391a Doc ID 16788 Rev 2 7/26 Description STM6510 Figure 4. Single-button Smart Reset™ typical hookup VCC 100 kΩ VCC TRECADJ CtREC RESET RST VCC SRC CSRC STM6510 MCU SR1 INT/ NMI SR0 VSS VSS PUSH-BUTTON SWITCH AM04870v1 Note: When only one Smart Reset™ input push-button is used, tie both the SR inputs together. Figure 5. Dual-button Smart Reset™ typical hookup VCC VCC TRECADJ CtREC 100 kΩ RST RESET VCC SRC CSRC STM6510 MCU SR1 INT/ NMI SR0 VSS PUSH-BUTTON SWITCH VSS PUSH-BUTTON SWITCH AM004871v1 8/26 Doc ID 16788 Rev 2 STM6510 Description 1.3 Pin descriptions 1.3.1 Power supply (VCC) This pin is used to provide the power to the Smart Reset™ device and to monitor the power supply. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between the VCC and VSS pins. 1.3.2 Ground (VSS) This is the supply ground for the device. 1.3.3 Smart Reset™ push-button inputs (SR0, SR1) Both SR0 and SR1 need to be held active at the same time for at least tSRC to activate the reset output pulse. Include an internal 65 kΩ pull-up resistor to VCC for each input. Figure 6. Timing waveforms tSRC tREC SR0 SR1 RST AM00393 1.3.4 Adjustable delay of Smart Reset™ input (SRC pin) This pin controls the setup time before the push-button action is validated by the reset output. It is connected to an external capacitor (CSRC), which is tied to ground to provide the desired value of setup time (tSRC). Calculated tSRC and CSRC examples are given in Table 2. Refer also to Table 6. Table 2. tSRC programmed by an ideal external capacitor Calculated CSRC value [µF] Setup delay tSRC [s](1)(2) Min. Typ. Max. Closest common CSRC value [µF] 0.2 2 3 4 0.22 0.3 3 4.5 6 0.33 0.6 6 9 12 0.56 1 10 15 20 1 1. Example calculations based on an ideal capacitor. During application design and component selection it should be considered that the current flowing into the external tSRC programming capacitor (CSRC) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) and an adequate PCB environment should be used to prevent tSRC accuracy from being affected. A recommended minimum value of CSRC is 0.01 µF. 2. In case of repeated activations of the tSRC counter, an interval of 10 ms min. is needed between the activations to fully discharge CSRC, so that the next tSRC is as specified. Doc ID 16788 Rev 2 9/26 Description 1.3.5 STM6510 Reset output (RST) RST is active-low, open-drain. 1.3.6 Adjustable reset timeout (TRECADJ pin) The reset timeout (tREC) is adjustable by connecting an external capacitor CtREC to this pin. Calculated tREC and CtREC examples are given in Table 3. Refer also to Table 6. Table 3. tREC programmed by an ideal external capacitor Calculated CtREC value [µF] tREC [ms](1)(2) Min. Typ. Max. Closest common CtREC value [µF] 0.001 10 15 20 0.001 0.002 20 30 40 0.0022 0.01 100 150 200 0.01 0.014 140 210 280 0.015 0.028 280 420 560 0.027 0.056 560 840 1120 0.056 0.112 1120 1680 2240 0.1 1. Example calculations based on an ideal capacitor. During application design and component selection it should be considered that the current flowing into the external tREC programming capacitor (CtREC) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) and an adequate PCB environment should be used to prevent tREC accuracy from being affected. A recommended minimum value of CtREC is 0.001 µF. 2. In case of repeated activations of the tREC counter, an interval of 10 ms min. is needed between tREC intervals to fully discharge CtREC, so that the next tREC is as specified. 10/26 Doc ID 16788 Rev 2 STM6510 Typical operating characteristics 2 Typical operating characteristics Figure 7. Supply current (ICC) vs. temperature 2.4 2.2 2 1.8 1.6 ICC [μA] 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature [°C] 5.5 V Figure 8. 3.3 V 5V 3V AM04876v1 Smart Reset™ delay (tSRC) vs. temperature, CSRC = 0.56 µF 12 11 tSRC [s] 10 9 8 7 6 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature [°C] 5.75 V 5.5 V 3.3 V Doc ID 16788 Rev 2 AM04877v1 11/26 Typical operating characteristics Figure 9. STM6510 Reset timeout period (tREC) vs. temperature, CtREC = 0.01 µF 200 190 180 170 tREC [ms] 160 150 140 130 120 110 100 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature [°C] 5.75 V 5.5 V 3.3 V AM04878v1 Figure 10. Reset threshold (VRST) vs. temperature, “S” threshold option, VCC falling 2.99 2.97 VRST [V] 2.95 2.93 2.91 2.89 2.87 2.85 -60 -40 -20 0 20 40 60 Temperature [°C] 12/26 Doc ID 16788 Rev 2 80 100 120 140 AM04879v1 STM6510 3 Maximum ratings Maximum ratings Stressing the device above the rating listed in the Table 4: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics™ SURE Program and other relevant quality documents. Table 4. Absolute maximum ratings Symbol TSTG Parameter Storage temperature (VCC off) TSLD(1) Lead solder temperature for 10 seconds θJA Thermal resistance (junction to ambient) VIO Input or output voltage VCC Supply voltage TDFN8 Value Unit –55 to +150 °C 260 °C 149.0 °C/W –0.3 to VCC +0.3 V –0.3 to 7 V 1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds. Doc ID 16788 Rev 2 13/26 DC and AC parameters 4 STM6510 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the Table 6: DC and AC characteristics that follow, are derived from tests performed under the Measurement Conditions summarized in Table 5: Operating and measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 5. Operating and measurement conditions Parameter Value Unit VCC supply voltage 1.0 to 5.5 V Ambient operating temperature (TA) –40 to +85 °C ≤ 5 ns Input pulse voltages 0.2 to 0.8 VCC V Input and output timing ref. voltages 0.3 to 0.7 VCC V Input rise and fall times Figure 11. AC testing input/output waveforms 0.8 VCC 0.2 VCC 14/26 Doc ID 16788 Rev 2 0.7 VCC 0.3 VCC AM00478 STM6510 Table 6. Symbol DC and AC parameters DC and AC characteristics VCC Supply voltage range ICC Supply current (VCC) VOL VRST Test conditions(1) Parameter Reset output voltage low Min. Reset output valid - active-low 1.0 VCC = 5.0 V VCC = 3.0 V 1.5 (3) VCC to reset delay(4) tREC(4) Units 5.5 V 2.4 µA µA VCC ≥ 4.5 V, sinking 3.2 mA 0.3 V VCC ≥ 3.3 V, sinking 2.5 mA 0.3 V VCC ≥ 1.0 V, sinking 0.1 mA 0.3 V –40 to +85 °C VRST –2.5% VRST VRST +2.5% V 25 °C VRST –2.0% VRST VRST +2.0% V VCC undervoltage reset threshold (refer to Table 7) Hysteresis of VRST Max. 1.4 L, M VHYST Typ.(2) 0.5% T, S, R, Z, Y, W, V 1% VCC falling from (VRST + 100 mV) to (VRST - 100 mV) at 10 mV/µs 20 µs 10 000 x 15 000 x 20 000 x CtREC CtREC CtREC (µF) (µF) (µF) ms 15 x CSRC (µF) 20 x CSRC (µF) s 0.3 VCC V User-adjustable reset timeout period on RST. Refer to Table 3. Smart Reset™ inputs tSRC(5) User-adjustable delayed Smart Reset™ setup time. Refer to Table 2. VIL SR0, SR1 input voltage low VIH SR0, SR1 input voltage high RPUI Internal pull-up resistor, SR0, SR1 inputs 10 x CSRC (µF) 0.7 VCC V 65 kΩ 1. Valid for ambient operating temperature: TA = –40 to +85 °C; VCC = 1.0 to 5.5 V (except where noted). 2. Typical value is at 25 °C and VCC = 3.3 V unless otherwise noted. 3. For devices with VRST < 3.0 V. 4. Guaranteed by design. 5. Input glitch immunity is equal to tSRC (when both SR inputs are low, otherwise infinite). Doc ID 16788 Rev 2 15/26 DC and AC parameters Table 7. STM6510 Possible VCC voltage thresholds VCC voltage threshold VRST 16/26 ±2.5% (–40 °C to +85 °C) ±2.0% (25 °C) Typ. Unit Min. Max. Min. Max. L (falling) 4.625 4.509 4.741 4.533 4.718 V M (falling) 4.375 4.266 4.484 4.288 4.463 V T (falling) 3.075 2.998 3.152 3.014 3.137 V S (falling) 2.925 2.852 2.998 2.867 2.984 V R (falling) 2.625 2.559 2.691 2.573 2.678 V Z (falling) 2.313 2.255 2.371 2.267 2.359 V Y (falling) 2.188 2.133 2.243 2.144 2.232 V W (falling) 1.665 1.623 1.707 1.632 1.698 V V (falling) 1.575 1.536 1.614 1.544 1.607 V Doc ID 16788 Rev 2 STM6510 5 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Doc ID 16788 Rev 2 17/26 Package mechanical data STM6510 Figure 12. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline D A B PIN 1 INDEX AREA E 0.10 C 2x 0.10 C 2x TOP VIEW 0.10 C C A1 A SEAT ING PLANE SIDE VIEW 0.08 C e b PIN 1 INDEX AREA 1 4 0.10 C A B Pin#1 ID L 5 8 BOTTOM VIEW 8070540_A Table 8. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data Dimension (mm) Dimension (inches) Symbol Min. Nom. Max. Min. Nom. Max. A 0.70 0.75 0.80 0.028 0.030 0.031 A1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 D BSC 2.00 0.079 E BSC 2.00 0.079 e 0.50 0.020 L 18/26 0.45 0.55 0.65 Doc ID 16788 Rev 2 0.018 0.022 0.026 STM6510 Package mechanical data Figure 13. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad D P E E1 L b Table 9. AM00441 Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package Dimension (mm) Parameter Description Min. Nom. Max. L Contact length 1.05 — 1.15 b Contact width 0.25 — 0.30 E Max. land pattern Y-direction — 2.75 — E1 Contact gap spacing — 0.65 — D Max. land pattern X-direction — 1.75 — P Contact pitch — 0.5 — Doc ID 16788 Rev 2 19/26 Package mechanical data STM6510 Figure 14. Carrier tape P0 D P2 T E A0 F Top cover tape W B0 Center lines of cavity K0 P1 User direction of feed AM03073v2 Table 10. Carrier tape dimensions Package W D TDFN8 8.00 +0.30 –0.10 1.50 +0.10/ –0.00 20/26 E P0 P2 F 1.75 4.00 2.00 3.50 ±0.10 ±0.10 ±0.10 ±0.05 A0 B0 K0 P1 T 2.30 ±0.05 2.30 ±0.05 1.00 ±0.05 4.00 ±0.10 0.250 ±0.05 Doc ID 16788 Rev 2 Unit Bulk qty. mm 3000 STM6510 Package mechanical data Figure 15. Reel dimensions T 40 mm min. acces hole at slot location B D C N A Full radius Tape slot in core for tape start 25 mm min width G measured at hub AM00443 Table 11. Reel dimensions Tape sizes A max. B min. C D min. N min. G T max. 8 mm 180 (7 inches) 1.50 13.0 +/– 0.20 20.20 60 8.4 +2/–0 14.40 Doc ID 16788 Rev 2 21/26 Package mechanical data STM6510 Figure 16. Tape trailer/leader End Top cover tape Start No components Components 100 mm min. T RA IL ER No components L EA D ER 160 mm min. 400 mm min. Sealed with cover tape User direction of feed AM00444 Figure 17. Pin 1 orientation User direction of feed Note: 22/26 1 Drawings are not to scale. 2 All dimensions are in mm, unless otherwise noted. Doc ID 16788 Rev 2 AM00442 STM6510 Part numbering 6 Part numbering Table 12. Ordering information scheme Example: STM6510 W C A C DG 6 F Device type STM6510 Reset (VCC monitoring threshold) voltage VRST L = 4.625 V (typ., falling) M = 4.375 V T = 3.075 V S = 2.925 V R = 2.625 V Z = 2.313 V Y = 2.188 V W = 1.665 V V = 1.575 V Smart Reset™ setup delay control (tSRC); presence of internal input pull-up on all Smart Reset™ inputs (SR0, SR1) C = 1 to 15 s, user-programmable (external capacitor); 65 kΩ input pull-up Output type A = open-drain, active-low Reset timeout period (tREC) C = user-programmable (external capacitor) Package DG = TDFN8 - 2 x 2 x 0.75 mm, 0.5 mm pitch Temperature range 6 = –40 °C to +85 °C Shipping method F = ECOPACK® package, tape and reel For device options currently available refer to Table 13. For other options, voltage threshold values etc. or for more information on any aspect of this device, please contact the ST sales office nearest you. Doc ID 16788 Rev 2 23/26 Package marking 7 Package marking Table 13. Note: STM6510 Package marking Part name tSRC delay control Smart Reset™ inputs type VRST STM6510WCACDG6F CSRC AL, PU W AL, OD CtREC 8WK STM6510SCACDG6F CSRC AL, PU S AL, OD CtREC 8SK STM6510RCACDG6F CSRC AL, PU R AL, OD CtREC 8RK Reset tREC Topmark output type programming AL = Active-Low, AH = Active-High; PU = with internal pull-up resistor, OD = Open-Drain. Figure 18. Package marking, top view A B C D E Topmark A = dot (pin 1 reference) B = assembly plant (P) C = assembly year (Y, 0-9): 9 = 2009 etc. D = assembly work week (WW, 01 to 52): 20 = WW20 etc. E = marking area (topmark) AM00479 24/26 Doc ID 16788 Rev 2 STM6510 8 Revision history Revision history Table 14. Document revision history Date Revision Changes 12-Feb-2010 1 Initial release. 26-Feb-2010 2 Updated title of datasheet, Features, Applications; updated footnote 1 of Table 2; updated Table 6, 12, 13; Figure 3; Section 1.3.3; minor textual and formatting changes. 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