STM6600 STM6601 Smart push-button on/off controller with Smart ResetTM and power-on lockout Features ■ Operating voltage 1.6 V to 5.5 V ■ Low standby current of 1 µA ■ Adjustable Smart Reset™ assertion delay time driven by external CSRD ■ Power-up duration determined primarily by push-button press (STM6600) or by fixed time period, tON_BLANK (STM6601) ■ Debounced PB and SR inputs ■ PB and SR ESD inputs withstand voltage up to ±15 kV (air discharge) ±8 kV (contact discharge) ■ Active high or active low enable output option (EN or EN) provides control of MOSFET, DC-DC converter, regulator, etc. ■ Secure startup, interrupt, Smart Reset™ or power down driven by push-button ■ Precise 1.5 V voltage reference with 1% accuracy ■ Industrial operating temperature –40 to +85 °C ■ Available in TDFN12 2 x 3 mm package Table 1. TDFN12 Applications ■ Portable devices ■ Terminals ■ Audio and video players ■ Cell phones and smart phones ■ PDAs, palmtops, organizers Device summary Device RST CSRD PB / SR EN or EN INT Startup process STM6600 open drain(1) ✓ ✓ push-pull open drain(1) PB must be held low until the PSHOLD(2) confirmation STM6601 open drain(1) ✓ ✓ push-pull open drain(1) PB can be released before the PSHOLD(2) confirmation 1. External pull-up resistor needs to be connected to open drain outputs. 2. For a successful startup, the PSHOLD (Power Supply Hold) needs to be pulled high within specific time, tON_BLANK. June 2010 Doc ID 15453 Rev 7 1/51 www.st.com 1 Contents STM6600 - STM6601 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10 Product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2/51 Doc ID 15453 Rev 7 STM6600 - STM6601 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 TDFN12 (2 x 3 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Carrier tape dimensions for TDFN12 (2 mm x 3 mm) package . . . . . . . . . . . . . . . . . . . . . 45 STM6600 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 STM6601 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 STM6600 product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 STM6601 product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Doc ID 15453 Rev 7 3/51 List of figures STM6600 - STM6601 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. 4/51 Application hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Basic functionality (option with enable deassertion after long push) . . . . . . . . . . . . . . . . . . 6 Basic functionality (option with RST assertion after long push) . . . . . . . . . . . . . . . . . . . . . . 6 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TDFN12 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Successful power-up on STM6600 (PB released prior to tON_BLANK expiration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Successful power-up on STM6600 (tON_BLANK expires prior to PB release) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Unsuccessful power-up on STM6600 (PB released prior to tON_BLANK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Unsuccessful power-up on STM6600 (tON_BLANK expires prior to PB release) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Successful power-up on STM6601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Unsuccessful power-up on STM6601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power-up on STM660x with voltage dropout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PB interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Long push, PB pressed first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Long push, SR pressed first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Invalid long push . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Long push (option with RST assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Long push (option with enable deassertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Undervoltage detected for <tSRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Undervoltage detected for >tSRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PBOUT output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Supply current vs. temperature, normal state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Supply current vs. temperature, standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Supply current vs. supply voltage, normal state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Supply current vs. supply voltage, standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Threshold vs. temperature, VTH+ = 3.4 V (typ.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Threshold hysteresis vs. temperature, VHYST = 200 mV (typ.) . . . . . . . . . . . . . . . . . . . . . . 30 Debounce period vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CSRD charging current vs. temperature, VCC = 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Output low voltage vs. output low current, TA = 25°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Output high voltage vs. output high current, TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Output voltage vs. supply voltage, IOUT = 1 mA, TA = 25 °C . . . . . . . . . . . . . . . . . . . . . . . 33 Input voltage vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reference output voltage vs. temperature, VCC = 2.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reference output voltage vs. load current, VCC = 2.0 V, TA = 25 °C . . . . . . . . . . . . . . . . . 34 Reference output voltage vs. supply voltage, TA = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Reference startup, IREF = 15 µF, TA = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Reference response to steps on supply voltage, IREF = 15 µA, TA = 25 °C . . . . . . . . . . . . 36 Reference response to steps in load current, VCC = 3.6 V, TA = 25 °C . . . . . . . . . . . . . . . 37 TDFN12 (2 x 3 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 TDFN12 (2 x 3 mm) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Carrier tape for TDFN12 (2 mm x 3 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Doc ID 15453 Rev 7 STM6600 - STM6601 1 Description Description The STM6600-01 devices monitor the state of connected push-button(s) as well as sufficient supply voltage. An enable output controls power for the application through the MOSFET transistor, DC-DC converter, regulator, etc. If the supply voltage is above a precise voltage threshold, the enable output can be asserted by a simple press of the button. Factoryselectable supply voltage thresholds are determined by highly accurate and temperaturecompensated references. An interrupt is asserted by pressing the push-button during normal operation and can be used to request a system power-down. The interrupt is also asserted if undervoltage is detected. By a long push of one button (PB) or two buttons (PB and SR) either a reset is asserted or power for the application is disabled depending on the option used. The device also offers additional features such as precise 1.5 V voltage reference with very tight accuracy of 1%, separate output indicating undervoltage detection and separate output for distinguishing between interrupt by push-button or undervoltage. The device consumes very low current of 6 µA during normal operation and only 1 µA current during standby. The STM6600-01 is available in the TDFN12 package and is offered in several options among features such as selectable threshold, hysteresis, timeouts, output types, etc. (see Table 8 and Table 9 for more information). Figure 1. Application hookup $#$#CONVERTER POWER-/3&%4 REGULATORETC 2 ,%$ 6## %.%. 234 6## ,/ 2 2 34- 34- 0" /54 )/ 6 2%& #32$ 6$$ .-)OR).4 ).4 32 234 )/ 03 (/,$ 0" '.$ 2 #2%& -#5 #05 "!3%"!.$ #32$ !-V !-V 1. A resistor is required for open drain output type only. A 10 kΩ pull-up is sufficient in most applications. 2. Capacitor CREF is mandatory on VREF output (even if VREF is not used). Capacitor value of 1 µF is recommended. 3. For the STM6601 the processor has to confirm the proper power-on during the fixed time period, tON_BLANK. This failsafe feature prevents the user from turning on the system when there is a faulty power switch or an unresponsive microprocessor. Doc ID 15453 Rev 7 5/51 Description STM6600 - STM6601 Figure 2. Basic functionality (option with enable deassertion after long push) INTERRUPT (short push) POWER-UP(1) POWER DOWN (long push) PB SR EN INT interrupt interrupt AM00243v1 1. For power-up the battery voltage has to be above VTH+ threshold. Figure 3. Basic functionality (option with RST assertion after long push) INTERRUPT (short push) POWER-UP(1) POWER DOWN (long push) PB SR RST INT interrupt interrupt AM00243bv1 1. For power-up the battery voltage has to be above VTH+ threshold. Figure 4. Logic diagram VCC EN (EN) RST PB SR PSHOLD STM6600 STM6601 INT PBOUT VCC LO CSRD VREF GND 6/51 Doc ID 15453 Rev 7 AM00236v1 STM6600 - STM6601 Table 2. Description Pin descriptions Pin number Symbol 1 VCC Power supply input 2 SR Smart Reset™ button input 3 VREF 4 PSHOLD 5 CSRD 6 PB 7 VCCLO Output for high threshold comparator output (VTH+) 8 PBOUT Status of PB push-button input 9 EN or EN Enable output 10 RST Reset output 11 INT Interrupt output 12 GND Ground Figure 5. Function Precise 1.5 V voltage reference PSHOLD input Adjustable Smart Reset™ delay time input Push-button input TDFN12 pin connections VCC 1 12 GND SR 2 11 INT VREF 3 10 RST PSHOLD 4 9 EN (EN) CSRD 5 8 PBOUT 7 VCC LO PB 6 AM00245v1 Doc ID 15453 Rev 7 7/51 Description Figure 6. STM6600 - STM6601 Block diagram VCC LO VCC VCC (1) RPB PB (2) RSR EN (EN) VCC + + – – VTH+ RST tREC generator PSHOLD VTH– Smart logic Glitch immunity Edge detector debounce (3) RPSHOLD INT SR Glitch immunity Edge detector debounce VREF GND SRD logic PBOUT 1.5 V CSRD AM00237v3 1. Internal pull-up resistor connected to PB input (see Table 5 for precise specifications). 2. Optional internal pull-up resistor connected to SR input (see Table 5 for precise specifications and Table 10 for detailed device options). 3. Internal pull-down resistor is connected to PSHOLD input only during startup (see Figure 7, 8, 9, 10, 11, 12, 13, and 18). 8/51 Doc ID 15453 Rev 7 STM6600 - STM6601 2 Pin descriptions Pin descriptions VCC - power supply input VCC is monitored during startup and normal operation for sufficient voltage level. Decouple the VCC pin from ground by placing a 0.1 µF capacitor as close to the device as possible. SR - Smart Reset™ button input This input is equipped with voltage detector with a factory-trimmed threshold and has ±8 kV HBM ESD protection. Both PB and SR buttons have to be pressed and held for tSRD period so the long push is recognized and the reset is asserted (or the enable output is deasserted depending on the option) - see Figure 15, 16, and 17. Active low SR input is usually connected to GND through the momentary push-button (see Figure 1) and it has an optional 100 kΩ pull-up resistor. It is also possible to drive this input using an external device with either open drain (recommended) or push-pull output. Open drain output can be connected in parallel with push-button or other open drain outputs, which is not possible with push-pull output. VREF - external precise 1.5 V voltage reference This 1.5 V voltage reference is specified with very tight accuracy of 1% (see Table 5). It has proper output voltage as soon as the reset output is deasserted (i.e. after tREC expires) and it is disabled when the device enters standby mode. A mandatory capacitor needs to be connected to VREF output (even if VREF is not used). Capacitor value of 1 µF is recommended. PSHOLD input This input is equipped with a voltage detector with a factory-trimmed threshold. It is used to confirm correct power-up of the device (if EN or EN is not asserted) or to initiate a shutdown (if EN or EN is asserted). Forcing PSHOLD high during power-up confirms the proper start of the application and keeps enable output asserted. Because most processors have outputs in high-Z state before initialization, an internal pull-down resistor is connected to PSHOLD input during startup (see Figure 7, 8, 9, 10, 11, 12, 13, and 18). Forcing the PSHOLD signal low during normal operation deasserts the enable output (see Figure 14). Input voltage on this pin is compared to an accurate voltage reference. CSRD - Smart Reset™delay time input A capacitor to ground determines the additional time (tSRD) that PB with SR must be pressed and held before a long push is recognized. The connected CSRD capacitor is charged with ISRD current. Additional Smart Reset™ delay time tSRD ends when voltage on the CSRD capacitor reaches the VSRD voltage threshold. It is recommended to use a low ESR capacitor (e.g. ceramic). If the capacitor is not used, leave the CSRD pin open. If no capacitor is connected, there is no tSRD and a long push is recognized right after tINT_Min expires (see Figure 18 and 19). Doc ID 15453 Rev 7 9/51 Pin descriptions STM6600 - STM6601 PB - power ON switch This input is equipped with a voltage detector with a factory-trimmed threshold and has ± 8 kV HBM ESD protection. When the PB button is pressed and held, the battery voltage is detected and EN (or EN) is asserted if the battery voltage is above the threshold VTH+ during the whole tDEBOUNCE period (see Figure 13). A short push of the push-button during normal operation can initiate an interrupt through debounced INT output (see Figure 14) and a long push of PB and SR simultaneously can either assert reset output RST (see Figure 18) or deassert the EN or EN output (see Figure 19) based on the option used. Note: A switch to GND must be connected to this input (e.g. mechanical push-button, open drain output of external circuitry, etc.), see Figure 1. This ensures a proper startup signal on PB (i.e. a transition from full VCC below specified VIL). PB input has an internal 100 kΩ pull-up resistor connected. VCCLO - high threshold detection output During power-up, VCCLO is low when VCC supply voltage is below the VTH+ threshold. After successful power-up (i.e. during normal operation) VCCLO is low anytime undervoltage is detected (see Figure 13). Output type is active low and open drain by default. Open drain output type requires a pullup resistor. A 10 kΩ is sufficient in most applications. VCCLO is floating when STM660x is in standby mode. PBOUT - PB input state If the push-button PB is pressed, the pin stays low during the tDEBOUNCE time period. If PB is asserted for the entire tDEBOUNCE period, PBOUT will then stay low for at least tINT_Min. If PB is asserted after tINT_Min expires, PBOUT will return high as soon as PB is deasserted (see Figure 22). PBOUT ignores PB assertion during an undervoltage condition. At startup on the STM6601 PBOUT will respond only to the first PB assertion and any other assertion will be ignored until tON_BLANK expires. This output is active low and open drain by default. Open drain output type requires a pull-up resistor. A 10 kΩ is sufficient in most applications. 10/51 Doc ID 15453 Rev 7 STM6600 - STM6601 Pin descriptions EN or EN - enable output This output is intended to enable system power (see Figure 1). EN is asserted high after a valid turn-on event has been detected and confirmed (i.e. push-button has been pressed and held for tDEBOUNCE or more and VCC > VTH+ voltage level has been detected - see Figure 13). EN is released low if any of the conditions below occur: a) the push-button is released before PSHOLD is driven high (valid for STM6600, see Figure 9) or tON_BLANK expires before PSHOLD is driven high during startup (valid for both STM6600 and STM6601, see Figure 10 and 12). b) PSHOLD is driven low during normal operation (see Figure 14). c) an undervoltage condition is detected for more than tSRD + tINT_Min + tDEBOUNCE (see Figure 21). d) a long push of the buttons is detected (only for the device with option “EN deasserted by long push” - see Figure 19) or PSHOLD is not driven high during tON_BLANK after a long push of the buttons (only for the device with option “RST asserted by long push” - see Figure 18). Described logic levels are inverted in case of EN output. Output type is push-pull by default. RST - reset output This output pulls low for tREC: a) during startup. PB has been pressed (falling edge on the PB detected) and held for at least tDEBOUNCE and VCC > VTH+ (see Figure 7, 8, 9, 10, 11, 12 and 13 for more details). b) after long push detection (valid only for the device with option “RST asserted by long push”). PB has been pressed (falling edge on the PB detected) and held for more than tDEBOUNCE + tSRD (additional Smart Reset™ delay time can be adjusted by the external capacitor CSRD) - see Figure 18. Output type is active low and open drain by default. Open drain output type requires a pullup resistor. A 10 kΩ is sufficient in most applications. INT - interrupt output While the system is under normal operation (PSHOLD is driven high, power for application is asserted), the INT is driven low if: a) VCC falls below VTH- threshold (i.e. undervoltage is detected - see Figure 20 and 21). b) the falling edge on the PB is detected and the push-button is held for tDEBOUNCE or more. INT is driven low after tDEBOUNCE and stays low as long as PB is held. The INT signal is held high during power-up. The state of the PBOUT output can be used to determine if the interrupt was caused by either the assertion of the PB input, or was due to the detection of an undervoltage condition on VCC. INT output is asserted low for at least tINT_Min. Output type is active low and open drain by default. Open drain output type requires a pullup resistor. A 10 kΩ is sufficient in most applications. GND - ground Doc ID 15453 Rev 7 11/51 Operation 3 STM6600 - STM6601 Operation The STM6600-STM6601 simplified smart push-button on/off controller with Smart Reset™ and power-on lockout enables and disables power for the application depending on pushbutton states, signals from the processor, and battery voltage. Power-on Because most of the processors have outputs in high-Z state before initialization, an internal pull-down resistor is connected to PSHOLD input during startup (see Figure 7, 8, 9, 10, 11, 12, 13, and 18). To power up the device the push-button PB has to be pressed for at least tDEBOUNCE and VCC has to be above VTH+ for the whole tDEBOUNCE period. If the battery voltage drops below VTH+ during the tDEBOUNCE, the counter is reset and starts to count again when VCC > VTH+ (see Figure 13). After tDEBOUNCE the enable signal is asserted (EN goes high, EN goes low), reset output RST is asserted for tREC and then the startup routine is performed by the processor. During initialization, the processor sets the PSHOLD signal high. On the STM6600 the PSHOLD signal has to be set high prior to push-button release and tON_BLANK expiration, otherwise the enable signal is deasserted (EN goes low, EN goes high) - see Figure 7, 8, 9, and 10. The time up to push-button release represents the maximum time allowed for the system to power up and initialize the circuits driving the PSHOLD input. If the PSHOLD signal is low at push-button release, the enable output is deasserted immediately, thus turning off the system power. If tON_BLANK expires prior to push-button release, the PSHOLD state is checked at its expiration. This safety feature disables the power and prevents discharging the battery if the push-button is stuck or it is held for an unreasonable period of time and the application is not responding (see Figure 8 and 10). PB status, INT status and VCC undervoltage detection are not monitored until power-up is completed. On the STM6601 the PSHOLD signal has to be set high before tON_BLANK expires, otherwise the enable signal is deasserted - see Figure 11 and 12. In this case the tON_BLANK period is the maximum time allowed for the power switch and processor to perform the proper poweron. If the PSHOLD signal is low at the end of the blanking period, the enable output is released immediately, thus turning off the system power. PB status, INT status and VCC undervoltage detection are not monitored during the entire tON_BLANK period. This failsafe feature prevents the user from turning on the system when there is a faulty power switch or an unresponsive microprocessor. Push-button interrupt If the device works under normal operation (i.e. PSHOLD is high) and the push-button PB is pressed for more than tDEBOUNCE, a negative pulse with minimum tINT_Min width is generated on the INT output. By connecting INT to the processor interrupt input (INT or NMI) a safeguard routine can be performed and the power can be shut down by setting PSHOLD low - see Figure 14. Forced power-down mode The PSHOLD output can be forced low anytime during normal operation by the processor and can deassert the enable signal - see Figure 14. 12/51 Doc ID 15453 Rev 7 STM6600 - STM6601 Operation Undervoltage detection If VCC voltage drops below VTH- voltage threshold during normal operation, the INT output is driven low (see Figure 20 and Figure 21). If an undervoltage condition is detected for tDEBOUNCE + tINT_Min + tSRD, the enable output is deasserted (see Figure 21). Hardware reset or power-down while system not responding If the system is not responding and the system hangs, the PB and SR push-buttons can be pressed simultaneously longer than tDEBOUNCE + tINT_Min + tSRD, and then a) either the reset output RST is asserted for tREC and the processor is reset (valid only for the device with option “RST asserted by long push”) – see Figure 18 b) or the power is disabled by EN or EN signal (valid only for the device with option “EN deasserted by long push”) – see Figure 19 The tSRD is set by the external capacitor connected to the CSRD pin. Standby If the enable output is deasserted (i.e. EN is low or EN is high), the STM660x device enters standby mode with low current consumption (see Table 5). In standby mode PB input is only monitored for the falling edge. The external 1.5 V voltage reference is also disabled in standby mode. Doc ID 15453 Rev 7 13/51 Waveforms STM6600 - STM6601 4 Waveforms Figure 7. Successful power-up on STM6600 (PB released prior to tON_BLANK expiration) Push-button pressed and PB connected to GND processor sets PSHOLD PB released prior to t ON_BLANK expiration PSHOLD state detected as high EN remains asserted VCC undervoltage detection ignored PSHOLD ignored internal pull-down resistor connected to PSHOLD input PB(1) PSHOLD(2) EN(3) RST tDEBOUNCE tREC tON_BLANK Note: INT signal is held high during power-up (i.e. until PB release in this case). VCC is considered VCC > VTH+. AM00247v3 1. PB detection on falling and rising edges. 2. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up. 3. EN signal is high even after PB release, because processor sets PSHOLD signal high before PB is released. 14/51 Doc ID 15453 Rev 7 STM6600 - STM6601 Figure 8. Waveforms Successful power-up on STM6600 (tON_BLANK expires prior to PB release) Push-button pressed and PB connected to GND processor sets PSHOLD tON_BLANK expired prior to PB release PSHOLD state detected as high EN remains asserted PB released VCC undervoltage detection ignored PSHOLD ignored internal pull-down resistor connected to PSHOLD input PB(1) PSHOLD(2) EN(3) RST tDEBOUNCE tREC tON_BLANK Note: INT signal is held high during power-up (i.e. until tON_BLANK expires in this case). VCC is considered VCC > VTH+. AM00247bv2 1. PB detection on falling and rising edges. 2. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up. 3. tON_BLANK expires prior to PB release so PSHOLD is checked at its expiration. Doc ID 15453 Rev 7 15/51 Waveforms Figure 9. STM6600 - STM6601 Unsuccessful power-up on STM6600 (PB released prior to tON_BLANK) PB released PSHOLD state detected as low EN deasserted Push-button pressed and PB connected to GND VCC undervoltage detection ignored PSHOLD ignored internal pull-down resistor connected to PSHOLD input PB(1) PSHOLD(2) PB status ignored EN(3) RST tDEBOUNCE tEN_OFF tREC tON_BLANK Note: INT signal is held high during power-up (i.e. until PB release in this case). VCC is considered VCC > VTH+. AM00248v3 1. PB detection on falling and rising edges. 2. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up. 3. EN signal goes low with PB release, because processor did not force PSHOLD signal high. 16/51 Doc ID 15453 Rev 7 STM6600 - STM6601 Waveforms Figure 10. Unsuccessful power-up on STM6600 (tON_BLANK expires prior to PB release) tON_BLANK expired prior to PB release PSHOLD state detected as low EN is deasserted Push-button pressed and PB connected to GND PB (1) PB released VCC undervoltage detection ignored PB status ignored PSHOLD ignored internal pull-down resistor connected to PSHOLD input PSHOLD(2) EN(3) RST tDEBOUNCE tEN_OFF tREC tON_BLANK Note: INT signal is held high during power-up (i.e. until tON_BLANK expires in this case). VCC is considered VCC > VTH+. AM00248bv2 1. PB detection on falling and rising edges. 2. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up. 3. tON_BLANK expires prior to PB release so PSHOLD is checked at its expiration. Doc ID 15453 Rev 7 17/51 Waveforms STM6600 - STM6601 Figure 11. Successful power-up on STM6601 tON_BLANK expires processor PSHOLD state detected as high sets PSHOLD EN remains asserted Push-button pressed and PB connected to GND PB PB status and V CC undervoltage detection ignored (1) PSHOLD ignored (2) PSHOLD EN internal pull-down resistor connected to PSHOLD input (3) RST t DEBOUNCE t REC t ON_BLANK Note: INT signal is held high during power-up (i.e. until tON_BLANK expires in the case of the STM6601). VCC is considered VCC > VTH+. AM00250v2 1. PB detection on falling edge. 2. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up. 3. PSHOLD signal is ignored during tON_BLANK. When tON_BLANK expires, the level of the PSHOLD signal is high therefore the EN signal remains asserted. 18/51 Doc ID 15453 Rev 7 STM6600 - STM6601 Waveforms Figure 12. Unsuccessful power-up on STM6601 tON_BLANK expires PSHOLD state detected as low Push-button pressed and PB connected to GND EN deasserted Push-button pressed and PB connected to GND (1) PB PSHOLD ignored (2) PSHOLD intenal pull-down resistor connected to PSHOLD input (3) EN RST t DEBOUNCE t REC Note: INT signal is held high during power-up (i.e. until tON_BLANK expires in the case of the STM6601). VCC is considered VCC > VTH+. AM00238v2 1. PB detection on falling edge. 2. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up. 3. PSHOLD signal is ignored during tON_BLANK. When tON_BLANK expires, the level of the PSHOLD signal is not high therefore the EN signal goes low. Even releasing the PB button after the tON_BLANK will not prevent this. Doc ID 15453 Rev 7 19/51 Waveforms STM6600 - STM6601 Figure 13. Power-up on STM660x with voltage dropout Push-button pressed and PB connected to GND VCC goes above VTH+ and tDEBOUNCE is counted again VTH+ VTH– VCC VCC LO VCC–Min VCC undervoltage detected VCC drop (1) PB (2) PSHOLD INT internal pull-down resistor connected to PSHOLD input (3) INT signal is held high during power-up EN RST < t DEBOUNCE t DEBOUNCE tREC < t ON_BLANK AM00249v2 1. PB detection on falling and rising edges. 2. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during power-up. 3. INT signal is held high during power-up. 20/51 Doc ID 15453 Rev 7 STM6600 - STM6601 Waveforms Figure 14. PB interrupt processor interrupt starts power-down sequence processor sets PSHOLD low Push-button pressed and PB connected to GND PB and EN is deasserted accordingly PB status ignored (1,2) PSHOLD PB status ignored VCC undervoltage detection ignored t DEBOUNCE t INT_Min tEN_OFF Note: VCC is considered VCC > VTH+. AM00251v2 1. PB detection on falling edge. 2. PB is released within tSRD and that is why NO reset is asserted and EN is NOT deasserted immediately. Doc ID 15453 Rev 7 21/51 Waveforms STM6600 - STM6601 Figure 15. Long push, PB pressed first Push-button PB is pressed PB Push-button tSRD starts to SR is pressed be counted tSRD tDEBOUNCE set by CSRD tDEBOUNCE SR INT PB status ignored tINT_Min AM00257v1 Figure 16. Long push, SR pressed first Push-button SR is pressed PB Push-button PB is pressed tSRD starts to be counted tDEBOUNCE tSRD SR set by CSRD INT PB status ignored tINT_Min 22/51 Doc ID 15453 Rev 7 AM00258v1 STM6600 - STM6601 Waveforms Figure 17. Invalid long push Push-button PB is pressed Push-button SR is pressed PB tSRD starts to be counted Any rising edge will stop tSRD to count regardless of glitch immunity tDEBOUNCE < tSRD SR set by CSRD INT PB status ignored tINT_Min AM00259v1 Doc ID 15453 Rev 7 23/51 Waveforms STM6600 - STM6601 Figure 18. Long push (option with RST assertion) Push-button pressed and PB connected to GND tON_BLANK expires PSHOLD state detected as high therefore EN remains high Push-button held even after tSRD expires therefore RST is asserted tSRD(1) set by CSRD PB After tON_BLANK PB is monitored for falling edge tON_BLANK (valid for STM6600 and STM6601) SR PB status ignored INT (2) RST INT can go high, if PB goes high, but system freezes and processor won’t respond VCC undervoltage detection status ignored PSHOLD ignored if system freezes, processor won’t respond to any INT status change (3, 4) PSHOLD tDEBOUNCE t INT_Min internal pull-down resistor connected to PSHOLD input tREC Note: EN is high. tDEBOUNCE AM00252v2 1. tSRD period is set by external capacitor CSRD. 2. PB ignored during tINT_Min. 3. PSHOLD signal is ignored during tON_BLANK. Its level is checked after tON_BLANK expires and if it is high the EN signal remains asserted, otherwise EN goes low. 4. Internal pull-down resistor 300 kΩ is connected to PSHOLD input during startup when device is reset. 24/51 Doc ID 15453 Rev 7 STM6600 - STM6601 Waveforms Figure 19. Long push (option with enable deassertion) Push-button pressed and PB connected to GND Push-button held even after tSRD expires and EN is deasserted tSRD(1) set by CSRD PB After tEN_OFF expires PB is monitored for falling edge PB status ignored SR INT can go high, if PB goes high, PB status but system freezes and processor ignored won’t respond INT (2) EN(3) VCC undervoltage detection status ignored if system freezes, processor won’t respond to any INT status change PSHOLD tDEBOUNCE t INT_Min tEN_OFF tDEBOUNCE AM00253v2 1. tSRD period is set by external capacitor CSRD. 2. PB ignored during tINT_Min. 3. After tSRD expires EN is forced low. Doc ID 15453 Rev 7 25/51 Waveforms STM6600 - STM6601 Figure 20. Undervoltage detected for <tSRD processor interrupt starts power-down sequence VCC undervoltage detected (1) VCC processor sets PSHOLD low VTH+ tSRD set by CSRD (2) VTH– VCC-Min PB status ignored and EN is deasserted accordingly VCC LO PSHOLD V CC undervoltage detection ignored INT PB status ignored EN tINT_Min tDEBOUNCE tEN_OFF AM00254v1 1. VCC goes above VTH+ within tSRD thus power is not disabled after tSRD expires. 2. tSRD period is set by external capacitor CSRD. Figure 21. Undervoltage detected for >tSRD VCC undervoltage detected VCC is below VTH+ even after tSRD expires thus power is disabled (EN goes low) and PB is monitored for regular startup VTH+ (1) VCC tSRD(2) VTH– set by CSRD VCC-Min VCCLO PSHOLD VCC undervoltage detection ignored INT PB status ignored PB status ignored EN tDEBOUNCE tINT_Min tEN_OFF AM00255v1 1. After tSRD expires VCC is still insufficient (below VTH+) thus power is disabled (EN goes low or EN goes high). 2. tSRD period is set by external capacitor CSRD. 26/51 Doc ID 15453 Rev 7 STM6600 - STM6601 Waveforms Figure 22. PBOUT output waveform <glitch immunity (1,2,3,4) PB PBOUT tDEBOUNCE tINT_min AM00256v1 1. Pulses on PB shorter than glitch immunity are ignored. 2. Pulses on PB shorter than tDEBOUNCE are not recognized by PBOUT. 3. Minimum pulse width on PBOUT is tINT_Min. 4. If push-button is held longer than tDEBOUNCE + tINT_Min, PBOUT goes high when the push-button is released. Doc ID 15453 Rev 7 27/51 Typical operating characteristics 5 STM6600 - STM6601 Typical operating characteristics Figure 23. Supply current vs. temperature, normal state 7.0 Supply current, ICC (µA) 6.5 6.0 5.5 5.0 4.5 VCC = 5.5 V 4.0 VCC = 3.6 V VCC = 2.0 V 3.5 3.0 -40 -20 0 20 40 60 80 Temperature, TA (°C) AM04701v1 Figure 24. Supply current vs. temperature, standby state 2.0 Supply current, ICC (µA) VCC = 5.5 V VCC = 3.6 V 1.5 VCC = 2.0 V 1.0 0.5 0.0 -40 -20 0 20 40 60 80 Temperature, TA (°C) AM04702v1 28/51 Doc ID 15453 Rev 7 STM6600 - STM6601 Typical operating characteristics Figure 25. Supply current vs. supply voltage, normal state 7 Supply current, ICC (µA) 6 5 4 3 TA = 85 °C 2 TA = 25 °C TA = 0 °C 1 TA = –40 °C 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Supply voltage, VCC (V) AM04703v1 Figure 26. Supply current vs. supply voltage, standby state 1.5 Supply current, ICC (µA) TA = 85 °C TA = 25 °C TA = 0 °C 1.0 TA = –40 °C 0.5 0.0 2.0 2.5 3.0 3.5 4.0 Supply voltage, VCC (V) Doc ID 15453 Rev 7 4.5 5.0 5.5 AM04704v1 29/51 Typical operating characteristics STM6600 - STM6601 Figure 27. Threshold vs. temperature, VTH+ = 3.4 V (typ.) 3.50 Threshold, V TH+ (V) 3.45 3.40 3.35 3.30 3.25 3.20 -40 -20 0 20 40 60 80 Tem perature, T A (°C) AM04705v1 Figure 28. Threshold hysteresis vs. temperature, VHYST = 200 mV (typ.) Threshold hysteresis, VHTYST (mV) 230 220 210 200 190 180 170 -40 -20 0 20 Tem perature, TA (°C) 30/51 Doc ID 15453 Rev 7 40 60 80 AM04706v1 STM6600 - STM6601 Typical operating characteristics Figure 29. Debounce period vs. supply voltage Debounce period, tDEBOUNCE (ms) 45 40 35 30 TA = 85 °C 25 TA = 25 °C TA = 0 °C 20 TA = –40 °C 15 3.5 4 4.5 5 5.5 Supply voltage, VCC (V) AM04707v1 Figure 30. CSRD charging current vs. temperature, VCC = 3.6 V 200 CSRD charging current, ISRD (nA) 190 180 170 160 150 140 130 VCC = 5.5 V 120 VCC = 3.6 V 110 VCC = 2 V 100 -40 -20 0 20 40 Temperature, TA (°C) Doc ID 15453 Rev 7 60 80 AM04708v1 31/51 Typical operating characteristics STM6600 - STM6601 Figure 31. Output low voltage vs. output low current, TA = 25°C Output low voltage, VOL (V) 0.30 VCC =1.6V 0.25 VCC =3.6V 0.20 VCC =5.5V 0.15 0.10 0.05 0.00 0 1 2 3 4 5 Output low current, IOL (mA) Note: AM04709v1 Characteristics valid for all the outputs (EN, EN, RST, INT, PBOUT and VCCLO). Figure 32. Output high voltage vs. output high current, TA = 25°C 0.8 Output high voltage, VCC - VOH (V) VCC=1.6V VCC=3.6V 0.6 VCC=5.5V 0.4 0.2 0 0 0.5 1 Output high current, IOH (mA) Note: 32/51 Characteristics valid for EN and EN outputs. Doc ID 15453 Rev 7 1.5 2 AM04710v1 STM6600 - STM6601 Typical operating characteristics Figure 33. Output voltage vs. supply voltage, IOUT = 1 mA, TA = 25 °C 1 Output voltage, VOUT (V) 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 Supply voltage, VCC (V) Note: AM04711v1 Characteristics valid for all the outputs (EN, EN, RST, INT, PBOUT and VCCLO). Figure 34. Input voltage vs. temperature 1.05 VCC = 3.6 V 1.04 Input voltage, VIN (V) VCC = 5.5 V 1.03 1.02 1.01 1.00 0.99 -40 -20 0 20 Temperature, TA (°C) Note: 40 60 80 AM04712v1 Characteristics valid for PB, SR and PSHOLD inputs. Doc ID 15453 Rev 7 33/51 Typical operating characteristics STM6600 - STM6601 Figure 35. Reference output voltage vs. temperature, VCC = 2.0 V 1.520 Reference output voltage, VREF (V) 1.515 IREF = 0 mA 1.510 IREF = 15 µA 1.505 1.500 1.495 1.490 1.485 1.480 -40 -20 0 20 40 60 80 Temperature, TA (°C) Note: AM04713v1 1 µF capacitor is connected to the VREF pin. Figure 36. Reference output voltage vs. load current, VCC = 2.0 V, TA = 25 °C Reference output voltage, VREF (V) 1.6 1.5 1.4 1.3 1.2 1.1 1 0 50 100 150 Load current, IREF (µA) Note: 34/51 1 µF capacitor is connected to the VREF pin. Doc ID 15453 Rev 7 200 250 300 AM04714v1 STM6600 - STM6601 Typical operating characteristics Figure 37. Reference output voltage vs. supply voltage, TA = 25 °C 1.520 Reference output voltage, VREF (V) 1.515 1.510 1.505 1.500 1.495 IREF = 0 µA 1.490 IREF = 15 µA 1.485 1.480 2 2.5 3 3.5 4 Supply voltage, VCC (V) Note: 4.5 5 5.5 AM04715v1 1 µF capacitor is connected to the VREF pin. Figure 38. Reference startup, IREF = 15 µF, TA = 25 °C Note: 1 µF capacitor is connected to the VREF pin. Doc ID 15453 Rev 7 35/51 Typical operating characteristics STM6600 - STM6601 Figure 39. Reference response to steps on supply voltage, IREF = 15 µA, TA = 25 °C Note: 36/51 1 Supply voltage goes from 3.6 V to 5.5 V and back to 3.6 V, ramp 1 V / 100 ns. 2 1 µF capacitor is connected to the VREF pin. Doc ID 15453 Rev 7 STM6600 - STM6601 Typical operating characteristics Figure 40. Reference response to steps in load current, VCC = 3.6 V, TA = 25 °C Note: 1 Supply voltage goes from 0 µA to 15 µA and back to 0 µA, ramp 1 µA / 100 ns. 2 1 µF capacitor is connected to the VREF pin. Doc ID 15453 Rev 7 37/51 Maximum ratings 6 STM6600 - STM6601 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3. Symbol VCC Absolute maximum ratings Parameter Min. Max. Unit Remarks Input supply voltage –0.3 +7.0 V Input voltages on PB, SR, PSHOLD and CSRD –0.3 VCC + 0.3 V Output voltages on EN (EN), RST and INT –0.3 VCC + 0.3 V –2 +2 kV Human body model (all pins) –8 +8 kV Human body model (PB and SR) VESD Electrostatic protection VESD Electrostatic protection –1000 +1000 V Charged device model VESD Electrostatic protection –200 +200 V Machine model VESD Point discharge on PB and SR inputs –8 +8 kV IEC61000-4-2 VESD Air discharge on PB and SR inputs –15 +15 kV IEC61000-4-2 Operating ambient temperature –40 +85 °C Storage temperature –45 +150 °C Lead solder temperature for 10 seconds +260 °C Thermal resistance (junction to ambient) +132.4 °C/W TA TSTG TSLD (1) θ JA 1. Reflow at peak temperature of 260°C. The time above 255°C must not exceed 30 seconds. 38/51 Doc ID 15453 Rev 7 STM6600 - STM6601 7 DC and AC characteristics DC and AC characteristics This section summarizes the operating measurement conditions and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests performed under the measurement conditions summarized in Table 4. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4. Operating and AC measurement conditions Parameter Condition Unit VCC supply voltage 1.6 to 5.5 V Ambient operating temperature (TA) –40 to 85 °C ≤_5 ns Input rise and fall times Table 5. Symbol VCC DC and AC characteristics Parameter Test condition(1) Supply voltage Min. 1.6 VCC = 3.6 V, no load ICC VTH+ Supply current Threshold hysteresis (see Table 10 for detailed listing) VTH– Forced power-off voltage (see Table 10 for detailed listing) tTH– Undervoltage detection to INT delay Max. Unit 5.5 V 8 µA 1 µA 2.40 2.50 2.60 3.00 3.10 3.20 3.20 3.30 3.40 3.29 3.40 3.51 3.39 3.50 3.61 V 200 mV 500 VTH+ – VHYST VCC ≥ 2.0 V Blanking period (see tON_BLANK Table 10 for detailed listing)(3) RST assertion to EN (EN) assertion delay during power-up 6 Standby mode, enable deasserted, VCC = 3.6 V Power-on lockout voltage (see Table 10 for detailed listing) VHYST Typ.(2) VCC = 3.6 V Doc ID 15453 Rev 7 V 20 32 44 1.4 2.2 3.0 5.6 8.8 12.0 11.2 17.6 24.0 100 ms s ns 39/51 DC and AC characteristics Table 5. Symbol STM6600 - STM6601 DC and AC characteristics (continued) Parameter Test condition(1) Min. Typ.(2) Max. Unit 0.99 V PB VIL Input low voltage VCC ≥ 2.0 V, enable asserted VIH Input high voltage VCC ≥ 2.0 V, enable asserted tDEBOUNCE Debounce period RPB Internal pull-up resistor VIL Input low voltage VIH Input high voltage 1.05 V VCC ≥ 2.0 V 20 32 44 ms VCC = 5.5 V, input asserted 65 100 135 kΩ 0.99 V SR 1.05 tDEBOUNCE Debounce period RSR(4) Internal pull-up resistor VCC = 5.5 V, input asserted Output low voltage VCC = 2 V, ISINK = 1 mA, PBOUT asserted PBOUT leakage current VPBOUT = 3 V, PBOUT open drain Output low voltage VCC = 2 V, ISINK = 1 mA, VCCLO asserted VCC LO leakage current VVCCLO = 3 V, VCCLO open drain VIL Input low voltage VCC ≥ 2.0 V VIH Input high voltage VCC ≥ 2.0 V V 20 32 44 ms 65 100 135 kΩ 0.3 V +0.1 µA 0.3 V +0.1 µA 0.99 V PBOUT VOL –0.1 VCCLO VOL –0.1 PSHOLD Glitch immunity PSHOLD leakage current 1.05 1 VPSHOLD = 0.6 V V 80 –0.1 PSHOLD to enable propagation delay Pull-down resistor RPSHOLD connected internally during power-up 40/51 VPSHOLD = 5.5 V Doc ID 15453 Rev 7 195 300 µs 0.1 µA 30 µs 405 kΩ STM6600 - STM6601 Table 5. Symbol DC and AC characteristics DC and AC characteristics (continued) Parameter Test condition(1) Min. Typ.(2) Max. Unit 100 150 200 nA CSRD ISRD C SRD charging current VSRD C SRD voltage threshold VCC = 3.6 V, load on VREF pin 100 kΩ and mandatory 1 µF capacitor, TA = 25 °C 1.5 V tSRD Additional Smart Reset™ delay time External CSRD connected 10 s/µF VOL Output low voltage VCC = 2 V, ISINK = 1 mA, enable asserted VOH(5) Output high voltage VCC = 2 V, ISOURCE = 1 mA, enable asserted EN, EN tEN_OFF(6) enable off to enable on VCC ≥ 2.0 V 0.3 V VCC – 0.3 40 EN, EN leakage current VEN = 2 V, enable open drain VOL Output low voltage VCC = 2 V, ISINK = 1 mA, RST asserted tREC RST pulse width VCC ≥ 2.0 V 240 RST leakage current VRST = 3V –0.1 Output low voltage VCC = 2 V, ISINK = 1 mA, INT asserted Minimum INT pulse width VCC ≥ 2.0 V INT leakage current VINT = 3 V –0.1 1.5 V voltage reference VCC = 3.6 V, load on VREF pin 100 kΩ and mandatory 1 µF capacitor, TA = 25 °C 1.485 –1% V 64 –0.1 88 ms +0.1 µA 0.3 V 480 ms +0.1 µA 0.3 V 44 ms +0.1 µA 1.515 +1% V RST 360 INT VOL tINT_Min 20 32 VREF VREF 1.5 1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 1.6 V to 5.5 V (except where noted). 2. Typical values are at TA = +25 °C. 3. This blanking time allows the processor to start up correctly (see Figure 7, 8, 9, 10, 11, 12). 4. The internal pull-up resistor connected to the SR input is optional (see Table 10 for detailed device options). 5. Valid for push-pull only. 6. Minimal delay between enable off and enable on allows the application to power down properly. PB is ignored during this period. Doc ID 15453 Rev 7 41/51 Package mechanical data 8 STM6600 - STM6601 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 42/51 Doc ID 15453 Rev 7 STM6600 - STM6601 Package mechanical data Figure 41. TDFN12 (2 x 3 mm) package outline D A B INDEX AREA 0.10 C 2x E (D/2xE/2) 0.10 C TOP VIEW A A1 0.10 C C SEATING PLANE SIDE VIEW 0.08 C e b 1 6 12 7 0.10 C A B PIN#1 ID INDEX AREA L (D/2xE/2) BOTTOM VIEW 8070542_A Table 6. TDFN12 (2 x 3 mm) package mechanical data mm inches Symbol Min. Typ. Max. Min. Typ. Max. A 0.70 0.75 0.80 0.028 0.030 0.031 A1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 D 3.00 BSC 0.118 E 2.00 BSC 0.079 e 0.50 0.020 L 0.45 0.55 0.65 Doc ID 15453 Rev 7 0.018 0.022 0.026 43/51 Package mechanical data STM6600 - STM6601 Figure 42. TDFN12 (2 x 3 mm) recommended footprint X X X X X X X X $IMENSIONS MM INCHES !- Note: 44/51 Drawing not to scale. Doc ID 15453 Rev 7 STM6600 - STM6601 Package mechanical data Figure 43. Carrier tape for TDFN12 (2 mm x 3 mm) package P0 E P2 D T A0 F TOP COVER TAPE W B0 P1 CENTER LINES OF CAVITY K0 USER DIRECTION OF FEED AM03073v1 Table 7. Carrier tape dimensions for TDFN12 (2 mm x 3 mm) package Package W D TDFN12 12.00 ±0.30 1.50 +0.10/ –0.00 E P0 P2 F 1.75 4.00 2.00 5.50 ±0.10 ±0.10 ±0.10 ±0.05 A0 B0 K0 P1 T 2.30 ±0.10 3.20 ±0.10 1.10 ±0.01 4.00 ±0.10 0.30 ±0.05 Doc ID 15453 Rev 7 Unit Bulk Qty. mm 3000 45/51 Part numbering STM6600 - STM6601 9 Part numbering Table 8. STM6600 ordering information scheme Example: STM660 0 F Q 2 4 DM 6 Device type STM660 Startup process 0: PB must be held low until the PSHOLD confirmation Input and output types(1) A: active high EN output, long push asserts RST, pull-up on SR E: active high EN output, long push asserts RST, no resistor on SR F: active low EN output, long push asserts RST, no resistor on SR G: active high EN output, long push deasserts EN, no resistor on SR H: active low EN output, long push deasserts EN, no resistor on SR VTH+ threshold voltage(1) A: 2.50 V Q: 3.30 V S: 3.40 V U: 3.50 V VHYST voltage hysteresis(1) 2: 200 mV 5: 500 mV tON_BLANK blanking period(1) 2: 1.4 s (min.) 4: 5.6 s (min.) 5: 11.2 s (min.) Package DM: TDFN12 Temperature range 6: –40 °C to +85 °C Shipping method E: ECOPACK® package, tubes F: ECOPACK® package, tape and reel 1. Other options are offered. Minimum order quantities may apply. Please contact local ST sales office for availability. 46/51 Doc ID 15453 Rev 7 F STM6600 - STM6601 Table 9. Part numbering STM6601 ordering information scheme Example: STM660 1 G U 2 B DM 6 F Device type STM660 Startup process 1: PB can be released before the PSHOLD confirmation Input and output types(1) A: active high EN output, long push asserts RST, pull-up on SR B: active low EN output, long push asserts RST, pull-up on SR C: active high EN output, long push deasserts EN, pull-up on SR D: active low EN output, long push deasserts EN, pull-up on SR G: active high EN output, long push deasserts EN, no resistor on SR VTH+ threshold voltage(1) M: 3.10 V Q: 3.30 V S: 3.40 V U: 3.50 V VHYST voltage hysteresis(1) 2: 200 mV tON_BLANK blanking period(1) B: 1.4 s (min.) D: 5.6 s (min.) Package DM: TDFN12 Temperature range 6: –40 °C to +85 °C Shipping method E: ECOPACK® package, tubes F: ECOPACK® package, tape and reel 1. Other options are offered. Minimum order quantities may apply. Please contact local ST sales office for availability. Doc ID 15453 Rev 7 47/51 Product selector STM6600 - STM6601 10 Product selector Table 10. STM6600 product selector Full part number EN or EN(1) Internal Power-on Forced tON_BLANK tON_BLANK After resistor lockout power-off Top (s) (s) long (3) voltage on SR voltage marking at startup at reset push(2) VTH+ (V) VTH- (V) input (min.) (min.) STM6600AS24DM6F EN RST pull-up 3.40 3.20 5.6 5.6 pyww AS24 STM6600ES24DM6F(4) EN RST — 3.40 3.20 5.6 5.6 pyww ES24 STM6600FQ24DM6F(4) EN RST — 3.30 3.10 5.6 5.6 pyww FQ24 STM6600GS22DM6F(4) EN EN — 3.40 3.20 1.4 — pyww GS22 STM6600GS25DM6F(4) EN EN — 3.40 3.20 11.2 — pyww GS25 STM6600GU22DM6F(4) EN EN — 3.50 3.30 1.4 — pyww GU22 STM6600HA55DM6F(4) EN EN — 2.50 2.00 11.2 — pyww HA55 STM6600HQ25DM6F(4) EN EN — 3.30 3.10 11.2 — pyww HQ25 STM6600HU25DM6F(4) EN EN — 3.50 3.30 11.2 — pyww HU25 1. EN (or EN) output is push-pull. RST, INT, PBOUT and VCCLO outputs are open drain. 2. After tSRD expires through long push, either device reset (RST) will be activated for tREC (240 ms min.) or the EN (or EN) pin will be deasserted. The additional Smart Reset™ delay time, tSRD , can be adjusted by the user at 10 s/µF (typ.) by connecting the external capacitor to the CSRD pin. 3. Where “p” = assembly plant, “y” = assembly year (0 to 9) and “ww” = assembly work week (01 to 52). 4. Please contact local ST sales office for availability. 48/51 Doc ID 15453 Rev 7 STM6600 - STM6601 Table 11. Product selector STM6601 product selector Full part number EN or EN(1) Internal Power-on Forced tON_BLANK tON_BLANK After Top resistor lockout power-off (s) (s) long marking(3) voltage on SR voltage at startup at reset (2) push VTH+ (V) VTH- (V) input (min.) (min.) STM6601AQ2BDM6F EN RST pull-up 3.30 3.10 1.4 1.4 pyww AQ2B STM6601AU2DDM6F EN RST pull-up 3.50 3.30 5.6 5.6 pyww AU2D STM6601BM2DDM6F EN RST pull-up 3.10 2.90 5.6 5.6 pyww BM2D STM6601BS2BDM6F EN RST pull-up 3.40 3.20 1.4 1.4 pyww BS2B STM6601CM2DDM6F EN EN pull-up 3.10 2.90 5.6 — pyww CM2D STM6601CQ2BDM6F EN EN pull-up 3.30 3.10 1.4 — pyww CQ2B STM6601DS2BDM6F EN EN pull-up 3.40 3.20 1.4 — pyww DS2B STM6601GU2BDM6F(4) EN RST — 3.50 3.30 5.6 5.6 pyww GU2B 1. EN (or EN) output is push-pull. RST, INT, PBOUT and VCCLO outputs are open drain. 2. After tSRD expires through long push, either device reset (RST) will be activated for tREC (240 ms min.) or the EN (or EN) pin will be deasserted. The additional Smart Reset™ delay time, tSRD, can be adjusted by the user at 10 s/µF (typ.) by connecting the external capacitor to the CSRD pin. 3. Where “p” = assembly plant, “y” = assembly year (0 to 9) and “ww” = assembly work week (01 to 52). 4. Please contact local ST sales office for availability. Doc ID 15453 Rev 7 49/51 Revision history 11 Revision history Table 12. 50/51 STM6600 - STM6601 Document revision history Date Revision Changes 04-Mar-2009 1 Initial release. 05-Jun-2009 2 Updated text in Section 2, Section 3, Figure 11, 12; updated Figure 1, 7, 9, 14, 18, 19, 43, Table 3, 5, 8, 9, 10; added Figure 8, 10, Table 7; reformatted document. 23-Jul-2009 3 Updated text in Features, Table 1, 8, 9, and 10; reformatted document. 22-Oct-2009 4 Updated Section 2, Table 5, Table 10, Figure 1, 7, 8, 9, 10, 11, 12, 14, 18, title of Section 10; added Section 5: Typical operating characteristics (Figure 23 through 40); document status upgraded to full datasheet. 25-Jan-2010 5 Updated Figure 6, Section 2, Table 5; textual update to “Smart Reset™”. 13-Apr-2010 6 Updated Figure 1, 6, 7, 8, 9, 10, 11, 12, 13, Section 2, Section 3, Table 3, 5, 8, 9, 10. 07-Jun-2010 7 Reformatted Figure 1 and Figure 42, corrected typo in Section 3, added option A to Table 8, updated Table 10 and separated Table 10 to Table 10 and Table 11. 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