MICROCHIP 24LC02BT-ISNG

24AA00/24LC00/24C00
24AA014/24LC014
24AA02/24LC02B
24AA024/24LC024
24AA04/24LC04B
24AA16/24LC16B
24AA64/24LC64/24FC64
24AA256/24LC256/24FC256
24AA01/24LC01B
24C01C/24C02C
24AA025/24LC025
24AA08/24LC08B
24AA32A/24LC32A
24AA128/24LC128/24FC128
24AA512/24LC512/24FC512
24AA1025/24LC1025/24FC1025
I2C™ Serial EEPROM Family Data Sheet
Features:
Description:
• 128-bit through 1024 Kbit Devices
• Single Supply with Operation Down to 1.7V for
24AAXX Devices
• Low-Power CMOS Technology:
- 1 mA active current, typical
- 1 μA standby current, typical (I-temp)
• 2-Wire Serial Interface Bus, I2C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 400 kHz (≥ 2.5V): 24LCXX and 24AAXX
• 1 MHz (≥ 2.5V) and 400 kHz (1.7V): 24FCXX
• Self-Timed Write Cycle (including Auto-Erase)
• Page Write Buffer
• Hardware Write-Protect Available on Most
Devices
• Factory Programming (QTP) Available
• ESD Protection >4,000V
• 1 Million Erase/Write Cycles
• Data Retention >200 years
• 8-lead PDIP, SOIC, TSSOP and MSOP Packages
• 5-lead SOT-23 Package (Most 1-16 Kbit Devices)
• 8-lead 2x3mm and 5x6mm DFN Packages
Available
• Pb-Free and RoHS Compliant
• Available for Extended Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
The Microchip Technology Inc. 24CXX, 24LCXX,
24AAXX and 24FCXX (24XX*) devices are a family of
128-bit through 1024 Kbit Electrically Erased PROMs.
The devices are organized in blocks of x8-bit memory
with 2-wire serial interfaces. Low-voltage design
permits operation down to 1.7V (for 24AAXX devices),
with standby and active currents of only 1 μA and 1
mA, respectively. Devices 1 Kbit and larger have page
write capability. Parts having functional address lines
allow connection of up to 8 devices on the same bus.
The 24XX family is available in the standard 8-pin
PDIP, surface mount SOIC, TSSOP and MSOP packages. Most 128-bit through 16 Kbit devices are also
available in the 5-lead SOT-23 package. DFN
packages (2x3mm or 5x6mm) are also available. All
packages are Pb-free (Matte Tin) finish.
Note:
This document is an overview. For
detailed specifications, please consult the
individual product data sheet, available at
www.microchip.com.
*24XX is used in this document as a generic part
number for 24 series devices in this data sheet.
24XX64, for example, represents all voltages of the 64
Kbit device.
Package Types(1)
TSSOP/MSOP(2)
PDIP/SOIC
A0
1
8
VCC
(3)
SOT-23-5
(24XX00)
A0
1
8
VCC
A1
2
7
WP
A1
2
7
WP(3)
A2
3
6
SCL
A2
3
6
SCL
VSS
4
5
SDA
VSS
4
5
SDA
SOT-23-5
(all except 24XX00)
SCL
1
VSS
2
SDA
3
5
4
WP
VCC
© 2007 Microchip Technology Inc.
8 VCC
A1 2
7 WP(3)
A2 3
6 SCL
VSS 4
5 SDA
1
VSS
2
SDA
3
5
VCC
4
NC
Note 1:
Pins A0, A1, A2 and WP are not used by some
devices (no internal connections). See Table 1-1,
Device Selection Table, for details.
2:
Pins A0 and A1 are no-connects for the 24XX128
and 24XX256 MSOP devices.
3:
Pin 7 is “not used” for 24XX00, 24XX025 and
24C01C.
DFN
A0 1
SCL
DS21930C-page 1
24AAXX/24LCXX/24FCXX
TABLE 1-1:
DEVICE SELECTION TABLE
VCC
Range
Max. Clock
Frequency
24AA00
1.7-5.5V
400 kHz(1)
24LC00
2.5-5.5V
400 kHz(1)
24C00
4.5-5.5V
400 kHz
24AA01
1.7-5.5V
400 kHz (2)
24LC01B
2.5-5.5V
400 kHz
24AA014
1.7-5.5V
400 kHz(2)
24LC014
2.5-5.5V
400 kHz
24AA01H(6)
1.7-5.5v
(6)
2.5-5.5v
Part Number
Page
Size
WriteProtect
Array
Functional
Address
Pins
Temp.
Range
Packages(5)
128-bit devices
I
—
None
None
P, SN, ST, OT, MC
I
I, E
1 Kb devices
24LC01H
24C01C
I
P, SN, ST, MS, OT, MC
8 bytes
Entire Array
None
16 bytes
Entire Array
A0, A1, A2
400 kHz(1)
16 bytes
Upper Half
A0, A1, A2
I
P, SN, ST, MS, OT, MC
400 kHz(1)
16 bytes
Upper Half
A0, A1, A2
I, E
P, SN, ST, MS, OT, MC
16 bytes
None
A0, A1, A2
I, E
P, SN, ST, MC
8 bytes
Entire Array
None
16 bytes
Entire Array
A0, A1, A2
16 bytes
None
A0, A1, A2
4.5V-5.5V 400 kHz
I, E
I
P, SN, ST, MS, MC
I
2 Kb devices
24AA02
1.7-5.5V
400 kHz (2)
24LC02B
2.5-5.5V
400 kHz
24AA024
1.7-5.5V
400 kHz(2)
24LC024
2.5-5.5V
400 kHz
24AA025
1.7-5.5V
400 kHz(2)
24LC025
2.5-5.5V
400 kHz
24AA02H(6)
1.7-5.5v
400 kHz(1)
16 bytes
Upper Half
A0, A1, A2
I
P, SN, ST, MS, OT, MC
2.5-5.5v
kHz(1)
16 bytes
Upper Half
A0, A1, A2
I, E
P, SN, ST, MS, OT, MC
16 bytes
Upper Half
of Array
A0, A1, A2
I, E
P, SN, ST, MC
16 bytes
Entire Array
None
24LC02H(6)
24C02C
400
4.5-5.5V
400 kHz
24AA04
1.7-5.5V
400 kHz (2)
24LC04B
2.5-5.5V
400 kHz
24AA08
1.7-5.5V
400 kHz (2)
24LC08B
2.5-5.5V
400 kHz
24AA16
1.7-5.5V
400 kHz (2)
24LC16B
2.5-5.5V
400 kHz
24AA32A
1.7-5.5V
400 kHz (2)
24LC32A
2.5-5.5V
400 kHz
I
P, SN, ST, MS, OT, MC
I, E
I
P, SN, ST, MS, MC
I
I
P, SN, ST,MS, MC
I
4 Kb devices
I
P, SN, ST, MS, OT, MC
I, E
8 Kb devices
16 bytes
Entire Array
None
16 bytes
Entire Array
None
32 bytes
Entire Array
A0, A1, A2
I
P, SN, ST, MS, OT, MC
I, E
16 Kb devices
I
P, SN, ST, MS, OT, MC
I, E
32 Kb devices
I
P, SN, SM, ST, MS, MC
I, E
Note 1: 100 kHz for VCC <4.5V.
2: 100 kHz for VCC <2.5V.
3: 400 kHz for VCC <2.5V.
4: Pins A0 and A1 are no-connects for the 24XX128 and 24XX256 in the MSOP package.
5: P = 8-PDIP, SN = 8-SOIC (3.90 mm JEDEC), ST = 8-TSSOP, OT = 5 or 6-SOT23, MC = 2x3mm DFN,
MS = 8-MSOP, SM = 8-SOIC (200 mil EIAJ), MF = 5x6mm DFN.
6: Available Q4 2007.
DS21930C-page 2
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
TABLE 1-1:
DEVICE SELECTION TABLE (CONTINUED)
VCC
Range
Max. Clock
Frequency
24AA64
1.7-5.5V
400 kHz (2)
24LC64
2.5-5.5V
400 kHz
24FC64
1.7-5.5V
1 MHz(3)
24AA128
1.7-5.5V
400 kHz (2)
24LC128
2.5-5.5V
400 kHz
24FC128
1.7-5.5V
1 MHz(3)
24AA256
1.7-5.5V
400 kHz (2)
24LC256
2.5-5.5V
400 kHz
24FC256
1.7-5.5V
1 MHz(3)
1.7-5.5V
400 kHz (2)
2.5-5.5V
400 kHz
Part Number
Page
Size
WriteProtect
Array
Functional
Address
Pins
Temp.
Range
Packages(5)
I
P, SN, SM, ST, MS, MC
32 bytes
Entire Array
A0, A1, A2
I, E
64 Kb devices
I
128 Kb devices
64 bytes
Entire Array
A0, A1,
A2(4)
I
P, SN, SM, ST, MS, MF
I, E
I
256 Kb devices
64 bytes
Entire Array
A0, A1,
A2(4)
I
P, SN, SM, ST, MS, MF
I, E
I
512 Kb devices
24AA512
24LC512
24FC512
1.7-5.5V(3) 1 MHz
128
bytes
I
Entire Array
A0, A1, A2
P, SM, MF,
I, E
I
1024 Kb devices
24AA1025
24LC1025
24FC1025
1.7-5.5V
2.5-5.5V
400 kHz (2)
400 kHz
1.7-5.5V(3) 1 MHz
I
128
bytes
Entire Array
A0, A1
P, SM
I, E
I
Note 1: 100 kHz for VCC <4.5V.
2: 100 kHz for VCC <2.5V.
3: 400 kHz for VCC <2.5V.
4: Pins A0 and A1 are no-connects for the 24XX128 and 24XX256 in the MSOP package.
5: P = 8-PDIP, SN = 8-SOIC (3.90 mm JEDEC), ST = 8-TSSOP, OT = 5 or 6-SOT23, MC = 2x3mm DFN,
MS = 8-MSOP, SM = 8-SOIC (200 mil EIAJ), MF = 5x6mm DFN.
6: Available Q4 2007.
© 2007 Microchip Technology Inc.
DS21930C-page 3
24AAXX/24LCXX/24FCXX
2.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 2-1:
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C
DC CHARACTERISTICS
Param.
No.
D1
Sym.
Characteristic
—
A0, A1, A2, SCL, SDA and
WP pins:
Min.
Max.
Units
—
—
—
Conditions
—
D2
VIH
High-level input voltage
0.7 VCC
—
V
—
D3
VIL
Low-level input voltage
—
0.3 VCC
0.2 VCC
V
V
VCC ≥ 2.5V
VCC < 2.5V
D4
VHYS
Hysteresis of Schmitt Trigger
inputs (SDA, SCL pins)
0.05 VCC
—
V
(Note 1)
D5
VOL
Low-level output voltage
—
0.40
V
IOL = 3.0 mA @ VCC = 2.5V
D6
ILI
Input leakage current
—
±1
μA
VIN = VSS or VCC
D7
ILO
Output leakage current
—
±1
μA
VOUT = VSS or VCC
D8
CIN,
COUT
Pin capacitance
(all inputs/outputs)
—
10
pF
VCC = 5.0V (Note 1)
TA = 25°C, FCLK = 1 MHz
D9
ICC Read Operating current
—
500
400
1
μA
μA
mA
24XX1025
24XX128, 256, 512:
All except 24XX128, 256, 512,
1025:
(VCC = 5.5V, SCL = 400 kHz)
ICC Write
—
3
mA
5
mA
All except 24XX512 and
24XX1025
24XX512 and 24XX1025
(VCC = 5.5V)
—
—
1
5
μA
μA
All except 24XX1025
24XX1025
—
50
μA
24C01C and 24C02C only
(TA = -40°C to +85°C)
—
5
μA
All except 24XX1025
(TA = -40°C to +125°C)
SCL = SDA = VCC = 5.5V
A0, A1, A2, WP = VSS or VCC
D10
ICCS
Standby current
Note 1: This parameter is periodically sampled and not 100% tested.
DS21930C-page 4
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
TABLE 2-2:
AC CHARACTERISTICS – ALL EXCEPT 24XX00, 24C01C
AND 24C02C
Electrical Characteristics:
Industrial (I):
VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C
AC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
Conditions
1
FCLK
Clock frequency
—
—
—
—
100
400
400
1000
kHz
1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.7V ≤ VCC < 2.5V 24FCXXX
2.5V ≤ VCC ≤ 5.5V 24FCXXX
2
THIGH
Clock high time
4000
600
600
500
—
—
—
—
ns
1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.7V ≤ VCC < 2.5V 24FCXXX
2.5V ≤ VCC ≤ 5.5V 24FCXXX
3
TLOW
Clock low time
4700
1300
1300
500
—
—
—
—
ns
1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.7V ≤ VCC < 2.5V 24FCXXX
2.5V ≤ VCC ≤ 5.5V 24FCXXX
4
TR
SDA and SCL rise time
(Note 1)
—
—
—
1000
300
300
ns
1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.7V ≤ VCC ≤ 5.5V 24FCXXX
5
TF
SDA and SCL fall time
(Note 1)
—
—
300
100
ns
All except 24FCXXX
1.7V ≤ VCC ≤ 5.5V 24FCXXX
6
THD:STA Start condition hold time
4000
600
600
250
—
—
—
—
ns
1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.7V ≤ VCC < 2.5V 24FCXXX
2.5V ≤ VCC ≤ 5.5V 24FCXXX
7
TSU:STA Start condition setup time
4700
600
600
250
—
—
—
—
ns
1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.7V ≤ VCC < 2.5V 24FCXXX
2.5V ≤ VCC ≤ 5.5V 24FCXXX
8
THD:DAT Data input hold time
0
—
ns
(Note 2)
9
TSU:DAT Data input setup time
250
100
100
—
—
—
ns
1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.7V ≤ VCC ≤ 5.5V 24FCXXX
10
TSU:STO Stop condition setup time
4000
600
600
250
—
—
—
—
ns
1.7 V ≤ VCC < 2.5V
2.5 V ≤ VCC ≤ 5.5V
1.7V ≤ VCC < 2.5V 24FCXXX
2.5 V ≤ VCC ≤ 5.5V 24FCXXX
11
TSU:WP WP setup time
(32K and above only)
4000
600
600
—
—
—
ns
1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.7V ≤ VCC ≤ 5.5V 24FCXXX
12
THD:WP WP hold time
(32K and above only)
4700
1300
1300
—
—
—
ns
1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.7V ≤ VCC ≤ 5.5V 24FCXXX
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site:
www.microchip.com.
4: 24FCXXX denotes the 24FC64, 24FC128, 24FC256, 24FC512 and 24FC1025 devices.
© 2007 Microchip Technology Inc.
DS21930C-page 5
24AAXX/24LCXX/24FCXX
TABLE 2-2:
AC CHARACTERISTICS – ALL EXCEPT 24XX00, 24C01C
AND 24C02C (CONTINUED)
Electrical Characteristics:
Industrial (I):
VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C
AC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
—
—
—
—
3500
900
900
400
ns
1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.7V ≤ VCC < 2.5V 24FCXXX
2.5V ≤ VCC ≤ 5.5V 24FCXXX
4700
1300
1300
500
—
—
—
—
ns
1.7V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.7V ≤ VCC < 2.5V 24FCXXX
2.5V ≤ VCC ≤ 5.5V 24FCXXX
10 + 0.1CB
250
250
ns
All except 24FCXXX (Note 1)
24FCXXX (Note 1)
All except 24FCXXX (Note 1)
13
TAA
Output valid from clock
(Note 2)
14
TBUF
Bus free time: Time the bus
must be free before a new
transmission can start
15
TOF
Output fall time from VIH
minimum to VIL maximum
CB ≤ 100 pF
16
TSP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
17
TWC
Write cycle time (byte or
page)
—
5
ms
18
—
Endurance
1,000,000
—
Conditions
cycles 25°C (Note 3)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site:
www.microchip.com.
4: 24FCXXX denotes the 24FC64, 24FC128, 24FC256, 24FC512 and 24FC1025 devices.
DS21930C-page 6
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
TABLE 2-3:
AC CHARACTERISTICS – 24XX00, 24C01C AND 24C02C
All Parameters apply across all
recommended operating ranges
unless otherwise noted
Parameter
TA = -40°C to +85°C, VCC = 1.7V to 5.5V
TA = -40°C to +125°C, VCC = 4.5V to 5.5V
Industrial (I):
Automotive (E):
Symbol
Min.
Max.
Units
Conditions
Clock frequency
FCLK
—
—
—
100
100
400
kHz
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Clock high time
THIGH
4000
4000
600
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Clock low time
TLOW
4700
4700
1300
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
SDA and SCL rise time
(Note 1)
TR
—
—
—
1000
1000
300
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
SDA and SCL fall time
TF
—
300
ns
(Note 1)
Start condition hold time
THD:STA
4000
4000
600
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Start condition setup time
TSU:STA
4700
4700
600
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Data input hold time
THD:DAT
0
—
ns
(Note 2)
Data input setup time
TSU:DAT
250
250
100
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Stop condition setup time
TSU:STO
4000
4000
600
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Output valid from clock
(Note 2)
TAA
—
—
—
3500
3500
900
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
4700
4700
1300
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.7V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Bus free time: Time the bus must TBUF
be free before a new transmission can start
Output fall time from VIH
minimum to VIL maximum
TOF
20+0.1
CB
250
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppression
(SDA and SCL pins)
TSP
—
50
ns
(Note 1)
Write cycle time
TWC
—
4
1.5
ms
24XX00
24C01C, 24C02C
1,000,000
—
cycles
Endurance
Note 1:
2:
3:
(Note 3)
Not 100% tested. CB = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site:
www.microchip.com.
© 2007 Microchip Technology Inc.
DS21930C-page 7
24AAXX/24LCXX/24FCXX
FIGURE 2-1:
EXAMPLE BUS TIMING DATA
5
SCL
7
SDA
IN
3
4
D4
2
8
10
9
6
16
14
13
SDA
OUT
WP
DS21930C-page 8
(protected)
(unprotected)
11
12
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
8-Pin PDIP
and SOIC
8-Pin
TSSOP and
MSOP
5-Pin SOT-23
24XX00
A0
1
1(1)
—
—
1
User configurable Chip Select(3)(4)
A1
2
2(1)
—
—
2
User configurable Chip Select(3)(4)
A2
3
3
—
—
3
User configurable Chip Select(3)(4)
VSS
4
4
2
2
4
Ground
Pin Name
5-Pin SOT-23
8-Pin
All except
5x6 DFN and
24XX00
2x3 DFN
Function
SDA
5
5
3
3
5
Serial Data
SCL
6
6
1
1
6
Serial Clock
(NC)
—
—
4
—
—
Not Connected
WP
7(2)
7(2)
—
5
7
Write-Protect Input
8
8
5
4
8
Power Supply
VCC
Note 1:
2:
3:
4:
3.1
Pins 1 and 2 are not connected for the 24XX128 and 24XX256 MSOP packages.
Pin 7 is not used for 24XX00, 24XX025 and 24C01C.
Pins A0, A1 and A2 are not used by some devices (no internal connections). See Table 1-1 for details.
Pin A2 should be tied to a Logic High in the 24XX1025 for proper operation.
A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 pins are not used by the 24XX01
through 24XX16 devices.
The A0, A1 and A2 inputs are used by the 24C01C,
24C02C, 24XX014, 24XX024, 24XX025 and the
24XX32 through 24XX1025 for multiple device operations. The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
For the 24XX128 and 24XX256 in the MSOP package
only, pins A0 and A1 are not connected.
3.2
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
3.3
Serial Clock (SCL)
Up to eight devices (two for the 24XX128 and
24XX256 MSOP package) may be connected to the
same bus by using different Chip Select bit
combinations.
This input is used to synchronize the data transfer to
and from the device.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected. See Table 1-1 for the write-protect
scheme of each device.
Note:
In the 24XX1025, the A2 pin is not configurable, it must be tied to VCC in order for
this device to operate properly.
© 2007 Microchip Technology Inc.
3.4
3.5
Write-Protect (WP)
Power Supply (VCC)
A VCC threshold detect circuit is employed which
disables the internal erase/write logic if VCC is below
1.5V at nominal conditions. For the 24C00, 24C01C
and 24C02C devices, the erase/write logic is disabled
below 3.8V at nominal conditions.
DS21930C-page 9
24AAXX/24LCXX/24FCXX
4.0
FUNCTIONAL DESCRIPTION
Each 24XX device supports a bidirectional, 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as a transmitter, while a
device receiving data is defined as a receiver. The bus
has to be controlled by a master device which generates the Serial Clock (SCL), controls the bus access
and generates the Start and Stop conditions, while the
24XX works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
Block Diagram
A0*A1*A2* WP*
I/O
Control
Logic
HV Generator
Memory
Control
Logic
XDEC
EEPROM
Array
Page Latches*
I/O
SCL
YDEC
SDA
VCC
VSS
Sense Amp.
R/W Control
* A0, A1, A2, WP and page latches are not used by some
devices.
See Table 1-1, Device Selection Table, for details.
DS21930C-page 10
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
5.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 5-1).
5.1
Bus Not Busy (A)
Both data and clock lines remain high.
5.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
5.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
5.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device.
© 2007 Microchip Technology Inc.
DS21930C-page 11
24AAXX/24LCXX/24FCXX
5.5
Acknowledge
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end-ofdata to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX) will leave the data line
high to enable the master to generate the Stop
condition (Figure 5-2).
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
During a write cycle, the 24XX will not
acknowledge commands.
FIGURE 5-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
Start
Condition
Address or
Acknowledge
Valid
(C)
(A)
SCL
SDA
FIGURE 5-2:
Stop
Condition
Data
Allowed
to Change
ACKNOWLEDGE TIMING
Acknowledge
bit
1
SCL
SDA
2
3
4
5
6
7
Data from transmitter
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
DS21930C-page 12
8
9
1
2
3
Data from transmitter
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
5.6
Device Addressing For Devices
Without Functional Address Pins
The last bit of the control byte defines the operation to
be performed. When set to ‘1’, a read operation is
selected. When set to ‘0’ a write operation is selected.
Following the Start condition, the 24XX monitors the
SDA bus. Upon receiving a ‘1010’ code, the block
select bits and the R/W bit, the slave device outputs an
Acknowledge signal on the SDA line. The address byte
follows the acknowledge.
A control byte is the first byte received following the
Start condition from the master device (Figure 5-3).
The control byte begins with a four-bit control code. For
the 24XX, this is set as ‘1010’ binary for read and write
operations. The next three bits of the control byte are
the block-select bits (B2, B1, B0). They are used by the
master device to select which of the 256-word blocks of
memory are to be accessed. These bits are in effect the
three Most Significant bits of the word address. Note
that B2, B1 and B0 are “don’t care” for the 24XX00, the
24XX01 and 24XX02. B2 and B1 are “don’t care” for
the 24XX04. B2 is “don’t care” for the 24XX08.
FIGURE 5-3:
CONTROL AND ADDRESS BYTE ASSIGNMENTS FOR
DEVICES WITHOUT ADDRESS PINS
Address Byte
Control Byte
24XX00
S
24XX01
S
1
0
1
0
x
x
24XX02
S
1
0
1
0
x
x
24XX04
S
1
0
1
0
x
x
24XX08
S
1
0
1
0
x
B1 B0
24XX016
S
Start bit
1
1
0
0
1
1
Control Code
0
0
x
x
x
R/W
ACK
x
x
x
x
A3
.
.
A0
x
R/W
ACK
x
A6
.
.
.
.
.
A0
x
R/W
ACK
A7
.
.
.
.
.
.
A0
B0
R/W
ACK
A7
.
.
.
.
.
.
A0
R/W
ACK
A7
.
.
.
.
.
.
A0
ACK
A7
.
.
.
.
.
.
A0
B2 B1 B0
Block Select bits
R/W
Acknowledge
bit
Read/Write bit (Read = 1, Write = 0)
x = “don’t care” bit
© 2007 Microchip Technology Inc.
DS21930C-page 13
24AAXX/24LCXX/24FCXX
5.7
Device Addressing For Devices
With Functional Address Pins
For higher density devices (24XX32 through
24XX1025), the next two bytes received define the
address of the first data byte. Depending on the product density, not all bits in the address high byte are
used. A15, A14, A13 and A12 are “don’t care” for
24XX32. A15, A14 and A13 are “don’t care” for
24XX64. A15 and A14 are “don’t care” for 24XX128.
A15 is “don’t care” for 24XX256. All address bits are
used for the 24XX512 and 24XX1025. The upper
address bits are transferred first, followed by the Less
Significant bits.
A control byte is the first byte received following the
Start condition from the master device (Figure 5-4).
The control byte begins with a 4-bit control code. For
the 24XX, this is set as ‘1010’ binary for read and write
operations. The next three bits of the control byte are
the Chip Select bits (A2, A1, A0). The Chip Select bits
allow the use of up to eight 24XX devices on the same
bus and are used to select which device is accessed.
The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1
and A0 pins for the device to respond. These bits are,
in effect, the three Most Significant bits of the word
address.
Following the Start condition, the 24XX monitors the
SDA bus. Upon receiving a ‘1010’ code, appropriate
device select bits and the R/W bit, the slave device outputs an Acknowledge signal on the SDA line. The
address byte(s) follow the acknowledge.
For 24XX128 and 24XX256 in the MSOP package, the
A0 and A1 pins are not connected. During device
addressing, the A0 and A1 Chip Select bits (Figure 5-4)
should be set to ‘0’. Only two 24XX128 or 24XX256
MSOP packages can be connected to the same bus.
The 24XX1025 has an internal address boundary
limitation that is divided into two segments of 512 Kbits.
Block select bit ‘B0’ is used to control access to each
segment. Contiguous writes cannot be performed
across this boundary.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’, a read operation is
selected. When set to a ‘0’, a write operation is
selected.
FIGURE 5-4:
CONTROL AND ADDRESS BYTE ASSIGNMENTS FOR
DEVICES WITH ADDRESS PINS
Control Byte
Address Byte
24C01C
S
1
0
1
0
A2
A1
A0
R/W
ACK
x
A6
.
.
.
.
.
A0
24C02C
S
1
0
1
0
A2
A1
A0
R/W
ACK
A7
.
.
.
.
.
.
A0
S
1
0
1
0
A2
A1
A0
R/W
ACK
A7
.
.
.
.
.
.
A0
24XX024/025
Address High Byte
Control Byte
24XX32
S
1
0
1
0 A2 A1 A0 R/W ACK
x
x
x
24XX64
S
1
0
1
0 A2 A1 A0 R/W ACK
x
x
x
24XX128
S
1
0
1
0 A2 A1 A0 R/W ACK
x
x
24XX256
S
1
0
1
0 A2 A1 A0 R/W ACK
x
24XX512
S
1
0
1
24XX1025
S
1
0
1
Start bit
Address Low Byte
A11
A10
A9 A8
A7
.
.
.
.
.
.
A0
A12 A11
A10
A9 A8
A7
.
.
.
.
.
.
A0
A13 A12 A11
A10
A9 A8
A7
.
.
.
.
.
.
A0
A14 A13 A12 A11
A10
A9 A8
A7
.
.
.
.
.
.
A0
0 A2 A1 A0 R/W ACK
A15 A14 A13 A12 A11
A10
A9 A8
A7
.
.
.
.
.
.
A0
0 B0 A1 A0 R/W ACK
A15 A14 A13 A12 A11
A10
A9 A8
A7
.
.
.
.
.
.
A0
Control Code Chip Select bits*
x
Acknowledge
bit
Read/Write bit
(Read = 1, Write = 0)
x = “don’t care” bit
* Chip Select bits A1 and A0 must be set to ‘0’ for 24XX128/256 devices in the MSOP package.
DS21930C-page 14
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
5.7.1
CONTIGUOUS ADDRESSING
ACROSS MULTIPLE DEVICES
Chip Select bits A2, A1 and A0 can be used to expand
the contiguous address space by adding up to eight
24XXs on the same bus. Software can use the three
address bits of the control byte as the three Most
Significant bits of the address byte. For example, in the
24XX32 devices, software can use A0 of the control
byte as address bit A12; A1 as address bit A13; and A2
as address bit A14 (Table 5-1). It is not possible to
sequentially read across device boundaries.
TABLE 5-1:
CONTROL BYTE ADDRESS BITS
Maximum
Devices
Maximum
Contiguous
Address Space
Chip Select Bit
A2
Chip Select Bit Chip Select Bit
A1
A0
1K (24C01C)
8
8 Kb
A10
A9
A8
1K (24XX014)
8
8 Kb
A10
A9
A8
A8
2K (24C02C)
8
16 Kb
A10
A9
2K (24XX024/025)
8
16 Kb
A10
A9
A8
32K (24XX32)
8
256 Kb
A14
A13
A12
64K (24XX64)
8
512 Kb
A15
A14
A13
128K (24XX128)
8(1)
1 Mb
A16*
A15*
A14
256K (24XX256)
8(1)
2 Mb
A17*
A16*
A15
8
4 Mb
A18
A17
A16
4(2)
4 Mb
B0(3)
A17
A16
512K (24XX512)
1024K (24XX1025)
Note 1:
2:
3:
Up to two 24XX128 or 24XX256 devices in the MSOP package can be added for up to 256 kb or 512 kb of
address space, respectively. Bits A0 and A1 must be set to ‘0’.
Using the block select bit ‘B0’, up to four 24XX1025 devices can be cascaded together.
For proper operation of the 24XX1025 the A2 pin must be tied to a logic high. Software addressing uses
B0 to select between upper and lower 512 Kbit segments of memory.
© 2007 Microchip Technology Inc.
DS21930C-page 15
24AAXX/24LCXX/24FCXX
6.0
WRITE OPERATIONS
6.1
Byte Write
For the 24XX00 devices, only the lower four address
bits are used by the device. The upper four bits are
“don’t cares.”
After receiving the ACK from the 24XX acknowledging
the final address byte, the master device transmits the
data word to be written into the addressed memory
location. The 24XX acknowledges again and the
master generates a Stop condition, which initiates the
internal write cycle.
A byte write operation begins with a Start condition
from the master followed by the four-bit control code
(see Figure 6-1 and Figure 6-2). The next 3 bits are
either the Block Address bits (for devices without
address pins) or the Chip Select bits (for devices with
address pins). Then the master transmitter clocks the
R/W bit (which is a logic low) onto the bus. The slave
then generates an Acknowledge bit during the ninth
clock cycle.
If an attempt is made to write to an array with the WP
pin held high, the device will acknowledge the
command, but no write cycle will occur, no data will be
written, and the device will immediately accept a new
command. After a byte Write command, the internal
address counter will increment to the next address
location. During a write cycle, the 24XX will not
acknowledge commands.
The next byte transmitted by the master is the address
byte (for 128-bit to 16 Kbit devices) or the high-order
address byte (for 32-1024 Kbit devices). For 32 through
1024 Kbit devices, the high-order address byte is
followed by the low-order address byte. In either case,
each address byte is acknowledged by the 24XX and
the address bits are latched into the internal address
counter of the 24XX.
FIGURE 6-1:
BYTE WRITE: 128-BIT TO 16 KBIT DEVICES
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Control
Byte
Address
Byte
P
FIGURE 6-2:
SDA Line
Bus Activity
DS21930C-page 16
A
C
K
A
C
K
Bus Activity
Bus Activity
Master
S
T
O
P
Data
Byte
A
C
K
BYTE WRITE: 32 TO 1024 KBIT DEVICES
S
T
A
R
T
High Order
Address Byte
Control
Byte
Low Order
Address Byte
S
T
O
P
Data
Byte
S
P
A
C
K
A
C
K
A
C
K
A
C
K
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
6.2
Page Write
6.3
The write control byte, word address byte(s), and the
first data byte are transmitted to the 24XX in much the
same way as in a byte write (see Figure 6-3 and
Figure 6-4). The exception is that instead of generating
a Stop condition, the master transmits up to one page
of bytes(1), which is temporarily stored in the on-chip
page buffer. This data is then written into memory once
the master has transmitted a Stop condition. Upon
receipt of each word, the internal address counter is
incremented by one. If the master should transmit more
than one page of data prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte
write operation, once the Stop condition is received, an
internal write cycle begins. During the write cycle, the
24XX will not acknowledge commands.
Write-Protection
The WP pin allows the user to write-protect the array
when the pin is tied to VCC. See Device Selection
Table 1-1 for the write-protect scheme of each device.
If tied to VSS, the write protection is disabled. Please
refer to the product data sheet for complete details.
Note:
Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses
that are integer multiples of the page
buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size – 1]. If a Page Write
command attempts to write across a
physical page boundary, the result is
that the data wraps around to the
beginning of the current page (overwriting data previously stored there),
instead of being written to the next
page, as might be expected. It is therefore necessary for the application software to prevent page write operations
that would attempt to cross a page
boundary.
Page writes can be any number of bytes within a page
(up to the page size), starting at any address. Only the
data bytes being addressed will be changed within the
page.
If an attempt is made to write to the array with the WP
pin held high, the device will acknowledge the
command, but no write cycle will occur, no data will be
written and the device will immediately accept a new
command.
Note 1: See Device Selection Table 1-1 for the
page size of each device.
FIGURE 6-3:
PAGE WRITE: 1 KB TO 16 KBIT DEVICES
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Control
Byte
Address
Byte
Bus Activity
Bus Activity
Master
SDA Line
S
T
O
P
Final
Data Byte*
P
A
C
K
FIGURE 6-4:
Second
Data Byte
Initial
Data Byte
A
C
K
A
C
K
A
C
K
A
C
K
PAGE WRITE: 32 TO 1024 KBIT DEVICES
S
T
A
R
T
Control
Byte
High Order
Address Byte
S
T
O
P
Final
Data Byte*
Initial
Data Byte
Low Order
Address Byte
P
S
Bus Activity
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
* See Table 1-1 for maximum number of data bytes in a page.
© 2007 Microchip Technology Inc.
DS21930C-page 17
24AAXX/24LCXX/24FCXX
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge commands
during a write cycle, this can be used to determine
when the cycle is complete (This feature can be used
to maximize bus throughput). Once the Stop condition
for a Write command has been issued from the master,
the device initiates the internally timed write cycle. ACK
polling can be initiated immediately. This involves the
master sending a Start condition, followed by the control byte for a Write command (R/W = 0). If the device
is still busy with the write cycle, then no ACK will be
returned. If no ACK is returned, the Start bit and control
byte must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then proceed with the next Read or Write command. See
Figure 7-1 for flow diagram.
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
DS21930C-page 18
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
8.0
READ OPERATION
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the byte address must first
be set. This is done by sending the byte address to the
24XX as part of a write operation (R/W bit set to ‘0’).
Once the byte address is sent, the master generates a
Start condition following the acknowledge. This terminates the write operation, but not before the internal
address counter is set. The master then issues the
control byte again, but with the R/W bit set to a ‘1’. The
24XX will then issue an acknowledge and transmit the
8-bit data byte. The master will not acknowledge the
transfer but does generate a Stop condition, which
causes the 24XX to discontinue transmission
(Figure 8-2 and Figure 8-3). After a random Read
command, the internal address counter will increment
to the next address location.
Read operations are initiated in much the same way as
write operations with the exception that the R/W bit of
the control byte is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24XX contains an address counter that maintains
the address of the last byte accessed, internally incremented by ‘1’. Therefore, if the previous read or write
operation was to address ‘n’ (n is any legal address),
the next current address read operation would access
data from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the 24XX issues an acknowledge and transmits the
8-bit data byte. The master will not acknowledge the
transfer, but does generate a Stop condition and the
24XX discontinues transmission (Figure 8-1).
FIGURE 8-1:
CURRENT ADDRESS
READ
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Control
Byte
P
A
C
K
FIGURE 8-2:
N
O
A
C
K
RANDOM READ: 128-BIT TO 16 KBIT DEVICES
S
T
A
R
T
Bus Activity
Master
Control
Byte
S
T
A
R
T
Address
Byte (n)
S
SDA Line
FIGURE 8-3:
Control
Byte
S
T
O
P
Data
Byte
P
S
A
C
K
Bus Activity
SDA Line
S
T
O
P
Data
Byte
Bus Activity
Bus Activity
Master
Random Read
A
C
K
A
C
K
N
O
A
C
K
RANDOM READ: 32 TO 1024 KBIT DEVICES
S
T
A
R
T
Control
Byte
High Order
Address Byte
S
T
A
R
T
Low Order
Address Byte
S
Bus Activity
© 2007 Microchip Technology Inc.
Control
Byte
S
T
O
P
Data
Byte
S
A
C
K
A
C
K
A
C
K
P
A
C
K
N
O
A
C
K
DS21930C-page 19
24AAXX/24LCXX/24FCXX
8.3
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24XX transmits the
first data byte, the master issues an acknowledge as
opposed to the Stop condition used in a random read.
This acknowledge directs the 24XX to transmit the next
sequentially addressed data byte (Figure 8-4). Following the final byte transmitted to the master, the master
will NOT generate an acknowledge but will generate a
Stop condition. To provide sequential reads, the 24XX
contains an internal Address Pointer which is incremented by one at the completion of each operation.
This Address Pointer allows the entire memory contents to be serially read during one operation. If the last
address byte in the array is acknowledged, the Address
Pointer will roll over to address 0x00.
FIGURE 8-4:
Bus Activity
Master
SEQUENTIAL READ
Control
Byte
Initial
Data Byte
Second
Data Byte
S
T
O
P
Final
Data Byte
Third
Data Byte
P
SDA Line
Bus Activity
DS21930C-page 20
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
APPENDIX A:
REVISION HISTORY
Revision A
Original release of document. Combined Serial
EEPROM 24XXX device data sheets.
Revision B (02/2007)
Change 1.8V to 1.7V; Removed 14-Lead TSSOP
Package; Replaced Package Drawings; Revised
Product ID Section. Updates throughout.
Revision C (07/2007)
Added 24AA1025/LC1025/FC1025 part; Updates
throughout; Replaced Package Drawings (Rev. AP).
© 2007 Microchip Technology Inc.
DS21930C-page 21
24AAXX/24LCXX/24FCXX
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
Example:
8-Lead PDIP
24LC01B
I/P e3 1L7
0528
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP Package Marking
Device
Line 1
Marking
Device
Line 1
Marking
24AA00
24AA00
24LC00
24AA01
24AA01
24LC01B
24LC01B
24LC00
24AA014
24AA014
24LC014
24LC014
24AA02
24AA02
24LC02B
24LC02B
24AA024
24AA024
24LC024
24LC024
24AA025
24AA025
24LC025
24LC025
24AA04
24AA04
24LC04B
24LC04B
24AA08
24AA08
24LC08B
24LC08B
24AA16
24LC16B
24LC16B
24AA32A
24LC32A
24LC32A
24AA16
24AA32A
Device
24C00
Line 1
Marking
Device
Line 1
Marking
24C00
24C01C
24C01C
24C02C
24C02C
24AA64
24AA64
24LC64
24LC64
24FC64
24FC64
24AA128
24AA128
24LC128
24LC128
24FC128
24FC128
24AA256
24AA256
24LC256
24LC256
24FC256
24FC256
24AA512
24AA512
24LC512
24LC512
24FC512
24FC512
24AA1025
24AA1025
24LC1025
24LC1025
24FC1025
24FC1025
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
Part number or part number code
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn) plated devices
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
DS21930C-page 22
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
8-Lead SOIC
XXXXXXXX
XXXXXYYWW
NNN
Example:
24LC01BI
SN e3 0528
1L7
8-Lead SOIC Package Marking
Device
Line 1
Marking
Device
Line 1
Marking
24AA00
24AA00T
24LC00
24AA01
24AA01T
24LC01B
24LC01BT
24LC00T
24AA014
24AA014T
24LC014
24LC014T
24AA02
24AA02T
24LC02B
24LC02BT
24AA024
24AA024T
24LC024
24LC024T
24AA025
24AA025T
24LC025
24LC025T
Device
24C00
Line 1
Marking
Line 1
Marking
Device
24C00T
24C01C
24C01CT
24C02C
24C02CT
24AA04
24AA04T
24LC04B
24LC04BT
24AA08
24AA08T
24LC08B
24LC08BT
24AA16
24AA16T
24LC16B
24LC16BT
24AA32A
24AA32AT
24LC32A
24LC32AT
24AA64
24AA64T
24LC64
24LC64T
24FC64
24FC64T
24AA128
24AA128T
24LC128
24LC128T
24FC128
24FC128T
24AA256
24AA256T
24LC256
24LC256T
24FC256
24FC256T
24AA512
24AA512T
24LC512
24LC512T
24FC512
24FC512T
24AA1025
24LC1025
24LC1025
24FC1025
24FC1025
24AA1025
Note:
T = Temperature range: I = Industrial, E = Extended
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
Part number or part number code
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn) plated devices
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
© 2007 Microchip Technology Inc.
DS21930C-page 23
24AAXX/24LCXX/24FCXX
Example:
8-Lead 2x3 DFN
244
506
L7
XXX
YWW
NN
8-Lead 2x3mm DFN Package Marking
Device
24AA00
Industrial
Line 1
Marking
201
Device
24LC00
Industrial
Line 1
Marking
E-Temp
Line 1
Marking
204
205
24AA01
211
24LC01B
214
215
24AA014
2N1
24LC014
2N4
2N5
24AA02
221
24LC02B
224
225
24AA024
2P1
24LC024
2P4
2P5
24AA025
2R1
24LC025
2R4
2R5
24AA04
231
24LC04B
234
235
24AA08
241
24LC08B
244
245
24AA16
251
24LC16B
254
255
24AA32A
261
24LC32A
264
265
24AA64
271
24LC64
274
275
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
Note:
DS21930C-page 24
Industrial
Line 1
Marking
E-Temp
Line 1
Marking
24C00
207
208
24C01C
2N7
2N8
24C02C
2P7
2P8
24FC64
27A
27B
Device
Part number or part number code
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn) plated devices
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
Example:
8-Lead DFN
24AA128
I/MF e3
0528
1L7
XXXXXXX
T/XXXXX
YYWW
NNN
8-Lead 5x6mm DFN Package Marking
Device
Line 1
Marking
Device
Line 1
Marking
Device
Line 1
Marking
24AA128
24AA128
24LC128
24LC128
24FC128
24FC128
24AA256
24AA256
24LC256
24LC256
24FC256
24FC256
24AA512
24AA512
24LC512
24LC512
24FC512
24FC512
Note:
Temperature range (T) listed on second line. I = Industrial, E = Extended
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
Part number or part number code
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn) plated devices
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
DS21930C-page 25
24AAXX/24LCXX/24FCXX
Example:
5-Lead SOT-23
5EL7
XXNN
5-Lead SOT-23 Package Marking
Device
Comm. Indust.
Marking Marking
Device
Comm.
Marking
Indust. E-Temp
Comm. Indust. E-Temp
Device
Marking Marking
Marking Marking Marking
24AA00
A0NN
B0NN
24LC00
L0NN
M0NN
N0NN
24AA01
A1NN
B1NN
24LC01B
L1NN
M1NN
N1NN
24AA02
A2NN
B2NN
24LC02B
L2NN
M2NN
N2NN
24AA04
A3NN
B3NN
24LC04B
L3NN
M3NN
N3NN
24AA08
A4NN
B4NN
24LC08B
L4NN
M4NN
N4NN
24AA16
A5NN
B5NN
24LC16B
L5NN
M5NN
N5NN
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
24C00
C0NN
D0NN
E0NN
Part number or part number code
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn) plated devices
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
DS21930C-page 26
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
8-Lead MSOP (150 mil)
Example:
4L8BI
2281L7
XXXXXXT
YWWNNN
8-Lead MSOP Package Marking
Device
Line 1
Marking
Device
Line 1
Marking
24AA01
4A01T
24LC01B
4L1BT
24AA014
4A14T
24LC014
4L14T
24AA02
4A02T
24LC02B
4L2BT
24AA024
4A24T
24LC024
4L24T
24AA025
4A25T
24LC025
4L25T
24AA04
4A04T
24LC04B
4L4BT
24AA08
4A08T
24LC08B
4L8BT
24AA16
4A16T
24LC16B
4L16T
24AA32A
4A32AT
24LC32A
4L32AT
Device
Line 1
Marking
24C01C
4C1CT
24C02C
4C2CT
Line 1
Marking
Device
24AA64
4A64T
24LC64
4L64T
24FC64
4F64T
24AA128
4A128T
24LC128
4L128T
24FC128
4F128T
24AA256
4A256T
24LC256
4L256T
24FC256
4F256T
Note:
T = Temperature range: I = Industrial, E = Extended
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
Part number or part number code
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn) plated devices
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
DS21930C-page 27
24AAXX/24LCXX/24FCXX
Example:
8-Lead TSSOP
4L08
I228
1L7
XXXX
TYWW
NNN
8-Lead TSSOP Package Marking
Device
Line 1
Marking
24AA00
4A00
24AA01
24AA014
Device
Line 1
Marking
Device
Line 1
Marking
4C00
24C01C
4C1C
24C02C
4C2C
Line 1
Marking
24LC00
4L00
4A01
24LC01B
4L1B
4A14
24LC014
4L14
24AA02
4A02
24LC02B
4L02
24AA024
4A24
24LC024
4L24
24AA025
4A25
24LC025
4L25
24AA04
4A04
24LC04B
4L04
24AA08
4A08
24LC08B
4L08
24AA16
4A16
24LC16B
4L16
24AA32A
4AA
24LC32A
4LA
24AA64
4AB
24LC64
4LB
24FC64
4FB
24AA128
4AC
24LC128
4LC
24FC128
4FC
24AA256
4AD
24LC256
4LD
24FC256
4FD
Note:
24C00
Device
T = Temperature range: I = Industrial, E = Extended
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
Part number or part number code
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn) plated devices
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
DS21930C-page 28
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
3
2
D
E
A2
A
L
A1
c
e
eB
b1
b
Units
Dimension Limits
Number of Pins
INCHES
MIN
N
NOM
MAX
8
Pitch
e
Top to Seating Plane
A
–
–
.210
Molded Package Thickness
A2
.115
.130
.195
Base to Seating Plane
A1
.015
–
–
Shoulder to Shoulder Width
E
.290
.310
.325
Molded Package Width
E1
.240
.250
.280
Overall Length
D
.348
.365
.400
Tip to Seating Plane
L
.115
.130
.150
Lead Thickness
c
.008
.010
.015
b1
.040
.060
.070
b
.014
.018
.022
eB
–
–
Upper Lead Width
Lower Lead Width
Overall Row Spacing §
.100 BSC
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-018B
© 2007 Microchip Technology Inc.
DS21930C-page 29
24AAXX/24LCXX/24FCXX
8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
e
N
E
E1
NOTE 1
1
2
3
α
h
b
h
A2
A
c
φ
L
A1
L1
Units
Dimension Limits
Number of Pins
β
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
1.27 BSC
–
Molded Package Thickness
A2
1.25
–
–
Standoff §
A1
0.10
–
0.25
Overall Width
E
Molded Package Width
E1
3.90 BSC
Overall Length
D
4.90 BSC
1.75
6.00 BSC
Chamfer (optional)
h
0.25
–
0.50
Foot Length
L
0.40
–
1.27
Footprint
L1
1.04 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.17
–
0.25
Lead Width
b
0.31
–
0.51
Mold Draft Angle Top
α
5°
–
15°
Mold Draft Angle Bottom
β
5°
–
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-057B
DS21930C-page 30
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
8-Lead Plastic Dual Flat, No Lead Package (MC) – 2x3x0.9 mm Body [DFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
e
b
N
N
L
K
E2
E
EXPOSED PAD
NOTE 1
2
1
2
NOTE 1
1
D2
BOTTOM VIEW
TOP VIEW
A
A3
A1
NOTE 2
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
0.80
0.90
1.00
Standoff
A1
0.00
0.02
0.05
Contact Thickness
A3
0.20 REF
Overall Length
D
2.00 BSC
Overall Width
E
Exposed Pad Length
D2
1.30
–
Exposed Pad Width
E2
1.50
–
1.90
b
0.18
0.25
0.30
Contact Length
L
0.30
0.40
0.50
Contact-to-Exposed Pad
K
0.20
–
–
Contact Width
0.50 BSC
3.00 BSC
1.75
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-123B
© 2007 Microchip Technology Inc.
DS21930C-page 31
24AAXX/24LCXX/24FCXX
8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
e
D
L
b
N
N
K
E2
E
EXPOSED PAD
NOTE 1
1
2
2
NOTE 1
1
D2
BOTTOM VIEW
TOP VIEW
A
A3
A1
NOTE 2
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
0.80
1.27 BSC
0.85
1.00
Standoff
A1
0.00
0.01
0.05
Contact Thickness
A3
0.20 REF
Overall Length
D
5.00 BSC
Overall Width
E
Exposed Pad Length
D2
3.90
4.00
4.10
Exposed Pad Width
E2
2.20
2.30
2.40
6.00 BSC
Contact Width
b
0.35
0.40
0.48
Contact Length
L
0.50
0.60
0.75
Contact-to-Exposed Pad
K
0.20
–
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
–
Microchip Technology Drawing C04-122B
DS21930C-page 32
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
5-Lead Plastic Small Outline Transistor (OT) [SOT-23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
b
N
E
E1
3
2
1
e
e1
D
A2
A
c
φ
A1
L
L1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
NOM
MAX
N
5
Lead Pitch
e
0.95 BSC
Outside Lead Pitch
e1
Overall Height
A
0.90
–
Molded Package Thickness
A2
0.89
–
1.30
Standoff
A1
0.00
–
0.15
Overall Width
E
2.20
–
3.20
Molded Package Width
E1
1.30
–
1.80
Overall Length
D
2.70
–
3.10
Foot Length
L
0.10
–
0.60
Footprint
L1
0.35
–
0.80
Foot Angle
φ
0°
–
30°
Lead Thickness
c
0.08
–
0.26
1.90 BSC
1.45
Lead Width
b
0.20
–
0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-091B
© 2007 Microchip Technology Inc.
DS21930C-page 33
24AAXX/24LCXX/24FCXX
8-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
e
b
A2
A
c
φ
L
L1
A1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
0.65 BSC
–
Molded Package Thickness
A2
0.75
0.85
0.95
Standoff
A1
0.00
–
0.15
Overall Width
E
Molded Package Width
E1
3.00 BSC
Overall Length
D
3.00 BSC
Foot Length
L
Footprint
L1
1.10
4.90 BSC
0.40
0.60
0.80
0.95 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.08
–
0.23
Lead Width
b
0.22
–
0.40
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-111B
DS21930C-page 34
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
b
e
c
A
φ
A2
A1
L
L1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
0.65 BSC
–
Molded Package Thickness
A2
0.80
1.00
1.05
Standoff
A1
0.05
–
0.15
1.20
Overall Width
E
Molded Package Width
E1
4.30
6.40 BSC
4.40
Molded Package Length
D
2.90
3.00
3.10
Foot Length
L
0.45
0.60
0.75
Footprint
L1
4.50
1.00 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.09
–
0.20
Lead Width
b
0.19
–
0.30
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-086B
© 2007 Microchip Technology Inc.
DS21930C-page 35
24AAXX/24LCXX/24FCXX
NOTES:
DS21930C-page 36
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2007 Microchip Technology Inc.
DS21930C-page 37
24AAXX/24LCXX/24FCXX
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
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RE:
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Total Pages Sent ________
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Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: 24AAXX/24LCXX/24FCXX
Literature Number: DS21930C
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21930C-page 38
© 2007 Microchip Technology Inc.
24AAXX/24LCXX/24FCXX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device Part
Number
(Table 1-1)
Device:
X
X
PART NO.
/XX
Packaging Temperature Package
Medium
Range
Examples:
a)
24AA014-I/SN: 1 Kbit, Industrial
Temperature, 1.7V, SOIC package
b)
24AA02T-I/OT: 2 Kbit, Industrial
Temperature, 1.7V, SOT-23 package,
Tape and Reel
c)
24LC16B-I/P: 16 Kbit, Industrial Temperature, 2.5V, PDIP package
d)
24LC32A-E/MS: 32 Kbit, Extended
Temperature, 2.5V, MSOP package
e)
24LC64T-I/MC:
64
Kbit,
Industrial
Temperature, 2.5V 2x3 mm DFN package,
Tape and Reel
f)
24FC512T-I/SM: 512 Kbit, Industrial
Temperature, 1 MHz, SOIC package,
Tape and Reel
See Table 1-1
Temperature I
Range:
E
=
=
-40°C to +85°C
-40°C to +125°C
Packaging
Medium:
T
= Tape and Reel
Blank = Tube
Package:
P
SN
SM
ST
MS
OT
MC
MF
=
=
=
=
=
=
=
=
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (3.90 mm body), 8-lead
Plastic SOIC (208 mil body), 8-lead
Plastic TSSOP (4.4 mm), 8-lead
MSOP (3.0 mm), 8-lead
SOT-23, 5-lead (Tape and Reel only)
2x3 mm DFN, 8-lead (Tape and Reel only)
5x6 mm DFN, 8-lead
© 2007 Microchip Technology Inc.
DS21930C-page 39
24AAXX/24LCXX/24FCXX
NOTES:
DS21930C-page 40
© 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2007 Microchip Technology Inc.
DS21930C-page 41
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
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Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
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Suites 3707-14, 37th Floor
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Tel: 86-757-2839-5507
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Taiwan - Taipei
Tel: 886-2-2500-6610
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Tel: 86-27-5980-5300
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Tel: 66-2-694-1351
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Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
06/25/07
DS21930C-page 42
© 2007 Microchip Technology Inc.