TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 HIGH-EFFICIANCY MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLER WITH VOLTAGE FEED-FORWARD FEATURES • • • • • • • • • • DESCRIPTION Operation Over 4.5-V to 28-V Input Range Programmable Fixed-Frequency up to 1-MHz Voltage-Mode Controller Predictive Gate Drive™ With Anti-Cross Conduction Circuitry <1% Internal 700-mV Reference Internal Gate Drive Outputs for High-Side and Synchronous N-Channel MOSFETs 16-Pin PowerPAD™ Package Thermal Shutdown Protection TPS40070: Source Only TPS40071: Source/Sink Programmable High-Side Sense Short Circuit Protection The TPS4007x is a mid voltage, wide input (4.5 V to 28 V), synchronous, step-down converter. The TPS4007x offers design flexibility with a variety of user programmable functions, including; soft-start, UVLO, operating frequency, voltage feed-forward and high-side FET sensed short circuit protection. The TPS4007x incorporates MOSFET gate drivers for external N-channel high-side and synchronous rectifier (SR) MOSFETs. Gate drive logic incorporates predictive anti-cross conduction circuitry to prevent simultaneous high-side and synchronous rectifier conduction, while minimizing to eliminating current flow in the body diode of the SR FET. The TPS40071 allows the supply output to sink current at all times. The TPS40070 implements a source-only power supply. APPLICATIONS • • • • Power Modules Networking/Telecom Industrial Servers SIMPLIFIED APPLICATION DIAGRAM TPS40070PWP VDD 1 2 VOUT Powergood KFF RT ILIM 16 VDD VDD 15 3 LVBP BOOST 14 4 PGD HDRV 13 5 SGND SW 12 6 SS DBP 11 7 FB LDRV 10 8 COMP PGND 9 VOUT VDG−03170 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Predictive Gate Drive, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2004, Texas Instruments Incorporated TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 DESCRIPTION (CONTINUED) The TPS4007x uses voltage feed-forward control techniques to provide good line regulation over a wide-input voltage range, and fast response to input line transients with near constant gain with input variation to ease loop compensation. The externally programmable short circuit protection provides fault current limiting, as well as hiccup mode operation for thermal protection in the presence of a shorted output.The TPS4007x is packaged in a 16-pin PowerPAD package for better thermal performance at higher voltages and frequencies. See SLMA002 for information on board layout for the PowerPAD package. The pcb pad that the PowerPAD solders to should be connected to GND. Due to the die attach method, the PowerPAD itself cannot be used as the device ground connection. The two device grounds must be connected as well. ORDERING INFORMATION TA 40°C to 85°C (1) (2) APPLICATION PACKAGE PART NUMBER SOURCE ONLY (1) Plastic HTSSOP (PWP)( (2)) TPS40070PWP SOURCE/SINK (1) (PWP)( (2)) TPS40071PWP Plastic HTSSOP See Application Information section and Table 1. The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40070PWPR). See the application section of the data sheet for PowerPAD drawing and layout information. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TPS40070 TPS40071 VDD, ILIM VDD Input voltage range VOUT Output voltage range 30 COMP, FB, KFF, PGD, LVBP –0.3 to 6 SW –0.3 to 40 SW, transient < 50 ns –2.5 COMP, KFF, RT, SS –0.3 to 6 VBOOST Output current source IOUT Output current sink Output current DBP 10.5 6 LDRV, HDRV 1.5 LDRV, HDRV 2.0 KFF 10 RT 1 LVBP A mA 1.5 TJ Operating junction temperature range –40 to 125 Tstg Storage temperature –55 to 150 Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) V 50 LVBP IOUT UNIT °C 260 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIIONS MIN NOM MAX UNIT VDD Input voltage 4.5 28 V TA Operating free-air temperature -40 85 °C 2 TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 µA, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VDD Input voltage range, VIN 4.5 28 V 2.5 3.5 mA 3.9 4.2 4.5 V 450 500 550 kHz 2.23 2.40 2.58 V 250 ns OPERATING CURRENT IDD Quiescent current Output drivers not switching LVBP VLVBP Output voltage OSCILLATOR/RAMP GENERATOR fOSC TA = TJ = 25°C (1) Accuracy voltage (2) VRAMP PWM ramp VRT RT voltage tON Minimum output pulse time (2) Maximum duty cycle VKFF Feed-forward voltage IKFF Feed-forward current operating range (2) VPEAK-VVAL 2.0 CHDRV = 0 nF VFB = 0 V, 100 kHz ≤ fSW ≤ 500 kHz 84% VFB = 0 V, fSW = 1 MHz 76% 0.35 V 93% 93% 0.40 20 0.45 V 1100 µA 17 µA SOFT START ISS Charge current tDSCH Discharge time CSS = 3.9 nF 7 tSS Soft-start time CSS = 3.9 nF, VSS rising from 0.7 V to 1.6 V Command zero output voltage (1) 12 25 210 75 290 500 300 µs mV DBP VDBP Output voltage VDD > 10 V 7 8 4.0 4.3 TA = TJ = 25°C 0.698 0.700 0.704 0°C ≤ TA≤ 85°C 0.690 0.700 0.707 40°C ≤ TA≤ 85°C 0.690 0.700 0.715 VDD = 4.5 V, IOUT = 25 mA 9 V ERROR AMPLIFIER VFB Feedback regulation voltage total variation VSS Soft-start offset from VSS Offset from VSS to error amplifier bandwidth (1) 1 GBW Gain AVOL Open loop gain 50 ISRC Output source current 2.5 4.5 ISINK Output sink current 2.5 6 IBIAS Input bias current (1) (2) 5 VFB = 0.7 V V –250 10 MHz dB mA 0 nA For zero output voltage only. Does not assure lack of activity on HDRV or LDRV. Ensured by design. Not production tested. 3 TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 80 105 125 µA –75 –50 –30 mV 135 225 ns SHORT CIRCUIT CURRENT PROTECTION IILIM Current sink into current limit VILIM(ofst Current limit offset voltage ) tHSC VILIM = 11.5 V, (VSW - VILIM) VDD = 12 V Minimum HDRV pulse width Propagation delay to output During short circuit (3) 50 time (3) tBLANK Blanking tOFF Off time during a fault (SS cycle times) VSW Switching level to end precondition (3) (VDD - VSW) 50 ns 7 cycles 2 V time (3) tPC Precondition VILIM Current limit precondition voltage threshold (3) ns 100 6.8 ns V OUTPUT DRIVERS tHFALL High-side driver fall time (3) time (3) tHRISE High-side driver rise tHFALL High-side driver fall time (3) tHRISE High-side driver rise time (3) tLFALL Low-side driver fall time (3) tLRISE Low-side driver rise time (3) tLFALL Low-side driver fall time (3) time (3) tLRISE Low-side driver rise VOH High-level output voltage, HDRV VOL Low-level output voltage, HDRV VOH High-level output voltage, LDRV VOL Low-level output voltage, LDRV 36 CHDRV = 2200 pF, (HDRV - SW) ns 48 72 CHDRV = 2200 pF, (HDRV - SW) VDD = 4.5 V, 0.2 V ≤ VSS≤ 4 V ns 96 24 CLDRV = 2200 pF ns 48 48 CLDRV = 2200 pF, VDD= 4.5 V, 0.2 V ≤ VSS≤ 4 V ns 96 IHDRV = -0.01 A, (VBOOST- VHDRV) 0.7 1.0 IHDRV = -0.1 A, (VBOOST - VHDRV) 0.95 1.30 (VHDRV - VSW), IHDRV = 0.01A 0.06 0.10 (VHDRV - VSW), IHDRV = 0.1 A 0.65 1.0 (VDBP - VLDRV), ILDRV= -0.01A 0.65 1.00 (VDBP - VLDRV), ILDRV = -0.1 A 0.875 1.200 ILDRV = 0.01 A 0.03 0.05 ILDRV = 0.1 A 0.3 0.5 –5 0 5 15.2 17.0 V V V V ZERO CURRENT DETECTION IZERO Zero current threshold, TPS40070 mV BOOST REGULATOR VBOOST Output voltage VDD = 12 V V UVLO VUVLO Programmable UVLO threshold voltage RKFF = 90.9 kΩ, turn-on, VDD rising 6.2 7.2 8.2 Programmable UVLO hysteresis RKFF = 90.9 kΩ 1.10 1.55 2.00 Fixed UVLO threshold voltage Turn-on, VDD rising 4.15 4.30 4.45 275 365 Fixed UVLO hysteresis V mV POWER GOOD VPG Powergood voltage IPG = 1 mA 370 VOH High-level output voltage, FB 770 VOL Low-level output voltage, FB 630 500 mV THERMAL SHUTDOWN Shutdown temperature threshold (3) Hysteresis (3) (3) 4 Ensured by design. Not production tested. 165 15 °C TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 PWP PACKAGE(1)(2) (TOP VIEW) 1 2 3 4 5 6 7 8 KFF RT LVBP PGD SGND SS FB COMP THERMAL PAD 16 15 14 13 12 11 10 9 ILIM VDD BOOST HDRV SW DBP LDRV PGND (1) For more information on the PWP package, refer to TI Technical Brief (SLMA002). (2) PowerPAD™ heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins. Table 1. Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. BOOST 14 I Gate drive voltage for the high-side N-channel MOSFET. The BOOST voltage is 8 V greater than the input voltage. A capacitor should be connected from this pin to the SW pin. COMP 8 O Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the FB pin to compensate the overall loop. The comp pin is internally clamped to 3.4 V. DBP 11 O 8-V reference used for the gate drive of the N-channel synchronous rectifier. This pin should be bypassed to ground with a 1.0-µF ceramic capacitor. FB 7 I Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference voltage, 0.7 V. HDRV 13 O Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW (MOSFET off). ILIM 16 I Short circuit protection programming pin. This pin is used to set the overcurrent threshold. An internal current sink from this pin to ground sets a voltage drop across an external resistor connected from this pin to VDD. The voltage on this pin is compared to the voltage drop (VVDD -VSW) across the high side N-channel MOSFET during conduction. Just prior to the beginning of a switching cycle this pin is pulled to approximately VDD/2 and released when SW is within 2 V of VDD or after a timeout (the precondition time) - whichever occurs first. Placing a capacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the switch on time, effectively programming the ILIM blanking time. See applications information. KFF 1 I A resistor is connected from this pin to VIN programs the amount of feed-forward voltage. The current fed into this pin is internally divided by 25 and used to control the slope of the PWM ramp and program undervoltage lockout. Nominal voltage at this pin is maintained at 400 mV. LDRV 10 O Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to ground (MOSFET off). LVBP 3 O 4.2-V reference used for internal device logic only. This pin should be bypassed by a 0.1-µF ceramic capacitor. External loads less than 1 mA and electrically quiet may be applied. PGD 4 O This is an open drain output that pulls to ground when soft start is active, or when the FB pin is outside a ±10% band around VREF. PGND 9 RT 2 SGND 5 Signal ground reference for the device. SS 6 I Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The capacitor is charged with an internal current source of 10 µA. The resulting voltage ramp on the SS pin is used as a second non-inverting input to the error amplifier. The voltage at this error amplifier input is approximately 1 V less that that on the SS pin. Output voltage regulation is controlled by the SS voltage ramp until the voltage on the SS pin reaches the internal reference voltage of 1 V plus the internal reference voltage of 0.7 V. If SS is below the 1-V offset voltage to the error amplifier. The resulting output voltage is zero. Also provides timing for fault recovery attempts. SW 12 I This pin is connected to the switched node of the converter and used for overcurrent sensing and for zero current sensing as well. VDD 15 I Supply voltage for the device. Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of the lower MOSFET(s). I A resistor is connected from this pin to ground to set the internal oscillator and switching frequency. 5 TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 FUNCTIONAL BLOCK DIAGRAM VDD 15 11 DBP VDD Reference Regulator UVLO Controller 16 ILIM UVLO LVBP 3 RT 2 Oscillator Ramp Generator SW CLK Pulse Control 9 SS Active KFF 1 HDRV LDRV PGD 4 Power Good Logic SGND 5 770 mV FB 630 mV SS Active ILIM CLK LVBP SS 6 COMP 8 CLK CLK 700 mV + + Overcurrent Comparator and Control OC OC DBP OC FB 7 IZERO 12 SW RAMP Soft Start and Fault Control IZERO Comparator and Control (TPS40070 only) PGND PWM Predictive Gate Drive Control Logic 14 BOOST 13 HDRV 10 LDRV SW UVLO PGND FAULT IZERO VDG−03171 6 TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 APPLICATION INFORMATION The TPS40070 family of parts allows the user to construct synchronous voltage-mode buck converters with inputs ranging from 4.5 V to 28 V and outputs as low as 700 mV. Predictive gate drive circuitry optimizes switching delays for increased efficiency and improved converter output power capability. Voltage feed-forward is employed to ease loop compensation and provide better line transient response. A converter based on the TPS40070 operates as a single quadrant (source only) converter at all times. When the rectifier FET is on and the controller senses that current is near zero in the inductor, the rectifier FET is turned off, preventing the buildup of negative or reverse current in the inductor. This feature prevents the converter from pulling energy from its output and forcing that energy onto its input. Converters based on the TPS40071 operates as a two quadrant converter all the time (source and sink current). This is the controller of choice for most applications. MINIMUM PULSE WIDTH The TPS4007x devices have limitations on the minimum pulse width that can be used to design a converter. Reliable operation is guaranteed for nominal pulse widths of 250 ns and above. This places some restrictions on the conversion ratio that can be achieved at a given switching frequency. Figure 1 shows minimum output voltage for a given input voltage and frequency. SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR) The TPS4007x has independent clock oscillator and PWM ramp generator circuits. The clock oscillator serves as the master clock to the ramp generator circuit. Connecting a single resistor from RT to ground sets the switching frequency of the clock oscillator. The clock frequency is related to RT by: RT + ǒ f SW(kHz) 10 *6 Ǔ * 23 kW 600 VIN = 24 V VIN = 15 V 500 VIN = 18 V 3.5 VIN = 12 V VIN = 10 V 2.0 1.5 VIN = 8 V 1.0 0.5 100 VIN = 5 V 200 300 400 500 600 700 800 900 1000 RT - Timing Resistance - kΩ 4.0 2.5 SWITCHING FREQUENCY vs TIMING RESISTANCE VIN = 28 V 4.5 3.0 (1) MINIMUM OUTPUT VOLTAGE vs FREQUENCY 5.0 VOUT - Output Voltage - V 1 17.82 400 300 200 100 0 0 200 400 600 800 fOSC - Oscillator Frequency - kHz fSW - Switching Frequency - kHz Figure 1. Figure 2. 1000 7 TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 APPLICATION INFORMATION (continued) PROGRAMMING THE RAMP GENERATOR CIRCUIT AND UVLO The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations since the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 8). The PWM ramp must reach approximately 1 V in amplitude during a clock cycle, or the PWM is not allowed to start. The PWM ramp time is programmed via a single resistor (RKFF) connected from KFF VDD. RKFF , VSTART and RT are related by (approximately): R KFF V UVLO(on) + 7.6 ) 0.4 RT (2) where • • VUVLO(on) is in volts resistors use the same units This yields typical numbers for the programmed startup voltage. The minimum and maximum values may vary up ±15% from this number. Figure 4 through Figure 6 show the typical relationship of VUVLO(on), VUVLO(off) and RKFF at three common frequencies. FREQUENCY vs INPUT VOLTAGE 525 20 VUVLO - Programmable UVLO Threshold - V 520 fOSC - Frequency - kHz 515 510 505 500 495 490 485 480 5 9 11 13 15 17 19 21 VDD - Input Voltage - V Figure 3. 8 23 25 27 29 UNDERVOLTAGE LOCKOUT THRESHOLDS vs FEED FORWARD IMPEDANCE FSW = 300 kHz 18 UVLO VON 16 14 12 10 8 6 4 2 UVLO VOFF 90 120 150 180 210 240 270 300 330 360 390 RKFF - Feed-Forward Impedance - kΩ Figure 4. TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 APPLICATION INFORMATION (continued) UNDERVOLTAGE LOCKOUT THRESHOLDS vs FEED FORWARD IMPEDANCE UVLO VON 18 16 14 12 10 8 6 UVLO VOFF 4 2 0 30 20 FSW = 500 kHz VUVLO - Programmable UVLO Threshold - V VUVLO - Programmable UVLO Threshold - V 20 90 120 150 180 210 RKFF - Feed-Forward Impedance - kΩ Figure 5. 240 270 FSW = 750 kHz 18 UVLO VON 16 14 12 10 8 6 UVLO VOFF 4 2 60 UNDERVOLTAGE LOCKOUT THRESHOLDS vs FEED FORWARD IMPEDANCE 30 60 90 120 150 RKFF - Feed-Forward Impedance - kΩ 180 Figure 6. The programmable UVLO circuit incorporates 20% hysteresis from the start voltage to the shutdown voltage. For example, if the startup voltage is programmed to be 10 V, the controller starts when VDD reaches 10 V and shuts down when VDD falls below 8 V. The maximum duty cycle begins to decrease as the input voltage rises to twice the startup voltage. Below this point, the maximum duty cycle is as specified in the electrical table. Note that with this scheme, the theoretical maximum output voltage that the converter can produce is approximately two times the programmed startup voltage. For design, set the programmed startup voltage equal to or greater than the desired output voltage divided by maximum duty cycle (85% for frequencies 500 kHz and below). For example, a 5-V output converter should not have a programmed startup voltage below 5.9 V. Figure 7 shows the theoretical maximum duty cycle (typical) for various programmed startup voltages At startup, LDRV may pulse high when VDD is in the range of 1 V to 1.25 V and VDD is rising extremely slowly. To minimize these effects, the ramp rate of VDD at startup should be greater than 1 V/ms. 9 TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 APPLICATION INFORMATION (continued) TYPICAL MAXIMUM DUTY CYCLE vs INPUT VOLTAGE 100 UVLO(on) = 15 V 90 Duty Cycle - % 80 UVLO(on) = 8 V UVLO(on) = 12 V 70 60 UVLO(on) = 4.5 V 50 40 30 20 4 8 12 16 20 24 28 VIN - Input Voltage - V Figure 7. VIN VIN SW SW RAMP VPEAK COMP COMP RAMP VVALLEY tON1 t d + ON T T1 tON2 T2 tON1 > tON2 and d1 > d2 Figure 8. Voltage Feed-Forward and PWM Duty Cycle Waveforms 10 VDG−03172 TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 PROGRAMMING SOFT START TPS4007x uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start is programmed by connecting an external capacitor (CSS) from the SS pin to GND. This capacitor is charged by a fixed current, generating a ramp signal. The voltage on SS is level shifted down approximately 1 V and fed into a separate non-inverting input to the error amplifier. The loop is closed on the lower of the level shifted SS voltage or the 700-mV internal reference voltage. Once the level shifted SS voltage rises above the internal reference voltage, output voltage regulation is based on the internal reference. To ensure a controlled ramp-up of the output voltage the soft-start time should be greater than the L-COUT time constant or: t START w 2p ǸL COUT (seconds) (3) Please note: There is a direct correlation between tSTART and the input current required during start-up. The lower tSTART is, the higher the input current required during start-up since the output capacitance must be charged faster. For a desired soft-start time, the soft-start capacitance, CSS, can be found from: *6 C SS + 12 10 t START (Farads) 0.7 V (4) PROGRAMMING SHORT CIRCUIT PROTECTION The TPS4007x uses a two-tier approach for short circuit protection. The first tier is a pulse-by-pulse protection scheme. Short circuit protection is implemented on the high-side MOSFET by sensing the voltage drop across the MOSFET when its gate is driven high. The MOSFET voltage is compared to the voltage dropped across a resistor (RILIM) connected from VDD to the ILIM pin when driven by a constant current sink. If the voltage drop across the MOSFET exceeds the voltage drop across the ILIM resistor the switching pulse is immediately terminated. The MOSFET remains off until the next switching cycle is initiated. This is illustrated in Figure 9. VILIM Threshold (A) VSW IILIM VIN− 2V T2 T1 (B) VILIM Threshold VSW IILIM VIN− 2V T1 T3 VDG−03173 Figure 9. Voltage Feed-Forward and PWM Duty Cycle Waveforms In addition, just prior to the high-side MOSFET turning on, the ILIM pin is pulled down to approximately half of VDD. The ILIM pin is allowed to return to its nominal value after one of two events occur. If the SW node rises to within approximately 2 V of VDD, the device allows ILIM to go back to its nominal value. This is illustrated in Figure 9(A). T1 is the delay time from the internal PWM signal being asserted and the rise of SW. This includes a driver delay of 50 ns typical. T2 is the reaction time of the sensing circuit that allows ILIM to start to return to its nominal value, typically 20ns. The second event that can cause ILIM to return to its nominal value is for an internal timeout to expire. This is illustrated in Figure 9(B) as T3. Here SW never rises to VDD-2 V, for whatever reason, and the internal timer times out, releasing the ILIM pin. 11 TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 Prior to ILIM starting back to its nominal value, overcurrent sensing is not enabled. In normal operation, this ensures that the SW node is at a higher voltage than ILIM when overcurrent sensing starts, avoiding false trips while allowing for a quicker blanking delay than would ordinarily be possible. Placing a capacitor across RILIM sets an exponential approach to the normal voltage at the ILIM pin. This exponential decay of the overcurrent threshold can be used to compensate for ringing on the SW node after its rising edge and to help compensate for slower turn-on FETs. Choosing the proper capacitance requires care. If the capacitance is too large, the voltage at ILIM does not approach the desired overcurrent level quickly enough, resulting in an apparent shift in overcurrent threshold as pulse width changes. Also, the comparator that uses ILIM and SW to determine if an overcurrent condition exists has a clamp on its SW input. This clamp makes the SW node never appear to fall more than 1.4 V (approximately, could be as much as 2 V at -40°C) below VDD. When ILIM is more than 1.4 V below VDD, the overcurrent circuit is effectively disabled. As a general rule, it is best to make the time constant of the R-C at the ILIM pin 0.2 times or less of the nominal pulse width of the converter as shown in see Equation 9. The second tier protection incorporates a fault counter. The fault counter is incremented on each cycle with an overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a fault condition is declared by the controller. When this happens, the outputs are placed in a state defined in Table 2. Seven soft-start cycles are initiated (without activity on the HDRV and LDRV outputs) and the PWM is disabled during this period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero the PWM is re-enabled and the controller attempts to restart. If the fault has been removed the output starts up normally. If the output is still present the counter counts seven overcurrent pulses and re-enter the second tier fault mode. Refer to Figure 10 for typical fault protection waveforms. The minimum short circuit limit setpoint (ILIM) depends on tSTART, COUT, VOUT, and the load current at turn-on (ILOAD). C VOUT I ILIM u OUT ) I LOAD (A) t START (5) The short circuit limit programming resistor (RILIM) is calculated from: I SCP RDS(onMAX) ) VILIM (offset) R ILIM + W I ILIM (6) where • • • IILIM is the current into the ILIM pin (110 µA typical) VILIM(offset) is the offset voltage of the ILIM comparator (-50 mV typical) ISCP is the short-circuit protection current To find the range of the overcurrent values use the following equations. I ILIM(max) RILIM ) 75 mV I SCP(max) + W R DS(onMIN) I SCP(min) + I ILIM(min) RILIM ) 30 mV R DS(onMAX) (7) W The ILIM capacitor maximum value can be found from: V OUT 0.2 C ILIM(max) + (Farads) VIN RILIM f SW (8) (9) Note that this is a recommended maximum value. If a smaller value can be used, it should be. For most applications, consider using half the maximum value above. 12 TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 HDRV Clock tBLANKING VILIM VVIN−VSW SS 7 Current Limit Trips (HDRV Cycle Terminated by Current Limit Trip) 7 Soft-Start Cycles VDG−03174 Figure 10. Typical Fault Protection Waveforms LOOP COMPENSATION Voltage mode buck type converters are typically compensated using Type III networks. Since the TPS4007x uses voltage feedforward control, the gain of the voltage feedforward circuit must be included in the PWM gain. The gain of the voltage feedforward circuit combined with the PWM circuit and power stage for the TPS4007x is: K PWM ^ VUVLO (on) (10) The remainder of the loop compensation is performed as in a normal buck converter. Note that the voltage feedforward circuitry removes the input voltage term from the expression for PWM gain. PWM gain is strictly a function of the programmed startup voltage. BOOST AND LVBP BYPASS CAPACITANCE The BOOST capacitance provides a local, low-impedance flying source for the high-side driver. The BOOST capacitor should be a good quality, high-frequency capacitor. A capacitor with a minimum value of 100-nF is suggested. The LVBP has to provide energy for both the synchronous MOSFET and the high-side MOSFET (via the BOOST capacitor). The suggested value for this capacitor is 1-µF ceramic, minimum. INTERNAL REGULATORS The internal regulators are linear regulators that provide controlled voltages for the drivers and the internal circuitry to operate from. The DBP pin is connected to a nominal 8-V regulator that provides power for the driver circuits to operate from. This regulator has two modes of operation. At VDD voltages below 8.5 V ,the regulator is in a low dropout mode of operation and tries to provide as little impedance as possible from VDD to DBP. Above 10 V at VDD, the regulator regulates DBP to 8 V. Between these two voltages, the regulator remains in the state it was in when VDD entered this region (see Figure 11). Small amounts of current can be drawn from this pin for other circuit functions, as long as power dissipation in the controller device remains at acceptable levels and junction temperature does not exceed 125°C. 13 TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 The LVBP pin is connected to another internal regulator that provides 4.2-V (nom) for the operation of low-voltage circuitry in the controller. This pin can be used for other circuit purposes, but extreme care must be taken to ensure that no extra noise is coupled onto this pin, since controller performance suffers. Current draw is not to exceed 1 mA. See Figure 12 for typical output voltage at this pin. INPUT VOLTAGE vs DBP VOLTAGE INPUT VOLTAGE vs LOW VOLTAGE BYPASS VOLTAGE 4.50 10 VDBP - Low Voltage Bypass Voltage - V 4.45 VDBP - Driver Bypass Voltage - V 9 8 7 6 5 4 4.40 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 0 5 10 15 VDD - Input Voltage - V 20 25 Figure 11. 5 10 15 20 25 30 VDD - Input Voltage - V Figure 12. TPS4007x POWER DISSIPATION The power dissipation in the TPS4007x is largely dependent on the MOSFET driver currents and the input voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power (neglecting external gate resistance) can be calculated from: P D + Q g VDR f SW (Wattsńdriver) (11) where VDR is the driver output voltage • And the total power dissipation in the TPS4007x, assuming the same MOSFET is selected for both the high-side and synchronous rectifier is described in Equation 12. 2 PD PT + ) IQ V IN (Watts) V DR ǒ or P T + ǒ2 Ǔ Qg f SW ) I QǓ (12) V IN (Watts) (13) where: • IQ is the quiescent operating current (neglecting drivers) The maximum power capability of the TPS4007x PowerPAD package is dependent on the layout as well as air flow. The thermal impedance from junction to air assuming 2-oz. copper trace and thermal pad with solder and no air flow is see teh application report titledPowerPAD Thermally Enhanced Package (SLMA002) for detailed information on PowerPAD package mounting and usage. q JA + 36.51 CńW (14) O The maximum allowable package power dissipation is related to ambient temperature by Equation 15. 14 TPS40070 TPS40071 www.ti.com PT + SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 TJ * TA (Watts) q JA (15) Substituting Equation 15 into Equation 14 and solving for fSW yields the maximum operating frequency for the TPS4007x. The result is described in Equation 16. ǒƪ ǒT J*T AǓ ƫ ǒq JA V DDǓ f SW + ǒ2 * IQ Q gǓ Ǔ (Hz) (16) BOOST DIODE The TPS4007x series has internal diodes to charge the boost capacitor connected from SW to BOOST. The drop across this diode is rather large at 1.4-V nominal at room temperature. If this drop is too large for a particular application, an external diode may be connected from DBP (anode) to BOOST (cathode). This provides significantly improved gate drive for the high side FET, especially at lower input voltages. LOW VOLTAGE OPERATION If the programmable UVLO is set to less than 6.5 V nominal, connect a 330-kΩ resistor across the soft-start capacitor. This eliminates a race condition inside the device that can lead to an output voltage overshoot on power down of the part. If operation is expected below -10°C ambient temperature and at less than 5-V input, it is recommended that a diode be connected from LVBP to DBP. (See Figure 15). GROUNDING AND BOARD LAYOUT The TPS4007x provides separate signal ground (SGND) and power ground (PGND) pins. Care should be given to proper separation of the circuit grounds. Each ground should consist of a plane to minimize its impedance if possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor (DBP), and the input capacitor should be connected to PGND plane. Sensitive nodes such as the FB resistor divider and RT should be connected to the SGND plane. The SGND plane should only make a single point connection to the PGND plane. It is suggested that the SGND pin be tied to the copper area for the PowerPAD underneath the chip. Tie the PGND to the PowerPAD copper area as well and make the connection to the power circuit ground from the PGND pin. Reference the output voltage divider to the SGND pin. Component placement should ensure that bypass capacitors (LVPB and DBP) are located as close as possible to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). Failure to follow careful layout practices results in sub-optimal operation. More detailed information can be found in the TPS40071EVM User's Guide (SLUU180). 15 TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 SYNCHRONOUS RECTIFIER CONTROL Depending on which device is used the synchronous rectifier is controlled in slightly different ways. Table 2 describes the differences. Table 2. Synchronous Rectifier MOSFET States SYNCHRONOUS RECTIFIER OPERATION DURING DEVICE SOFT-START NORMAL FAULT OVERVOLTAGE TPS40070 Turns OFF when IZERO detected or start of next cycle Turns Off when IZERO detected or start of next cycle OFF Turns OFF when IZERO detected or start of next cycle TPS40071 Turns OFF only at start of next cycle Turns OFF only at start of next cycle ON Turns OFF only at start of next cycle, if duty cycle is > 0 + VDD R6 165 kΩ 12 V − R9 2 kΩ TPS40070PWP TPS40071PWP R2 165 kΩ C2 0.1 µF 1 KFF ILIM 16 2 RT VDD 15 3 LVBP 4 PG C3 22 nF R5 10 kΩ C5 5.6 nF C12 22 µF C10 0.1 µF 5 SGND L1 COEV Q1 DXM1306−1R6 Si7840DP 1.6 µH + SW 12 6 SS DBP 11 7 VFB C14 22 µF C8 0.1 µF HDRV 13 LDRV 10 8 COMP C4 470 pF BOOST 14 C7 10 pF C9 1 µF Q2 Si7856DP + C13 4.7 nF PGND 9 PWP C15 47 µF + C16 C17 C18 470 µF 470 µF 0.1 µF VOUT 1.8 V 10 A − R7 8.66 kΩ R3 5.49 kΩ C6 4.7 nF R8 226 Ω VDG−03175 Figure 13. 300 kHz, 12 V to 1.8 V 16 TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 + VDD 12 V R6 165 kΩ − TPS40070PWP TPS40071PWP R2 165 kΩ C2 0.1 µF 1 KFF ILIM 16 2 RT VDD 15 3 LVPB BOOST 14 4 PG C3 22 nF 5 SGND C7 10 pF R9 2 kΩ C12 22 µF C10 0.1 µF D1 BAT54 HDRV 13 Q1 Si7840DP C5 5.6 nF C4 470 pF L1 COEV DXM1306−1R6 1.6 µH + SW 12 C9 1 µF 6 SS DBP 11 R5 10 kΩ C8 0.1 µF C14 22 µF 7 VFB LDRV 10 8 COMP Q2 Si7856DP C13 4.7 nF + + C15 C16 47 µF 470 µF PGND 9 PWP VOUT 1.8 V C17 C18 470 µF 0.1 µF 10 A − R7 8.66 kΩ R3 5.49 kΩ C6 4.7 nF R8 226 Ω VDG−03176 Figure 14. 300 kHz, 12 V to 1.8 V with Improved High-Side Gate Drive See Application Information section Boost Diodes. 17 TPS40070 TPS40071 www.ti.com SLUS582D – DECEMBER 2003 – REVISED NOVEMBER 2004 + VDD R6 47 kΩ 5V − TPS40070PWP TPS40071PWP R2 90.1 kΩ C2 0.1 µF 1 KFF ILIM 16 2 RT VDD 15 C5 5.6 nF Q1 Si7860DP DBP 11 7 VFB Q2 Si7860DP C13 4.7 nF LDRV 10 PGND 9 PWP L1 COEV DXM1306−1R6 1.6 µH VOUT 1.2 V 10 A D1 BAT54 C9 1 µF 6 SS 8 COMP C4 470 pF SW 12 C14 22 µF C8 0.1 µF HDRV 13 5 SGND R4 330 kΩ C12 22 µF BOOST 14 3 LVBP 22 nF R5 10 kΩ C7 10 pF C10 0.1 µF 4 PGD C3 R9 2 kΩ + C15 47 µF + + C16 C17 C18 470 µF 470 µF 0.1 µF D2 BAT54 − R7 8.66 kΩ R3 12.1 kΩ C6 4.7 nF R8 226 Ω Note resistor across soft−start capacitor. Diode D2 for operation below −10°C Figure 15. 500 kHz, 5 V to 1.2 V with Improved High-Side Gate Drive See Application Information section Boost Diodes. 18 VDG−03177 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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