TPS73201, TPS73215, TPS73216 TPS73218, TPS73225, TPS73230 TPS73233, TPS73250 www.ti.com SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004 Cap-Free, NMOS, 250mA Low Dropout Regulator with Reverse Current Protection FEATURES • • • • • • • • • • • Stable with No Output Capacitor or Any Value or Type of Capacitor Input Voltage Range: 1.7V to 5.5V Ultralow Dropout Voltage: 40mV Typ at 250mA Excellent Load Transient Response—with or without Optional Output Capacitor New NMOS Topology Provides Low Reverse Leakage Current Low Noise: 30µVRMS Typ (10kHz to 100kHz) 0.5% Initial Accuracy 1% Overall Accuracy (Line, Load, and Temperature) Less Than 1µA Max IQ in Shutdown Mode Thermal Shutdown and Specified Min/Max Current Limit Protection Available in Multiple Output Voltage Versions – Fixed Outputs of 1.2V, 1.5V, 1.6V, 1.8V, 2.5V, 3.0V, 3.3V, and 5.0V – Adjustable Outputs From 1.20V to 5.5V – Custom Outputs Available APPLICATIONS • • • • DESCRIPTION The TPS732xx family of low-dropout (LDO) voltage regulators uses a new topology: an NMOS pass element in a voltage-follower configuration. This topology is stable using output capacitors with low ESR, and even allows operation without a capacitor. It also provides high reverse blockage (low reverse current) and ground pin current that is nearly constant over all values of output current. The TPS732xx uses an advanced BiCMOS process to yield high precision while delivering very low dropout voltages and low ground pin current. Current consumption, when not enabled, is under 1µA and ideal for portable applications. The extremely low output noise (30µVRMS with 0.1µF CNR) is ideal for powering VCOs. These devices are protected by thermal shutdown and foldback current limit. DCQ PACKAGE SOT223 (TOP VIEW) DBV PACKAGE SOT23 (TOP VIEW) IN 1 GND 2 EN 3 TAB IS GND 5 OUT 1 4 2 4 5 NR/FB Portable/Battery-Powered Equipment Post-Regulation for Switching Supplies Noise-Sensitive Circuitry such as VCOs Point of Load Regulation for DSPs, FPGAs, ASICs, and Microprocessors IN OUT Optional VIN 3 GND EN NR/FB Optional IN VOUT OUT TPS732xx EN GND NR Optional Typical Application Circuit for Fixed-Voltage Versions Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2004, Texas Instruments Incorporated TPS73201, TPS73215, TPS73216 TPS73218, TPS73225, TPS73230 TPS73233, TPS73250 www.ti.com SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION PRODUCT TPS73201 TPS73215 TPS73216 TPS73218 TPS73225 TPS73230 TPS73233 TPS73250 VOUT (1) PACKAGE-LEAD (DESIGNATOR) (2) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING SOT23-5 (DBV) -40°C to +125°C PJEQ Adjustable or 1.2V (3) SOT223-5 (DCQ) -40°C to +125°C PS73201 SOT23-5 (DBV) -40°C to +125°C T38 SOT223-5 (DCQ) -40°C to +125°C PS73215 1.5V 1.6V SOT23-5 (DBV) -40°C to +125°C T50 SOT23-5 (DBV) -40°C to +125°C T37 1.8V SOT223-5 (DCQ) -40°C to +125°C PS73218 SOT23-5 (DBV) -40°C to +125°C T36 SOT223-5 (DCQ) -40°C to +125°C PS73225 2.5V SOT23-5 (DBV) -40°C to +125°C T39 SOT223-5 (DCQ) -40°C to +125°C PS73230 3.0V SOT23-5 (DBV) -40°C to +125°C T40 SOT223-5 (DCQ) -40°C to +125°C PS73233 SOT23-5 (DBV) -40°C to +125°C T41 3.3V 5.0V SOT223-5 (DCQ) (1) (2) (3) 2 -40°C to +125°C PS73250 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TPS73201DBVT Tape and Reel, 250 TPS73201DBVR Tape and Reel, 3000 TPS73201DCQT Tube, 80 TPS73201DCQR Tape and Reel, 2500 TPS73215DBVT Tape and Reel, 250 TPS73215DBVR Tape and Reel, 3000 TPS73215DCQT Tube, 80 TPS73215DCQR Tape and Reel, 2500 TPS73216DBVT Tape and Reel, 250 TPS73216DBVR Tape and Reel, 3000 TPS73218DBVT Tape and Reel, 250 TPS73218DBVR Tape and Reel, 3000 TPS73218DCQT Tube, 80 TPS73218DCQR Tape and Reel, 2500 TPS73225DBVT Tape and Reel, 250 TPS73225DBVR Tape and Reel, 3000 TPS73225DCQT Tube, 80 TPS73225DCQR Tape and Reel, 2500 TPS73230DBVT Tape and Reel, 250 TPS73230DBVR Tape and Reel, 3000 TPS73230DCQT Tube, 80 TPS73230DCQR Tape and Reel, 2500 TPS73233DBVT Tape and Reel, 250 TPS73233DBVR Tape and Reel, 3000 TPS73233DCQT Tube, 80 TPS73233DCQR Tape and Reel, 2500 TPS73250DBVT Tape and Reel, 250 TPS73250DBVR Tape and Reel, 3000 TPS73250DCQT Tube, 80 TPS73250DCQR Tape and Reel, 2500 Custom output voltages from 1.3V to 4V in 100mV increments are available on a quick-turn basis for prototyping. Production quantities are available; minimum order quantities apply. Contact factory for details and availability. For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet. For fixed 1.2V operation, tie FB to OUT. TPS73201, TPS73215, TPS73216 TPS73218, TPS73225, TPS73230 TPS73233, TPS73250 www.ti.com SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004 ABSOLUTE MAXIMUM RATINGS over operating junction temperature range unless otherwise noted (1) TPS732xx UNIT VIN range -0.3 to 6.0 V VEN range -0.3 to 6.0 V VOUT range -0.3 to 5.5 V Peak output current Internally limited Output short-circuit duration Indefinite Continuous total power dissipation See Dissipation Ratings Table Junction temperature range, TJ -55 to +150 Storage temperature range °C -65 to +150 °C ESD rating, HBM 2 kV ESD rating, CDM 500 V (1) Stresses beyond those listedunder absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyondthose indicated under the Electrical Characteristics is not implied. Exposureto absolute maximum rated conditions for extended periods may affect devicereliability. POWER DISSIPATION RATINGS (1) BOARD PACKAGE RΘJC RΘJA DERATING FACTOR ABOVE TA = 25°C TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING Low-K (2) DBV 64°C/W 255°C/W 3.9mW/°C 390mW 215mW 155mW DBV 64°C/W 180°C/W 5.6mW/°C 560mW 310mW 225mW DCQ 15°C/W 53°C/W 18.9mW/°C 1.89W 1.04W 0.76W High-K (3) Low-K (2) (1) (2) (3) SeePower Dissipation in theApplications section formore information related to thermal design. The JEDEC Low-K (1s) boarddesign used to derive this data was a 3 inch x 3 inch, two-layer board with2-ounce copper traces on top of the board. The JEDEC High-K (2s2p)board design used to derive this data was a 3 inch x 3 inch, multilayer boardwith 1-ounce internal power and ground planes and 2-ounce copper traces on thetop and bottom of the board. 3 TPS73201, TPS73215, TPS73216 TPS73218, TPS73225, TPS73230 TPS73233, TPS73250 www.ti.com SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS Over operating temperature range (TJ = -40°C to +125°C), VIN = VOUT(nom) + 0.5V (1), IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise noted. Typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS VIN Input voltage range (1) VFB Internal reference (TPS73201) ∆VOUT%/∆VIN Accuracy (1) TJ = 25°C 1.198 UNIT 5.5 V 1.210 V 5.5-VDO V +0.5 TJ = 25°C -0.5 VIN, IOUT, and T VOUT + 0.5V ≤ VIN ≤ 5.5V; 10 mA ≤ IOUT≤ 250mA -1.0 VOUT(nom) + 0.5V ≤ VIN ≤ 5.5V 1.20 MAX VFB Nominal Line regulation (1) TYP 1.7 Output voltage range (TPS73201) (2) VOUT MIN ±0.5 +1.0 0.01 1mA ≤ IOUT ≤ 250mA 0.002 10mA ≤ IOUT ≤ 250mA 0.0005 % %/V ∆VOUT%/∆IOUT Load regulation VDO Dropout voltage (3) (VIN = VOUT (nom) - 0.1V) IOUT = 250mA ZO(DO) Output impedance in dropout 1.7 V ≤ VIN ≤ VOUT + VDO ICL Output current limit VOUT = 0.9 × VOUT(nom) ISC Short-circuit current VOUT = 0V 300 IREV Reverse leakage current (4) (-IIN) VEN ≤ 0.5V, 0V≤ VIN ≤ VOUT 0.1 10 IGND Ground pin current IOUT = 10mA (IQ) 400 550 IOUT = 250mA 650 950 ISHDN Shutdown current (IGND) VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5 0.02 1 µA IFB FB pin current (TPS73201) .1 .3 µA PSRR Power-supply rejection ratio (ripple rejection) f = 100Hz, IOUT = 250 mA 58 f = 10kHz, IOUT = 250 mA 37 VN Output noise voltage BW = 10Hz - 100kHz COUT = 10µF, No CNR 27 × VOUT COUT= 10µF, CNR = 0.01µF 8.5 × VOUT tSTR Startup time VOUT = 3V, RL = 30Ω COUT = 1 µF, CNR= 0.01 µF 600 VEN(HI) Enable high (enabled) VEN(LO) Enable low (shutdown) IEN(HI) Enable pin current (enabled) TSD Thermal shutdown temperature TJ Operating junction temperature (1) (2) (3) (4) 4 40 150 250 425 mV Ω 0.25 600 mA mA µA µA dB µVRMS µs 1.7 VIN 0 0.5 V 0.1 µA VEN = 5.5V 0.02 Shutdown Temp increasing 160 Reset Temp decreasing 140 Minimum VIN = VOUT +VDO or 1.7V, whichever isgreater. TPS73201 is tested atVOUT = 2.5V. VDO is not measured for the TPS73214, TPS73215 orTPS73216 since minimum VIN =1.7V. Fixed-voltage versions only;refer to Applicationssection for more information. %/mA -40 V °C 125 °C TPS73201, TPS73215, TPS73216 TPS73218, TPS73225, TPS73230 TPS73233, TPS73250 www.ti.com SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004 FUNCTIONAL BLOCK DIAGRAMS IN Charge Pump EN Thermal Protection Ref Servo 27kΩ Bandgap Error Amp Current Limit OUT 8kΩ GND R1 R1 + R2 = 80kΩ R2 NR Figure 1. Fixed Voltage Version IN Table 1. Standard 1% Resistor Values for Common Output Voltages Charge Pump EN Thermal Protection Ref Servo 27kΩ Bandgap Error Amp 8kΩ R1 R2 1.2V Short Open 1.5V 23.2kΩ 95.3kΩ 1.8V 28.0kΩ 56.2kΩ 2.5V 39.2kΩ 36.5kΩ 2.8V 44.2kΩ 33.2kΩ 3.0V 46.4kΩ 30.9kΩ 3.3V 52.3kΩ 30.1kΩ 5.0V 78.7kΩ 24.9kΩ OUT Current Limit GND VOUT NOTE: VOUT = (R1 + R2)/R2 × 1.204; R1R2 ≅ 19kΩ for best R1 accuracy. 80kΩ FB R2 Figure 2. Adjustable Voltage Version 5 TPS73201, TPS73215, TPS73216 TPS73218, TPS73225, TPS73230 TPS73233, TPS73250 www.ti.com SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004 PIN ASSIGNMENTS DBV PACKAGE SOT23 (TOP VIEW) IN 1 GND 2 EN 3 DCQ PACKAGE SOT223 (TOP VIEW) 5 OUT 4 NR/FB TAB IS GND 1 2 IN OUT 3 4 5 GND EN NR/FB TERMINAL FUNCTIONS TERMINAL SOT23 (DBV) PIN NO. SOT223 (DCQ) PIN NO. IN 1 1 Unregulated input supply GND 2 3 Ground EN 3 5 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. Refer to the Shutdown section under Applications Information for more details. EN can be connected to IN if not used. NR 4 4 Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by the internal bandgap. This allows output noise to be reduced to very low levels. FB 4 4 Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set the output voltage of the device. OUT 5 2 Output of the Regulator. There are no output capacitor requirements for stability. NAME 6 DESCRIPTION TPS73201, TPS73215, TPS73216 TPS73218, TPS73225, TPS73230 TPS73233, TPS73250 www.ti.com SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise noted. LOAD REGULATION LINE REGULATION 0.5 0.20 Referred to IOUT = 10mA −40C +25C +125C Change in VOUT (%) 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 Referred to VIN = VOUT + 0.5V at IOUT = 10mA 0.15 Change in VOUT (%) 0.4 0.10 +25 C +125C 0.05 0 −0.05 −40 C −0.10 −0.15 −0.4 −0.5 −0.20 0 50 100 150 200 0 250 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIN − VOUT (V) IOUT (mA) Figure 3. Figure 4. DROPOUT VOLTAGE vsOUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE 100 100 TPS73225DBV TPS73225DBV 80 80 VDO (mV) VDO (mV) +125 C 60 +25 C 40 20 60 50 20 −40C 0 0 50 100 150 200 0 −50 250 IOUT (mA) −25 0 25 50 75 100 125 Temperature (C) Figure 5. Figure 6. OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM 30 18 IOUT = 10mA 16 25 I OUT = 10mA All Voltage Versions Percent of Units (%) 15 10 12 10 8 6 4 5 2 0 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 0 −1.0 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Percent of Units (%) 14 20 VOUT Error (%) Worst Case dVOUT/dT (ppm/ C) Figure 7. Figure 8. 7 TPS73201, TPS73215, TPS73216 TPS73218, TPS73225, TPS73230 TPS73233, TPS73250 www.ti.com SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise noted. GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE 1000 800 900 700 IOUT = 250mA 800 600 600 I GND (µA) I GND (µA) 700 500 400 300 100 50 100 150 200 VIN = 5.5V VIN = 4V VIN = 2V 0 −50 250 −25 0 25 50 75 100 IOUT (mA) Temperature (C) Figure 9. Figure 10. CURRENT LIMIT vs VOUT (FOLDBACK) GROUND PIN CURRENT in SHUTDOWN vs TEMPERATURE 500 125 1 450 VENABLE = 0.5V VIN = VOUT + 0.5V ICL 400 350 300 IGND (µA) Current Limit (mA) 300 100 0 0 400 200 VIN = 5.5V VIN = 4V VIN = 2V 200 500 ISC 250 200 0.1 150 100 50 TPS73233 0 0.5 1.0 1.5 2.0 2.5 3.0 −25 0 25 50 75 100 VOUT (V) Temperature (C) Figure 11. Figure 12. CURRENT LIMIT vs VIN CURRENT LIMIT vs TEMPERATURE 600 600 550 550 500 500 450 400 350 300 125 450 400 350 300 250 1.5 8 0.01 −50 3.5 Current Limit (mA) Current Limit (mA) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 250 −50 −25 0 25 50 VIN (V) Temperature ( C) Figure 13. Figure 14. 75 100 125 TPS73201, TPS73215, TPS73216 TPS73218, TPS73225, TPS73230 TPS73233, TPS73250 www.ti.com SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise noted. PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs VIN - VOUT 40 90 IOUT = 100mA COUT = Any 80 35 30 IOUT = 1mA COUT = 10µF 60 50 IO = 100mA CO = 1µF IOUT = 1mA C OUT = Any 40 25 PSRR (dB) Ripple Rejection (dB) 70 IOUT = 1mA COUT = 1µF 20 15 30 20 IOUT = Any COUT = 0µF 10 0 10 100 1k 10k 10 I OUT = 100mA COUT = 10µF Frequency = 100kHz COUT = 10µF CNR = 0.01µF 5 0 100k 1M 0 10M 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Frequency (Hz) VIN − VOUT (V) Figure 15. Figure 16. NOISE SPECTRAL DENSITY CNR = 0µF NOISE SPECTRAL DENSITY CNR = 0.01µF 1 1.8 2.0 1 eN (µV/√Hz) eN (µV/√Hz) C OUT = 1µF COUT = 0µF 0.1 COUT = 10µF COUT = 1µF 0.1 COUT = 0µF COUT = 10µF IOUT = 150mA IOUT = 150mA 0.01 0.01 10 100 1k 10k 100k 10 100 1k Frequency (Hz) Frequency (Hz) Figure 17. Figure 18. RMS NOISE VOLTAGE vs COUT 10k 100k RMS NOISE VOLTAGE vs CNR 60 140 50 120 VOUT = 5.0V VOUT = 5.0V 100 30 VN (RMS) VN (RMS) 40 VOUT = 3.3V 20 10 20 CNR = 0.01µF 10Hz < Frequency < 100kHz 0.1 1 0 10 VOUT = 3.3V 60 40 VOUT = 1.5V 0 80 VOUT = 1.5V COUT = 0µF 10Hz < Frequency < 100kHz 1p 10p 100p COUT (µF) CNR (F) Figure 19. Figure 20. 1n 10n 9 TPS73201, TPS73215, TPS73216 TPS73218, TPS73225, TPS73230 TPS73233, TPS73250 www.ti.com SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise noted. TPS73233 LOAD TRANSIENT RESPONSE VIN = 3.8V TPS73233 LINE TRANSIENT RESPONSE COUT = 0µF 50mV/tick IOUT = 250mA VOUT COUT = 0µF 50mV/div COUT = 1µF 50mV/tick COUT = 10µF 50mV/tick VOUT VOUT VOUT C OUT = 100µF 50mV/div 5.5V 250mA 10mA 4.5V 1V/div VIN I OUT 10µs/div 10µs/div Figure 21. Figure 22. TPS73233 TURN-ON RESPONSE TPS73233 TURN-OFF RESPONSE RL = 1kΩ COUT = 0µF RL = 20Ω COUT = 10µF VOUT R L = 20Ω C OUT = 1µF R L = 20Ω C OUT = 1µF 1V/div RL = 1kΩ COUT = 0µF RL = 20Ω COUT = 10µF VOUT 2V 2V VEN 1V/div 1V/div 0V 0V VEN 100µs/div 100µs/div Figure 23. Figure 24. TPS73233 POWER UP / POWER DOWN IENABLE vs TEMPERATURE 10 6 5 4 VIN VOUT IENABLE (nA) 3 Volts = 0.5V/µs dt 50mA/tick 1V/div VOUT dVIN 2 1 1 0.1 0 −1 −2 50ms/div 0.01 −50 −25 0 25 50 Temperature (°C) Figure 25. 10 Figure 26. 75 100 125 TPS73201, TPS73215, TPS73216 TPS73218, TPS73225, TPS73230 TPS73233, TPS73250 www.ti.com SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS (continued) For all voltage versions at TJ= 25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1µF, unless otherwise noted. TPS73201 IFB vs TEMPERATURE 60 160 55 140 50 120 45 100 I FB (nA) VN (rms) TPS73101 RMS NOISE VOLTAGE vs CADJ 40 35 30 25 80 60 VOUT = 2.5V COUT = 0µF R1 = 39.2kΩ 10Hz < Frequency < 100kHz 20 10p 100p 40 20 1n 10n 0 −50 −25 0 25 50 75 100 CFB (F) Temperature (C) Figure 27. Figure 28. TPS73201 LOAD TRANSIENT, ADJUSTABLE VERSION TPS73201 LINE TRANSIENT, ADJUSTABLE VERSION CFB = 10nF R1 = 39.2kΩ COUT = 0µF 100mV/div COUT = 0µF VOUT 100mV/div VOUT 100mV/div C OUT = 10µF 100mV/div COUT = 10µF 125 VOUT = 2.5V CFB = 10nF VOUT VOUT 4.5V 250mA 3.5V VIN 10mA 10µs/div Figure 29. IOUT 5µs/div Figure 30. 11 TPS73201, TPS73215, TPS73216 TPS73218, TPS73225, TPS73230 TPS73233, TPS73250 www.ti.com SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004 APPLICATION INFORMATION The TPS732xx belongs to a family of new generation LDO regulators that use an NMOS pass transistor to achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints. These features, combined with low noise and an enable input, make the TPS732xx ideal for portable applications. This regulator family offers a wide selection of fixed output voltage versions and an adjustable output version. All versions have thermal and over-current protection, including foldback current limit. Figure 31 shows the basic circuit connections for the fixed voltage models. Figure 32 gives the connections for the adjustable output version (TPS73201). Optional input capacitor. May improve source impedance, noise, or PSRR. VIN Optional output capacitor. May improve load transient, noise, or PSRR. IN VOUT OUT TPS732xx EN GND NR Optional bypass capacitor to reduce output noise. VIN IN Optional output capacitor. May improve load transient, noise, or PSRR. EN VOUT OUT TPS732xx GND R1 CFB FB R2 VOUT = (R1 + R2) × 1.204 R2 Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1µF to 1µF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the power source. The TPS732xx does not require an output capacitor for stability and has maximum phase margin with no capacitor. It is designed to be stable for all available types and values of capacitors. In applications where VIN - VOUT < 0.5V and multiple low ESR capacitors are in parallel, ringing may occur when the product of COUT and total ESR drops below 50nΩF. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance will meet this requirement. OUTPUT NOISE Figure 31. Typical Application Circuit for Fixed-Voltage Versions Optional input capacitor. May improve source impedance, noise, or PSRR. INPUT AND OUTPUT CAPACITOR REQUIREMENTS Optional capacitor reduces output noise. Figure 32. Typical Application Circuit for Adjustable-Voltage Versions R1 and R2 can be calculated for any output voltage using the formula shown in Figure 32. Sample resistor values for common output voltages are shown in Figure 2. For best accuracy, make the parallel combination of R1 and R2 approximately 19kΩ. A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the dominant noise source within the TPS732xx and it generates approximately 32µVRMS (10Hz to 100kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by: V (R R2) V N 32VRMS 1 32VRMS OUT R2 VREF (1) Since the value of VREF is 1.2V, this relationship reduces to: V RMS V N(VRMS) 27 V OUT(V) V (2) for the case of no CNR. An internal 27kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10nF, the total noise in the 10Hz to 100kHz bandwidth is reduced by a factor of ~3.2, giving the approximate relationship: VV V V N(VRMS) 8.5 for CNR = 10nF. 12 RMS (V) OUT (3) www.ti.com This noise reduction effect is shown as RMS Noise Voltage vs CNR in the Typical Characteristics section. The TPS73201 adjustable version does not have the noise-reduction pin available. However, connecting a feedback capacitor, CFB, from the output to the FB pin will reduce output noise and improve load transient performance. The TPS732xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass element above VOUT. The charge pump generates ~250µV of switching noise at ~2MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and COUT. BOARD LAYOUT RECOMMENDATION TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the PCB be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. TPS73201, TPS73215, TPS73216 TPS73218, TPS73225, TPS73230 TPS73233, TPS73250 SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004 DROPOUT VOLTAGE The TPS732xx uses an NMOS pass transistor to achieve extremely low dropout. When (VIN - VOUT) is less than the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS-ON of the NMOS pass element. For large step changes in load current, the TPS732xx requires a larger voltage drop from VIN to VOUT to avoid degraded transient response. The boundary of this transient dropout region is approximately twice the dc dropout. Values of VIN - VOUT above this line insure normal transient response. Operating in the transient dropout region can cause an increase in recovery time. The time required to recover from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions [full-scale instantaneous load change with (VIN - VOUT) close to dc dropout levels], the TPS732xx can take a couple of hundred microseconds to return to the specified regulation accuracy. TRANSIENT RESPONSE INTERNAL CURRENT LIMIT The TPS732xx internal current limit helps protect the regulator during fault conditions. Foldback helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when VOUT drops below 0.5V. See Figure 11 in the Typical Characteristics section for a graph of IOUT vs VOUT. SHUTDOWN The Enable pin is active high and is compatible with standard TTL-CMOS levels. VEN below 0.5V (max) turns the regulator off and drops the ground pin current to approximately 10nA. When shutdown capability is not required, the Enable pin can be connected to VIN. When a pull-up resistor is used, and operation down to 1.8V is required, use pull-up resistor values below 50 kΩ. The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration allows operation without an output capacitor for many applications. As with any regulator, the addition of a capacitor (nominal value 1µF) from the output pin to ground will reduce undershoot magnitude but increase duration. In the adjustable version, the addition of a capacitor, CFB, from the output to the adjust pin will also improve the transient response. The TPS732xx does not have active pull-down when the output is over-voltage. This allows applications that connect higher voltage sources, such as alternate power supplies, to the output. This also results in an output overshoot of several percent if the load current quickly drops to zero when a capacitor is connected to the output. The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate determined by output capacitor COUT and the internal/external load resistance. The rate of decay is given by: (Fixed voltage version) V OUT dVdt C OUT 80k (4) 13 TPS73201, TPS73215, TPS73216 TPS73218, TPS73225, TPS73230 TPS73233, TPS73250 www.ti.com SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004 (Adjustable voltage version) VOUT dVdt C OUT 80k (R 1 R 2) (5) REVERSE CURRENT The NMOS pass element of the TPS732xx provides inherent protection against current flow from the output of the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed from the gate of the pass element, the enable pin must be driven low before the input voltage is removed. If this is not done, the pass element may be left on due to stored charge on the gate. After the enable pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note that reverse current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. There will be additional current flowing into the OUT pin due to the 80kΩ internal resistor divider to ground (see Figure 1 and Figure 2). For the TPS73201, reverse current may flow when VFB is more than 1.0V above VIN. THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due to overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good 14 reliability, thermal protection should trigger at least 35°C above the maximum expected ambient condition of your application. This produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS732xx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS732xx into thermal shutdown will degrade device reliability. POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the Power Dissipation Ratings table. Using heavier copper will increase the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers will also improve the heat-sink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT): P D (VIN VOUT) I OUT (6) Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required output voltage. Package Mounting Solder pad footprint recommendations for the TPS732xx are presented in Application Bulletin Solder Pad Recommendations for Surface-Mount Devices (AB-132), available from the Texas Instruments web site at www.ti.com. PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY TPS73201DBVR ACTIVE SOP DBV 5 3000 TPS73201DBVT ACTIVE SOP DBV 5 250 TPS73201DCQ ACTIVE SOP DCQ 6 78 TPS73201DCQR ACTIVE SOP DCQ 6 2500 TPS73215DBVR ACTIVE SOP DBV 5 3000 TPS73215DBVT ACTIVE SOP DBV 5 250 TPS73215DCQ ACTIVE SOP DCQ 6 78 TPS73215DCQR ACTIVE SOP DCQ 6 2500 TPS73216DBVR ACTIVE SOP DBV 5 3000 TPS73216DBVT ACTIVE SOP DBV 5 250 TPS73218DBVR ACTIVE SOP DBV 5 3000 TPS73218DBVT ACTIVE SOP DBV 5 250 TPS73218DCQ ACTIVE SOP DCQ 6 78 TPS73218DCQR ACTIVE SOP DCQ 6 2500 TPS73225DBVR ACTIVE SOP DBV 5 3000 TPS73225DBVT ACTIVE SOP DBV 5 250 TPS73225DCQ ACTIVE SOP DCQ 6 78 TPS73225DCQR ACTIVE SOP DCQ 6 2500 TPS73230DBVR ACTIVE SOP DBV 5 3000 TPS73230DBVT ACTIVE SOP DBV 5 250 TPS73230DCQ ACTIVE SOP DCQ 6 78 TPS73230DCQR ACTIVE SOP DCQ 6 2500 TPS73233DBVR ACTIVE SOP DBV 5 3000 TPS73233DBVT ACTIVE SOP DBV 5 250 TPS73233DCQ ACTIVE SOP DCQ 6 78 TPS73233DCQR ACTIVE SOP DCQ 6 2500 TPS73250DBVR ACTIVE SOP DBV 5 3000 TPS73250DBVT ACTIVE SOP DBV 5 250 TPS73250DCQ ACTIVE SOP DCQ 6 78 TPS73250DCQR ACTIVE SOP DCQ 6 2500 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. 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