TPS73619 SBVS167 – JUNE 2011 www.ti.com 400mA Low-Dropout Regulator for C2000™ Check for Samples: TPS73619 FEATURES DESCRIPTION • • • • The TPS73619 is a low-dropout (LDO) voltage regulator that offers very good line and load transient response, even without the use of an output capacitor. The TPS73619 is suitable for driving the C2000 MCUs from Texas Instruments. These devices offer very low voltage, thereby reducing power loss. 1 23 • • • • Optimal Output Voltage for Core Rail of C2000 Good Line/Load Transient Response for MCUs 400mA LDO Voltage Regulator with Enable Very Low Dropout Voltage: 75mV (typ) at 400mA Reverse Current Protection Stable with or without Output Capacitor 1% Overall Accuracy Over Line, Load, and Temperature Available in 8-Pin SON-8 Package In combination with a voltage supervisor such as the TPS3808G19 or TPS3808G01, the TPS73619 can deliver tight VCORE voltage and generate accurate power-good signals that meet or exceed power requirements for the C2000. The TPS73619 is available in an 8-pin SON-8 package. APPLICATIONS • C2000 Core Power Rail Supply DRB PACKAGE 3mm x 3mm SON (TOP VIEW) OUT 1 8 IN N/C 2 7 N/C NR/FB 3 6 N/C GND 4 5 EN 1.8 V 3.3 V 10 kW TPS3808G01 or TPS3808G19 TPS73219 or TPS73619 OUT EN LDO 1.8 V SENSE 51 kW 15 kW RESET SVS 1.8 V 10 kW C2000 TPS73534 or TPS73734 TPS3808G01 OUT EN LDO 3.3 V SENSE 91 kW RESET XRS SVS 3.3 V 13 kW Figure 1. Typical Application 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. C2000 is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPS73619 SBVS167 – JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT TPS736xx yy yz (1) (2) (3) VOUT (2) XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable (3)). YYY is package designator. Z is package quantity. For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet or see the TI website at www.ti.com. Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available on a quick-turn basis using innovative factory EEPROM programming. Minimum order quantities apply; contact factory for details and availability. For fixed 1.20V operation, tie FB to OUT. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) PARAMETER TPS73619 UNIT VIN range –0.3 to 6.0 V VEN range –0.3 to 6.0 V VOUT range –0.3 to 5.5 V –0.3 to 6.0 V VNR, VFB range Peak output current Output short-circuit duration Continuous total power dissipation Internally limited Indefinite See Thermal Information Table Junction temperature range, TJ –55 to +150 Storage temperature range –65 to +150 °C ESD rating, HBM 2 kV ESD rating, CDM 500 V (1) 2 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Copyright © 2011, Texas Instruments Incorporated TPS73619 SBVS167 – JUNE 2011 www.ti.com THERMAL INFORMATION TPS73619 (3) THERMAL METRIC (1) (2) DRB UNITS 8 PINS Junction-to-ambient thermal resistance (4) θJA (5) 47.8 θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (6) N/A ψJT Junction-to-top characterization parameter (7) 2.1 ψJB Junction-to-board characterization parameter (8) 17.8 θJCbot Junction-to-case (bottom) thermal resistance (9) 12.1 (1) (2) (3) (4) (5) (6) (7) (8) (9) 83 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array. (b) The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Copyright © 2011, Texas Instruments Incorporated 3 TPS73619 SBVS167 – JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), VIN = 24V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted. Typical values are at TJ = +25°C. PARAMETER TEST CONDITIONS VIN Input voltage range VOUT Accuracy ΔVOUT%/ΔVIN Line regulation MIN MAX UNIT 2.1 5.5 V +0.5 Nominal TJ = +25°C –0.5 over VIN, IOUT, and T VOUT + 0.5V ≤ VIN ≤ 5.5V; 10mA ≤ IOUT ≤ 400mA –1.0 ΔVOUT%/ΔIOUT Load regulation VO(nom) + 0.5V ≤ VIN ≤ 5.5V TYP ±0.5 0.01 1mA ≤ IOUT ≤ 400mA 0.002 10mA ≤ IOUT ≤ 400mA 0.0005 VDO Dropout voltage (VIN = VOUT(nom) – 0.1V) IOUT = 400mA ZO(DO) Output impedance in dropout 1.7V ≤ VIN ≤ VOUT + VDO +1.0 75 %/V %/mA 200 mV 800 mA 800 mA Ω 0.25 VOUT = 0.9 × VOUT(nom) 400 3.6V ≤ VIN ≤ 4.2V, 0°C ≤ TJ ≤ +70°C 500 650 ICL Output current limit ISC Short-circuit current VOUT = 0V 450 IREV Reverse leakage current (1) (–IIN) VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT 0.1 10 IOUT = 10mA (IQ) 400 550 IOUT = 400mA 800 1000 VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5, –40°C ≤ TJ ≤ +100°C 0.02 1 IGND GND pin current ISHDN Shutdown current (IGND) PSRR Power-supply rejection ratio (ripple rejection) f = 100Hz, IOUT = 400mA 58 f = 10KHz, IOUT = 400mA 37 VN Output noise voltage BW = 10Hz – 100KHz COUT = 10μF, No CNR 27 × VOUT COUT = 10μF, CNR = 0.01μF 8.5 × VOUT tSTR Startup time VEN(HI) EN pin high (enabled) VEN(LO) EN pin low (shutdown) IEN(HI) EN pin current (enabled) TSD Thermal shutdown temperature TJ Operating junction temperature (1) 4 VOUT = 3V, RL = 30Ω COUT = 1μF, CNR = 0.01μF mA 0 0.02 Shutdown, temperature increasing +160 Reset, temperature decreasing +140 –40 μA μA μVRMS μs VIN VEN = 5.5V μA dB 600 1.7 % V 0.5 V 0.1 μA °C +125 °C Fixed-voltage versions only; refer to Applications section for more information. Copyright © 2011, Texas Instruments Incorporated TPS73619 SBVS167 – JUNE 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM IN 4MHz Charge Pump EN Thermal Protection Ref Servo 27kΩ Bandgap Error Amp Current Limit OUT 8kΩ GND R1 R1 + R2 = 80kΩ R2 NR Figure 2. Fixed Voltage Version PIN CONFIGURATION DRB PACKAGE 3mm x 3mm SON (TOP VIEW) OUT 1 8 IN N/C 2 7 N/C NR/FB 3 6 N/C GND 4 5 EN PIN DESCRIPTIONS NAME 3x3 SON (DRB) PIN NO. DESCRIPTION IN 8 GND 4, Pad Input supply EN 5 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. Refer to the Shutdown section under Applications Information for more details. EN can be connected to IN if not used. NR 3 Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by the internal bandgap, reducing output noise to very low levels. FB 3 Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set the output voltage of the device. OUT 1 Output of the Regulator. There are no output capacitor requirements for stability. Ground Copyright © 2011, Texas Instruments Incorporated 5 TPS73619 SBVS167 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS For all voltage versions, at TJ = +25°C, VIN = 24V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted. LOAD REGULATION LINE REGULATION 0.20 0.5 Referred to IOUT = 10mA −40_C +25_C +125_ C Change in VOUT (%) 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 Referred to VIN = VOUT + 0.5V at IOUT = 10mA 0.15 Change in VOUT (%) 0.4 0.10 0 −0.05 −40_ C −0.10 −0.15 −0.4 −0.20 −0.5 0 50 100 150 200 250 300 350 0 400 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VIN − VOUT (V) IOUT (mA) Figure 3. Figure 4. DROPOUT VOLTAGE vs OUTPUT CURRENT 100 DROPOUT VOLTAGE vs TEMPERATURE 100 TPS73625DBV +125_ C 80 80 60 VDO (mV) VDO (mV) +25_ C +125_C 0.05 +25_ C 40 −40_C 20 50 100 150 200 250 300 60 40 20 0 −50 0 0 TPS73625DBV I OUT = 400mA 350 400 −25 0 25 50 IOUT (mA) Temperature (_ C) Figure 5. Figure 6. OUTPUT VOLTAGE ACCURACY HISTOGRAM 75 100 125 OUTPUT VOLTAGE DRIFT HISTOGRAM 30 18 IOUT = 10mA 16 25 IOUT = 10mA All Voltage Versions Percent of Units (%) Percent of Units (%) 14 20 15 10 12 10 8 6 4 5 2 0 −1.0 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 0 VOUT Error (%) Worst Case dVOUT/dT (ppm/_C) Figure 7. 6 Figure 8. Copyright © 2011, Texas Instruments Incorporated TPS73619 SBVS167 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) For all voltage versions, at TJ = +25°C, VIN = 24V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted. GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE 900 900 800 800 700 700 600 600 I GND (µA) 1000 IGND (µA) 1000 500 400 300 500 400 300 VIN = 5.5V VIN = 4V VIN = 2V 200 100 0 100 200 300 VIN = 5.5V VIN = 3V VIN = 2V 200 100 0 0 −50 400 −25 0 25 50 75 IOUT (mA) Temperature (_C) Figure 9. Figure 10. GROUND PIN CURRENT in SHUTDOWN vs TEMPERATURE CURRENT LIMIT vs VOUT (FOLDBACK) 100 125 800 1 TPS73633 VENABLE = 0.5V VIN = VO + 0.5V 700 Output Current (mA) IGND (µA) IOUT = 400mA 0.1 ICL 600 500 ISC 400 300 200 100 0.01 −50 −25 0 25 50 75 100 0 -0.5 125 0 0.5 Figure 11. 1.5 2.0 2.5 3.0 3.5 Figure 12. CURRENT LIMIT vs VIN CURRENT LIMIT vs TEMPERATURE 800 800 750 750 700 700 Current Limit (mA) Current Limit (mA) 1.0 Output Voltage (V) Temperature (_C) 650 600 550 500 450 650 600 550 500 450 400 1.5 2.0 2.5 3.0 3.5 4.0 VIN (V) Figure 13. Copyright © 2011, Texas Instruments Incorporated 4.5 5.0 5.5 400 −50 −25 0 25 50 75 100 125 Temperature (_C) Figure 14. 7 TPS73619 SBVS167 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) For all voltage versions, at TJ = +25°C, VIN = 24V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted. PSRR (RIPPLE REJECTION) vs VIN – VOUT PSRR (RIPPLE REJECTION) vs FREQUENCY 90 40 IOUT = 100mA COUT = Any Ripple Rejection (dB) 70 IOUT = 1mA COUT = 1µF 35 30 IOUT = 1mA COUT = 10µF 60 50 IO = 100mA CO = 1µF IOUT = 1mA C OUT = Any 40 25 PSRR (dB) 80 20 15 30 20 IOUT = Any COUT = 0µF 10 VIN = VOUT + 1V 0 10 100 1k 10k Frequency = 10kHz COUT = 10mF VOUT = 2.5V IOUT = 100mA 10 I OUT = 100mA COUT = 10µF 5 0 100k 1M 0 10M 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Frequency (Hz) VIN - VOUT (V) Figure 15. Figure 16. NOISE SPECTRAL DENSITY CNR = 0μF NOISE SPECTRAL DENSITY CNR = 0.01μF 1 1.8 2.0 1 COUT = 0µF 0.1 COUT = 10µF eN (µV/√Hz) eN (µV/√Hz) C OUT = 1µF COUT = 1µF 0.1 COUT = 0µF COUT = 10µF IOUT = 150mA IOUT = 150mA 0.01 0.01 10 100 1k 10k 100k 10 100 1k Frequency (Hz) Frequency (Hz) Figure 17. Figure 18. RMS NOISE VOLTAGE vs COUT 10k 100k RMS NOISE VOLTAGE vs CNR 60 140 50 120 VOUT = 5.0V VOUT = 5.0V 100 30 VN (RMS) VN (RMS) 40 VOUT = 3.3V 80 VOUT = 3.3V 60 20 40 VOUT = 1.5V 10 0 0.1 8 20 CNR = 0.01µF 10Hz < Frequency < 100kHz 0 1 10 VOUT = 1.5V COUT = 0µF 10Hz < Frequency < 100kHz 1p 10p 100p COUT (µF) CNR (F) Figure 19. Figure 20. 1n 10n Copyright © 2011, Texas Instruments Incorporated TPS73619 SBVS167 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) For all voltage versions, at TJ = +25°C, VIN = 24V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted. TPS73633 LOAD TRANSIENT RESPONSE VIN = 3.8V TPS73633 LINE TRANSIENT RESPONSE COUT = 0µF 100mV/tick IOUT = 400mA VOUT COUT = 0µF 50mV/div COUT = 1µF 50mV/tick COUT = 10µF 20mV/tick VOUT VOUT VOUT COUT = 100µF 50mV/div VOUT dVIN 5.5V 400mA IOUT 50mA/tick 10mA 1V/div VIN 10µs/div 10µs/div Figure 21. Figure 22. TPS73633 TURN-ON RESPONSE TPS73633 TURN-OFF RESPONSE RL = 1kΩ CO UT = 0µF R L = 20Ω C OUT = 10µF VOUT RL = 20Ω COUT = 1µF 1V/div R L = 20Ω C OUT = 1µF 1V/div R L = 1kΩ C OUT = 0µF RL = 20Ω COUT = 10µF VOUT 2V 2V VEN 1V/div 1V/div 0V 0V VEN 100µs/div 100µs/div Figure 23. Figure 24. TPS73633 POWER UP / POWER DOWN IENABLE vs TEMPERATURE 10 6 5 4 VIN VOUT IENABLE (nA) 3 Volts = 0.5V/µs dt 4.5V 2 1 1 0.1 0 −1 −2 50ms/div 0.01 −50 −25 0 25 50 75 100 125 Temperature (_ C) Figure 25. Copyright © 2011, Texas Instruments Incorporated Figure 26. 9 TPS73619 SBVS167 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) For all voltage versions, at TJ = +25°C, VIN = 24V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1μF, unless otherwise noted. TPS73601 IFB vs TEMPERATURE 60 160 55 140 50 120 45 100 IFB (nA) VN (rms) TPS73601 RMS NOISE VOLTAGE vs CFB 40 60 35 30 25 80 VOUT = 2.5V COUT = 0µF R1 = 39.2kΩ 10Hz < Frequency < 100kHz 20 10p 100p 40 20 1n 10n 0 −50 −25 0 25 50 75 100 CFB (F) Temperature (_C) Figure 27. Figure 28. TPS73601 LOAD TRANSIENT, ADJUSTABLE VERSION TPS73601 LINE TRANSIENT, ADJUSTABLE VERSION CFB = 10nF R1 = 39.2kΩ COUT = 0µF 200mV/div VOUT COUT = 0µF 100mV/div COUT = 10µF 100mV/div COUT = 10µF 200mV/div 125 VOUT = 2.5V CFB = 10nF VOUT VOUT VOUT 4.5V 400mA 3.5V VIN 10mA 10 IOUT 25µs/div 5µs/div Figure 29. Figure 30. Copyright © 2011, Texas Instruments Incorporated TPS73619 SBVS167 – JUNE 2011 www.ti.com APPLICATION INFORMATION The TPS73619 belongs to a family of new generation LDO regulators that use an NMOS pass transistor to achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints. These features, combined with low noise and an enable input, make the TPS73619 ideal for portable applications. This regulator family offers a wide selection of fixed output voltage versions and an adjustable output version. All versions have thermal and over-current protection, including foldback current limit. Figure 31 shows the basic circuit connections for the fixed voltage models. Optional input capacitor. May improve source impedance, noise, or PSRR. VIN Optional output capacitor. May improve load transient, noise, or PSRR. IN OUT VOUT OUTPUT NOISE A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the dominant noise source within the TPS73619 and it generates approximately 32μVRMS (10Hz to 100kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by: GND NR ON OFF Optional bypass capacitor to reduce output noise. Figure 31. Typical Application Circuit for Fixed-Voltage Versions ǒmVV Ǔ RMS V N(mVRMS) + 27 Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1μF to 1μF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the power source. The TPS73619 does not require an output capacitor for stability and has maximum phase margin with no capacitor. It is designed to be stable for all available types and values of capacitors. In applications where multiple low ESR capacitors are in parallel, ringing may occur when the product of COUT and total ESR drops below 50nΩF. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance will meet this requirement. Copyright © 2011, Texas Instruments Incorporated (1) V OUT(V) (2) for the case of no CNR. An internal 27kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10nF, the total noise in the 10Hz to 100kHz bandwidth is reduced by a factor of ~3.2, giving the approximate relationship: ǒmVV Ǔ V N(mVRMS) + 8.5 INPUT AND OUTPUT CAPACITOR REQUIREMENTS VOUT VREF Since the value of VREF is 1.2V, this relationship reduces to: TPS736xx EN (R1 ) R2) + 32mVRMS R2 V N + 32mVRMS RMS V OUT(V) (3) for CNR = 10nF. This noise reduction effect is shown as RMS Noise Voltage vs CNR in the Typical Characteristics section. The TPS73619 uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass element above VOUT. The charge pump generates ~250μV of switching noise at ~4MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and COUT. BOARD LAYOUT RECOMMENDATION TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. 11 TPS73619 SBVS167 – JUNE 2011 INTERNAL CURRENT LIMIT The TPS73619 internal current limit helps protect the regulator during fault conditions. Foldback current limit helps to protect the regulator from damage during output short-circuit conditions by reducing current limit when VOUT drops below 0.5V. See Figure 12 in the Typical Characteristics section. Note from Figure 12 that approximately –0.2V of VOUT results in a current limit of 0mA. Therefore, if OUT is forced below –0.2V before EN goes high, the device may not start up. In applications that work with both a positive and negative voltage supply, the TPS73619 should be enabled first. ENABLE PIN AND SHUTDOWN The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A VEN below 0.5V (max) turns the regulator off and drops the GND pin current to approximately 10nA. When EN is used to shutdown the regulator, all charge is removed from the pass transistor gate, and the output ramps back up to a regulated VOUT (see Figure 23). When shutdown capability is not required, EN can be connected to VIN. However, the pass gate may not be discharged using this configuration, and the pass transistor may be left on (enhanced) for a significant time after VIN has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and faster ramp times upon power-up. In addition, for VIN ramp times slower than a few milliseconds, the output may overshoot upon power-up. Note that current limit foldback can prevent device start-up under some conditions. See the Internal Current Limit section for more information. DROPOUT VOLTAGE The TPS73619 uses an NMOS pass transistor to achieve extremely low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS-ON of the NMOS pass element. For large step changes in load current, the TPS73619 requires a larger voltage drop from VIN to VOUT to avoid degraded transient response. The boundary of this transient dropout region is approximately twice the dc dropout. Values of VIN – VOUT above this line ensure normal transient response. 12 www.ti.com Operating in the transient dropout region can cause an increase in recovery time. The time required to recover from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions [full-scale instantaneous load change with (VIN – VOUT) close to dc dropout levels], the TPS73619 can take a couple of hundred microseconds to return to the specified regulation accuracy. TRANSIENT RESPONSE The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration allows operation without an output capacitor for many applications. As with any regulator, the addition of a capacitor (nominal value 1μF) from the OUT pin to ground will reduce undershoot magnitude but increase its duration. In the adjustable version, the addition of a capacitor, CFB, from the OUT pin to the FB pin will also improve the transient response. The TPS73619 does not have active pull-down when the output is over-voltage. This allows applications that connect higher voltage sources, such as alternate power supplies, to the output. This also results in an output overshoot of several percent if load current quickly drops to zero when a capacitor is connected to the output. The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate determined by output capacitor COUT and the internal/external load resistance. The rate of decay is given by: (Fixed Voltage Version) dVńdt + C OUT VOUT 80kW ø R LOAD (4) REVERSE CURRENT The NMOS pass element of the TPS73619 provides inherent protection against current flow from the output of the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed from the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this is not done, the pass element may be left on due to stored charge on the gate. After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note that reverse current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. There will be additional current flowing into the OUT pin due to the 80kΩ internal resistor divider to ground (see Figure 2 ). Copyright © 2011, Texas Instruments Incorporated TPS73619 SBVS167 – JUNE 2011 www.ti.com THERMAL PROTECTION POWER DISSIPATION Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due to overheating. The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the Thermal Information table. Using heavier copper will increase the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers will also improve the heat-sink effectiveness. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heat sink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of your application. This produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS73619 has been designed to protect against overload conditions. It was not intended to replace proper heat sinking. Continuously running the TPS73619 into thermal shutdown degrades device reliability. Copyright © 2011, Texas Instruments Incorporated Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT): space P D + (VIN * VOUT) I OUT (5) Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required output voltage. PACKAGE MOUNTING Solder pad footprint recommendations for the TPS73619 are presented in Application Bulletin Solder Pad Recommendations for Surface-Mount Devices (SBFA015), available from the Texas Instruments web site at www.ti.com. 13 PACKAGE OPTION ADDENDUM www.ti.com 7-Apr-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS73619DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS73619DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS73619DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS73619DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jun-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS73619DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS73619DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jun-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS73619DRBR SON DRB 8 3000 370.0 355.0 55.0 TPS73619DRBT SON DRB 8 250 220.0 205.0 50.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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