TI TPS71247

TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049B – MAY 2004 – REVISED MARCH 2005
Dual 250 mA Output, UltraLow Noise, High PSRR,
Low-Dropout Linear Regulator
FEATURES
•
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
Dual 250 mA High-Performance RF LDOs
Available in Fixed and Adjustable
Voltage Options (1.2 V to 5.5 V)
High PSRR: 65 dB at 10 kHz
UltraLow Noise: 32 µVrms
Fast Start-Up Time: 60 µs
Stable with 2.2 µF Ceramic Capacitor
Excellent Load/Line Transient Response
Very Low Dropout Voltage: 125 mV at 250 mA
Independent Enable Pins
Thermal Shutdown and Independent Current
Limit
Available in Thermally-Enhanced SON
Package: 3mm x 3mm x 1mm
The TPS712xx family of low-dropout (LDO) voltage
regulators is tailored to noise-sensitive and RF applications. These products feature dual 250 mA LDOs
with ultralow noise, high power-supply rejection ratio
(PSRR), and fast transient and start-up response.
Each regulator output is stable with low-cost 2.2 µF
ceramic output capacitors and features very low
dropout voltages (125 mV typical at 250 mA). Each
regulator achieves fast start-up times (approximately
60 µs with a 0.001 µF bypass capacitor) while
consuming very low quiescent current (300 µA typical
with both outputs enabled). When the device is
placed in standby mode, the supply current is reduced to less than 0.3 µA typical. Each regulator
exhibits approximately 32 µVrms of output voltage
noise with VOUT = 2.8 V and a 0.01 µF noise
reduction (NR) capacitor. Applications with analog
components that are noise-sensitive, such as portable RF electronics, will benefit from high PSRR, low
noise, and fast line and load transient features. The
TPS712 family is offered in a thin 3mm x 3mm SON
package and is fully specified from -40°C to +125°C
(TJ).
APPLICATIONS
•
•
•
•
•
Cellular and Cordless Phones
Wireless PDA/Handheld Products
PCMCIA/Wireless LAN Applications
Digital Camera/Camcorder/Internet Audio
DSP/FPGA/ASIC/Controllers and Processors
PSRR (RIPPLE REJECTION) vs FREQUENCY
80
70
IN 1
10 EN1
NC 2
9 FB1/NC
OUT1 3
8 EN2
7 FB2/NC
OUT2 4
GND 5
6 NR
IOUT = 250 mA
60
PSRR (dB)
DRC PACKAGE
3mm x 3mm SON
(TOP VIEW)
50
40
IOUT = 1 mA
30
20
VOUT = 2.8 V
COUT = 2.2 µF
CNR = 0.01 µF
10
0
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049B – MAY 2004 – REVISED MARCH 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
VOLTAGE (TJ)
PRODUCT
VOUT1
VOUT2
PACKAGELEAD
(DESIGNATOR)
SPECIFIED
TEMPERATURE
RANGE (TJ)
PACKAGE
MARKING
TPS71202
Adjustable
Adjustable
SON-10 (DRC)
-40°C to +125°C
ARQ
TPS71219
1.8 V
Adjustable
SON-10 (DRC)
-40°C to +125°C
ARW
TPS71229
2.8 V
Adjustable
SON-10 (DRC)
-40°C to +125°C
ARU
TPS71247
1.8 V
2.85 V
SON-10 (DRC)
-40°C to +125°C
ARS
TPS71256
2.8 V
2.8 V
SON-10 (DRC)
-40°C to +125°C
ARV
TPS71257
(1)
2.85 V
2.85 V
SON-10 (DRC)
-40°C to +125°C
ORDERING
NUMBER
ART
TRANSPORT
MEDIA, QUANTITY
TPS71202DRCT
Tape and Reel, 250
TPS71202DRCR
Tape and Reel, 3000
TPS71219DRCT
Tape and Reel, 250
TPS71219DRCR
Tape and Reel, 3000
TPS71229DRCT
Tape and Reel, 250
TPS71229DRCR
Tape and Reel, 3000
TPS71247DRCT
Tape and Reel, 250
TPS71247DRCR
Tape and Reel, 3000
TPS71256DRCT
Tape and Reel, 250
TPS71256DRCR
Tape and Reel, 3000
TPS71257DRCT
Tape and Reel, 250
TPS71257DRCR
Tape and Reel, 3000
For the most current package and ordering information, see the Package Ordering Addendum located at the end of this data sheet.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted (1)
TPS712xx
UNIT
VIN range
VEN1, VEN2 range
-0.3 to 6.0
V
-0.3 to VIN + 0.3
V
-0.3 to 6.0
V
VOUT range
Peak output current
Internally limited
Output short-circuit duration
Indefinite
Continuous total power dissipation
See Dissipation Ratings Table
Junction temperature range, TJ
-40 to +150
Storage temperature range
-65 to +150
°C
ESD rating, HBM
2
kV
ESD rating, CDM
500
V
(1)
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS
BOARD
PACKAGE
RθJC
RθJA
DERATING FACTOR
ABOVE TA = 25°C
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
High-K (1)
DRC
48
52
19 mW/°C
1.92 W
1.06 W
0.77 W
(1)
2
The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049B – MAY 2004 – REVISED MARCH 2005
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = -40°C to +125°C), VIN = highest VOUT(nom) + 1.0 V or 2.7 V (whichever is greater),
IOUT = 1 mA, VEN1, 2 = 1.2 V, COUT = 10 µF, CNR = 0.01 µF, and adjustable LDOs are tested at VOUT = 3.0 V, unless otherwise
noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
range (1)
VIN
Input voltage
VFB
Internal reference (adjustable LDOs)
Accuracy (1)
Nominal
TJ = 25°C, IOUT = 0 mA
Over VIN,
IOUT, and T
VOUT + 1.0 V ≤ VIN ≤ 5.5 V,
0 µA ≤ IOUT ≤ 250 mA
Line regulation (1)
VOUT + 1.0 V ≤ VIN ≤ 5.5 V
∆VOUT%/∆IOU
Load regulation
T
Dropout voltage (2)
(VIN = VOUT(nom) - 0.1V)
ICL
Output current limit
IGND
Ground pin current
5.5
V
1.225
1.250
V
VFB
5.5 - VDO
V
-1.5
+1.5
2.7
∆VOUT%/∆VIN
VDO
MAX
1.200
Output voltage range
(adjustable LDOs)
VOUT
TYP
2.8 V,
2.85 V
Adjustable
-3
±1
%/V
0 µA ≤ IOUT ≤ 250 mA
0.8
%/mA
IOUT1 = IOUT2 = 250 mA
125
230
mV
600
800
mA
400
One LDO
enabled
IOUT = 1 mA (enabled channel)
190
250
Both LDOs
enabled
IOUT1 = IOUT2 = 1 mA to 250 mA
300
600
VEN ≤ 0.4 V, 0 V ≤ VIN ≤ 5.5 V
0.3
2.0
µA
0.1
1
µA
Shutdown current (3)
IFB
FB pin current (adjustable LDOs)
µA
Vn
Output noise voltage,
BW = 10 Hz - 100 kHz
No CNR, IOUT = 250 mA
PSRR
Power-supply rejection ratio
(ripple rejection)
f = 100 Hz, IOUT = 250 mA
65
f = 10 kHz, IOUT = 250 mA
65
tSTR
Startup time
VOUT = 2.85 V, RL = 30Ω, CNR = 0.001 µF
60
VIH
Enable threshold high (EN1, EN2)
VIL
Enable threshold low (EN1, EN2)
IEN
Enable pin current (EN1, EN2)
TSD
Thermal shutdown temperature
(1)
(2)
(3)
%
0.05
VOUT = 0.9 × VOUT(nom)
ISHDN
UVLO
+3
UNIT
80.0 × VOUT
CNR = 0.01 µF, IOUT = 250 mA
11.8 × VOUT
VIN = VEN = 5.5 V
VIN
0.4
V
-1
1
µA
Temp increasing
+160
Temp decreasing
+140
Undervoltage lockout hysteresis
VIN falling
µs
0
Reset
VIN rising
dB
1.2
Shutdown
Undervoltage lockout threshold
µVrms
2.25
°C
2.65
100
V
V
mV
Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater.
VDO is not measured for 1.8 V regulators since minimum VIN = 2.7 V.
For the adjustable version, this applies only after VIN is applied; then VEN transitions from high to low.
3
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049B – MAY 2004 – REVISED MARCH 2005
FUNCTIONAL BLOCK DIAGRAM —
FIXED VERSION
IN
FUNCTIONAL BLOCK DIAGRAM —
ADJUSTABLE VERSION
OUT1
IN
OUT1
30 µA
Current
Limit
Current
Limit
EN1
90 kΩ
FB1
EN1
Thermal
Shutdown
Thermal
Shutdown
OUT2
UVLO
OUT2
30 µA
Current
Limit
Current
Limit
UVLO
90 kΩ
FB2
EN2
EN2
250 kΩ
250 kΩ
NR
VREF
5 pF
1.225 V
TPS712xx
Fixed/Fixed
Quickstart
NR
VREF
5 pF
1.225 V
Quickstart
TPS712xx
Adj/Adj
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME
4
DESCRIPTION
DRC
IN
1
GND
5, Pad
Unregulated input supply. A small 0.1 µF capacitor should be connected from IN to GND.
OUT1
3
Output of the regulator. A small 2.2 µF ceramic capacitor is required from this pin to ground to assure
stability.
OUT2
4
Same as OUT1 but for LDO2.
EN1
10
Driving the enable pin (EN) high turns on LDO1. Driving this pin low puts LDO1 into shutdown mode,
reducing operating current. The enable pin should be connected to IN if not used.
Ground
EN2
8
Same as EN1 but controls LDO2.
FB1/NC
9
Feedback for CH1 adjustable version; no connection for non-adjustable CH1.
FB2/NC
7
Feedback for CH2 adjustable version; no connection for non-adjustable CH2.
NR
6
Noise reduction pin; connect an external bypass capacitor to reduce LDO output noise.
NC
2
No connection.
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049B – MAY 2004 – REVISED MARCH 2005
TYPICAL CHARACTERISTICS
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 µF, and CNR = 0.01 µF,
unless otherwise noted.
OUTPUT VOLTAGE vs INPUT VOLTAGE
OUTPUT VOLTAGE vs OUTPUT CURRENT
1.0
1.0
0.8
0.8
0.6
0.6
0.4
+25 C
0.2
VOUT (%)
VOUT (%)
0.4
0
−0.2
+125 C
−0.4
−0.6
0
−40C
−0.2
−0.4
−0.6
−40C
−0.8
+25C
0.2
−0.8
−1.0
+125 C
−1.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
50
100
150
200
250
VIN (V)
IOUT (mA)
Figure 1.
Figure 2.
OUTPUT VOLTAGE vs TEMPERATURE
DROPOUT VOLTAGE vs INPUT VOLTAGE
(ADJUSTABLE VERSION)
200
1.0
180
160
VOUT (%)
IOUT = 10 mA
0
IOUT = 125 mA
−0.5
IOUT = 250 mA
−1.0
Dropout Voltage (mV)
0.5
TJ = +125C
140
120
TJ = +25C
100
80
60
TJ = −40C
40
20
−1.5
−40 −25 −10
0
5
20
35
50
65
80
95
2.7
110 125
2.9
3.1
3.3
3.5
3.7
3.9 4.1
4.3
4.5 4.7
4.9
Junction Temperature (C)
VIN (V)
Figure 3.
Figure 4.
TPS71256
DROPOUT VOLTAGE vs OUTPUT CURRENT
TPS71256
DROPOUT VOLTAGE vs JUNCTION TEMPERATURE
200
250
200
150
Dropout Voltage (mV)
Dropout Voltage (mV)
TJ = +125C
100
TJ = −40 C
TJ = +25C
50
150
IOUT = 250 mA
100
50
0
0
50
100
150
IOUT (mA)
Figure 5.
200
250
0
−40 −25 −10
5
20
35
50
65
80
95
110 125
Junction Temperature (°C)
Figure 6.
5
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049B – MAY 2004 – REVISED MARCH 2005
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 µF, and CNR = 0.01 µF,
unless otherwise noted.
GROUND PIN CURRENT vs INPUT VOLTAGE
GROUND PIN CURRENT vs IOUT
400
400
375
375
350
+125 C
325
IGND (µA)
IGND (µA)
350
300
275
−40C
+25C
250
+125C
300
275
+25 C
−40C
250
225
225
200
200
2.7
3.2
3.7
4.2
4.7
5.2
5.7
0
50
100
150
200
250
VIN (V)
IOUT (mA)
Figure 7.
Figure 8.
GROUND PIN CURRENT vs JUNCTION TEMPERATURE
GROUND PIN CURRENT vs JUNCTION TEMPERATURE
(DISABLED)
500
400
VEN1 = VEN2 = 1.2V
375
VEN1 = VEN2 = 0.4V
450
VIN = 3.8 V
VIN = 3.8 V
400
350
350
325
IGND (nA)
IGND (µA)
325
300
275
300
250
200
150
250
100
225
50
200
0
−40 −25 −10
5
20
35
50
65
80
95
110 125
5
20
35
50
80
95
Figure 9.
Figure 10.
CURRENT LIMIT vs JUNCTION TEMPERATURE
TPS71256
LINE TRANSIENT RESPONSE
110 125
COUT1 = COUT2 = 10µF
VIN = 3.8 V
750
3.8 V
VIN
700
3.2 V
650
600
I OUT = 250 mA
10 mV/div
550
IOUT = 1 mA
500
10 mV/div
450
400
−40 −25 −10
5
20
35
50
65
80
95
110 125
100 µs/div
Junction Temperature (C)
Figure 11.
6
65
Junction Temperature (C)
800
Current Limit (mA)
−40 −25 −10
Junction Temperature (C)
Figure 12.
VOUT1
VOUT2
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049B – MAY 2004 – REVISED MARCH 2005
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 µF, and CNR = 0.01 µF,
unless otherwise noted.
TPS71256
LOAD TRANSIENT RESPONSE
AND VOUT2 CROSSTALK
TPS71256
CHANNEL-TO-CHANNEL ISOLATION vs FREQUENCY
60
COUT2 = 10 µF
VOUT2
COUT1 = 10 µF
100 mV/div
VOUT1
250 mA
10 mA
200 mA/div
50
Channel Isolation (dB)
2 mV/div
IOUT1
40
30
20
10
COUT1 = C OUT2 = 10 µF
IOUT1 = 0 mA to 500 mA Sinusoidal Load
IOUT2 = 25 mA
0
20 µs/div
0.1
1
10
100
1k
Frequency (Hz)
Figure 13.
Figure 14.
TPS71256
TURN-ON/OFF RESPONSE
AND VOUT2 CROSSTALK
TPS71229
POWER-UP/POWER-DOWN
CNR = 0.01 µF
I OUT1 = IOUT2 = 250 mA
COUT1 = COUT 2 = 10 µF
IOUT1 = I OUT2 = 250 mA
20 mV/div
VOUT2
VIN
1 V/div
CNR = 0.001 µF
VOUT1
VOUT2
VOUT1
1 V/div
VEN1
50 µs/div
TOTAL NOISE vs CNR
NOISE SPECTRAL DENSITY
COUT = 2.2 µF
350
COUT = 2.2 µF
IOUT = 250 mA
200
Total Noise (µVrms)
Figure 16.
COUT = 10 µF
IOUT = 250 mA
150
100
VOUT = 2.8 V
COUT = 2.2 µF
IOUT = 0 mA
COUT = 10 µF
IOUT = 0 mA
50
0
1
10
100
1k
10k
100k
Spectral Noise Density (nV/√Hz)
250
50 ms/div
Figure 15.
300
CNR = 0.1 µF
VOUT = 2.8 V
IOUT = 250 mA
250
200
IOUT = 1 mA
150
100
50
0
100
1k
10k
CNR (pF)
Frequency (Hz)
Figure 17.
Figure 18.
100k
7
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049B – MAY 2004 – REVISED MARCH 2005
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 µF, and CNR = 0.01 µF,
unless otherwise noted.
NOISE SPECTRAL DENSITY
COUT = 10 µF
CNR = 0.01 µF
VOUT = 2.8 V
300
Spectral Noise Density (nV/√Hz)
Spectral Noise Density (nV/√Hz)
350
NOISE SPECTRAL DENSITY vs CNR
180
250
200
IOUT = 1 mA
150
IOUT = 250 mA
100
50
0
100
1k
10k
140
0.001 µF
120
100
0.047 µF
80
0.01 µF
60
40
0.1 µF
20
0
100
100k
Figure 19.
Figure 20.
60
50
50
PSRR (dB)
PSRR (dB)
60
40
I OUT = 1 mA
100
40
30
I OUT = 250 mA
20
VOUT = 2.8 V
COUT = 2.2 µF
CNR = 0.01 µF
10
IOUT = 1 mA
70
IOUT = 250 mA
30
VOUT = 2.8 V
COUT = 10 µF
CNR = 0.01 µF
10
0
1k
10k
100k
1M
10M
10
100
1k
100k
Frequency (Hz)
Figure 21.
Figure 22.
PSRR (RIPPLE REJECTION) vs VIN - VOUT
80
70
f = 1 kHz
PSRR (dB)
60
50
f = 10 kHz
40
30
f = 100 kHz
VOUT = 2.8 V
IOUT = 250 mA
COUT = 10 µF
CNR = 0.01 µF
20
10
0
0.2
0.4
0.6
0.8
1.0
1.2
VIN − VOUT (V)
Figure 23.
8
10k
Frequency (Hz)
0
100k
PSRR (RIPPLE REJECTION) vs FREQUENCY
80
70
0
10k
Frequency (Hz)
PSRR (RIPPLE REJECTION) vs FREQUENCY
10
1k
Frequency (Hz)
80
20
COUT = 10 µF
IOUT = 250 mA
VOUT = 2.8 V
160
1.4
1.6
1.8
2.0
1M
10M
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049B – MAY 2004 – REVISED MARCH 2005
APPLICATION INFORMATION
The TPS712xx family of dual low-dropout (LDO)
regulators has been optimized for use in
noise-sensitive battery-operated equipment. The device features extremely low dropout, high PSRR,
ultralow output noise, and low quiescent current
(190 µA typical per channel). When both outputs are
disabled, the supply currents are reduced to less than
2µA. A typical application circuit is shown in Figure 24.
TPS712xx
VIN
IN
VOUT1
OUT1
2.2 µF
0.1 µF
EN1
VOUT2
OUT2
EN2
2.2 µF
NR
GND
0.01 µF
Figure 24. Typical Application Circuit
(fixed-voltage versions)
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
A 0.1 µF or larger ceramic input bypass capacitor,
connected between IN and GND and located close to
the TPS712xx, is required for stability. It improves
transient response, noise rejection, and ripple rejection. A higher-value input capacitor may be necessary
if large, fast-rise-time load transients are anticipated
and the device is located several inches from the
power source.
The TPS712xx requires an output capacitor connected between the outputs and GND to stabilize the
internal control loops. The minimum recommended
output capacitor is 2.2 µF. If an output voltage of
1.8 V or less is chosen, the minimum recommended
output capacitor is 4.7 µF. Any ceramic capacitor that
meets the minimum output capacitor requirements is
suitable. Capacitors with higher ESR may be used,
provided the ESR is less than 1Ω.
OUTPUT NOISE
The internal voltage reference is a key source of
noise in an LDO regulator. The TPS712xx has an NR
pin that is connected to the voltage reference through
a 250 kΩ internal resistor. The 250 kΩ internal
resistor, in conjunction with an external ceramic
bypass capacitor connected to the NR pin, creates a
low-pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. To
achieve a fast startup, the 250 kΩ internal resistor is
shorted for 400 µs after the device is enabled.
Because the primary noise source is the internal
voltage reference, the output noise will be greater for
higher output voltage versions. For the case where
no noise reduction capacitor is used, the typical noise
(µVrms) over 10 Hz to 100 kHz is 80 times the output
voltage. If a 0.01 µF capacitor is used from the NR
pin to ground, the noise (µVrms) drops to 11.8 times
the output voltage. For example, the TPS71256
exhibits only 33 µVrms of output voltage noise using
a 0.01 µF ceramic bypass capacitor and a 2.2 µF
ceramic output capacitor.
STARTUP CHARACTERISITCS
To minimize startup overshoot, the TPS712xx will
initially target an output voltage that is approximately
80% of the final value. To avoid a delayed startup
time, noise reduction capacitors of 0.01 µF or less
are recommended. Larger noise reduction capacitors
will cause the output to hold at 80% until the voltage
on the noise reduction capacitor exceeds 80% of the
bandgap voltage. The typical startup time with a
0.001 µF noise reduction capacitor is 60 µs. Once
one of the output voltages is present, the startup time
of the other output will not be affected by the noise
reduction capacitor.
9
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
www.ti.com
SBVS049B – MAY 2004 – REVISED MARCH 2005
PROGRAMMING THE TPS71202
ADJUSTABLE LDO REGULATOR
C1 The output voltage of the TPS71202 dual adjustable
regulator is programmed using an external resistor
divider, as shown in Figure 25. The output voltage is
calculated using Equation 1:
V OUT VREF 1 R1
R2
(1)
where VREF = 1.225 V (the internal reference voltage).
Resistors R2 and R4 should be chosen for approximately a 40 µA divider current. Lower value resistors
can be used for improved noise performance, but will
consume more power. Higher values should be
avoided because leakage current at FB increases the
output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider
current at 40 µA, and then calculate R1 using
Equation 2:
R1 VV
OUT
REF
1 R2
(2)
To improve the stability and noise performance of the
adjustable version, a small compensation capacitor
can be placed between OUT and FB.
(3 105) (R1 R2)
(R1 R2)
(pF)
(3)
The suggested value of this capacitor for several
resistor ratios is shown in Figure 25. If this capacitor
is not used (such as in a unity-gain configuration) or if
an output voltage ≤ 1.8 V is chosen, then the
minimum recommended output capacitor is 4.7 µF
instead of 2.2 µF.
DROPOUT VOLTAGE
The TPS712xx uses a PMOS pass transistor to
achieve extremely low dropout. When (VIN - VOUT) is
less than the dropout voltage (VDO), the PMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS, ON of the PMOS
pass element. Dropout voltages at lower currents can
be approximated by calculating the effective RDS, ON
of the pass element and multiplying that resistance by
the load current. RDS, ON of the pass element can be
obtained by dividing the dropout voltage by the rated
output current. For the TPS71256, the RDS, ON of the
pass element is 84 mΩ. The dropout voltage of the
TPS712xx will be less for higher output voltage
versions. This is because the PMOS pass element
will have lower on-resistance due to increased gate
drive.
For voltages ≤ 1.8 V, the value of this capacitor
should be 100 pF. For voltages > 1.8 V, the approximate value of this capacitor can be calculated as
Equation 3:
TPS71202
VIN
IN
VOUT1
OUT1
R1
EN1
C1
FB1
R2
0.1 µF
EN2
VOUT2
OUT2
R3
NR
0.01 µF
GND FB2
R4
C2
Output Voltage Programming Guide
2.2 µF
2.2 µF
VOUT
R1/R3
R2/R4
C1/C2
1.225 V
Short
Open
Open
1.5 V
7.15 kΩ
30.1 kΩ
100 pF
2.5 V
31.6 kΩ
30.1 kΩ
22 pF
3.0 V
43.2 kΩ
30.1 kΩ
15 pF
3.3 V
49.9 kΩ
30.1 kΩ
15 pF
4.75 V
86.6 kΩ
30.1 kΩ
15 pF
Figure 25. TPS71202 Adjustable LDO Regulator Programming
10
www.ti.com
TRANSIENT RESPONSE
As with any regulator, increasing the size of the
output capacitor will reduce over/undershoot magnitude but increase duration of the transient response.
In the adjustable version, the addition of a capacitor,
CFB, from the output to the feedback pin will also
improve stability and transient response. The transient response of the TPS712xx is enhanced with an
active pull-down that engages when the output is
over-voltaged. The active pull-down decreases the
output recovery time when the load is removed.
Figure 13 in the Typical Characteristics section shows
the output transient response.
SHUTDOWN
Both enable pins are active high and are compatible
with standard TTL-CMOS levels. The device is only
completely disabled when both EN1 and EN2 are
logic low. In this state, the LDO is completely off and
the ground pin current drops to approximately 100
nA. With one output disabled, the ground pin current
is slightly greater than half the nominal value. When
shutdown capability is not required, the enable pins
should be connected to the input supply.
TPS71202, TPS71219
TPS71229, TPS71247
TPS71256, TPS71257
SBVS049B – MAY 2004 – REVISED MARCH 2005
Depending on power dissipation, thermal resistance,
and ambient temperature, the thermal protection
circuit may cycle on and off. This limits the dissipation
of the regulator, protecting it from damage due to
overheating.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To
estimate the margin of safety in a complete design
(including heatsink), increase the ambient temperature until the thermal protection is triggered; use
worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient condition of your application. This produces a worst-case
junction temperature of +125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS712xx was
designed to protect against overload conditions. It
was not intended to replace proper heatsinking.
Continuously running the TPS712xx into thermal
shutdown will degrade device reliability.
POWER DISSIPATION
INTERNAL CURRENT LIMIT
The TPS712xx internal current limit helps protect the
regulator during fault conditions. During current limit,
the output will source a fixed amount of current that is
largely independent of the output voltage.
The TPS712xx PMOS-pass transistors have a built-in
back diode that conducts reverse current when the
input voltage drops below the output voltage (that is,
during power-down). Current is conducted from the
output to the input and is not internally limited. If
extended reverse voltage operation is anticipated,
external limiting may be appropriate.
THERMAL PROTECTION
Thermal protection disables both outputs when the
junction temperature of either channel rises to approximately +160°C, allowing the device to cool.
When the junction temperature cools to approximately +140°C, the output circuitry is again enabled.
The ability to remove heat from the die is different for
each package type, presenting different considerations in the PCB layout. The PCB area around the
device that is free of other components moves the
heat from the device to the ambient air. Performance
data for a JEDEC high-K board is shown in the
Dissipation Ratings table. Using heavier copper will
increase the effectiveness in removing heat from the
device. The addition of plated through-holes to
heat-dissipating layers will also improve the heat-sink
effectiveness.
Power dissipation depends on input voltage and load
conditions. Power dissipation is equal to the product
of the output current times the voltage drop across
the output pass element (VIN to VOUT):
P D (VIN VOUT) I OUT
(4)
Power dissipation can be minimized by using the
lowest possible input voltage necessary to assure the
required output voltage.
11
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS71202DRCR
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS71202DRCRG4
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS71202DRCT
ACTIVE
SON
DRC
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS71219DRCR
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS71219DRCRG4
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS71219DRCT
ACTIVE
SON
DRC
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS71229DRCR
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS71229DRCRG4
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS71229DRCT
ACTIVE
SON
DRC
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS71229DRCTG4
ACTIVE
SON
DRC
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS71247DRCR
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS71247DRCRG4
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS71247DRCT
ACTIVE
SON
DRC
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS71256DRCR
PREVIEW
SON
DRC
10
3000
TBD
Call TI
Call TI
TPS71256DRCT
PREVIEW
SON
DRC
10
250
TBD
Call TI
Call TI
TPS71257DRCR
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS71257DRCRG4
ACTIVE
SON
DRC
10
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS71257DRCT
ACTIVE
SON
DRC
10
250
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 2
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