PROCESS CP319 Central Power Transistor TM Semiconductor Corp. NPN - Silicon Power Transistor Chip PROCESS DETAILS Process EPITAXIAL PLANAR Die Size 87 x 87 MILS Die Thickness 9.0 MILS Base Bonding Pad Area 24 x 15 MILS Emitter Bonding Pad Area 38 x 16 MILS Top Side Metalization Al - 30,000Å Back Side Metalization Ti/Ni/Ag - 11,000Å GEOMETRY GROSS DIE PER 4 INCH WAFER 1,460 PRINCIPAL DEVICE TYPES CZTA44HC TIP47 TIP48 TIP50 BACKSIDE COLLECTOR 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R2 (21-September 2003) Central TM Semiconductor Corp. 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com PROCESS CP319 Typical Electrical Characteristics R2 (21-September 2003)