PROCESS CP707 Central Small Signal Transistor TM Semiconductor Corp. PNP - Darlington Transistor Chip PROCESS DETAILS Process EPITAXIAL PLANAR Die Size 27 x 27 MILS Die Thickness 9.0 MILS Base Bonding Pad Area 5.3 x 3.8 MILS Emitter Bonding Pad Area 5.3 x 6.5 MILS Top Side Metalization Al - 30,000Å Back Side Metalization Au - 18,000Å GEOMETRY GROSS DIE PER 4 INCH WAFER 15,440 PRINCIPAL DEVICE TYPES CMPTA63 CMPTA64 CXTA64 CZTA64 MPSA63 MPSA64 BACKSIDE COLLECTOR 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R3 (1-August 2002) Central TM Semiconductor Corp. 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com PROCESS CP707 Typical Electrical Characteristics R3 (1-August 2002)