PROCESS CP207 Central Small Signal Transistor TM Semiconductor Corp. NPN - Saturated Switch Transistor Chip PROCESS DETAILS Process EPITAXIAL PLANAR Die Size 9.0 x 14 MILS Die Thickness 8.0 MILS Base Bonding Pad Area 3.1 x 2.9 MILS Emitter Bonding Pad Area 3.1 x 2.9 MILS Top Side Metalization Al - 13,000Å Back Side Metalization Au - 6,000Å GEOMETRY GROSS DIE PER 4 INCH WAFER 93,430 PRINCIPAL DEVICE TYPES 2N2369A CMPT2369 BACKSIDE COLLECTOR 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R2 (1-August 2002) Central TM Semiconductor Corp. 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com PROCESS CP207 Typical Electrical Characteristics R2 (1-August 2002)