TI SN65HVD35DR

SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665 – SEPTEMBER 2005
3.3V FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS
FEATURES
•
•
•
•
•
•
•
•
•
1/8 Unit-Load Option Available (Up to 256
Nodes on the Bus)
Bus-Pin ESD Protection Exceeds 15 kV HBM
Optional Driver Output Transition Times for
Signaling Rates (1) of 1 Mbps, 5 Mbps and 25
Mbps
Low-Current Standby Mode: < 1 µA
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
5V Tolerant Inputs
Bus Idle, Open, and Short Circuit Failsafe
Meets or exceeds the requirements of ANSI
TIA/EIA-485-A and RS-422 Compatible
5-V Devices available, SN65HVD50-59
APPLICATIONS
•
•
•
•
Utility Meters
DTE/DCE Interfaces
Industrial, Process, and Building Automation
Point-of-Sale (POS) Terminals and Networks
DESCRIPTION
The SN65HVD3X devices are 3-state differential line
drivers and differential-input line receivers that
operate with 3.3-V power supply.
(1)
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
Each driver and receiver has separate input and
output pins for full-duplex bus communication
designs. They are designed for balanced
transmission lines and interoperation with ANSI
TIA/EIA-485A, TIA/EIA-422-B, ITU-T v.11 and ISO
8482:1993 standard-compliant devices.
The SN65HVD30, SN65HVD31, SN65HVD32,
SN65HVD36 and SN65HVD37 are fully enabled with
no external enabling pins. The SN65HVD36 and
SN65HVD37
implement
receiver
equalization
technology for improved performance in long distance
applications.
The SN65HVD33, SN65HVD34, SN65HVD35,
SN65HVD38, and SN65HVD39 have active-high
driver enables and active-low receiver enables. A
very low, less than 1 µA, standby current can be
achieved by disabling both the driver and receiver.
The SN65HVD38 and SN65HVD39 implement
receiver equalization technology for improved
performance in long distance applications.
All devices are characterized for operation from -40°C
to +85°C.
The SN65HVD36 and SN65HVD38 implement
receiver equalization technology for improved jitter
performance on differential bus applications with data
rates up to 20 Mbps at cable lengths up to 160
meters.
The SN65HVD37 and SN65HVD39 implement
receiver equalization technology for improved jitter
performance on differential bus applications with data
rates in the range of 1 to 5 Mbps at cable lengths up
to 1000 meters.
IMPROVED REPLACEMENT FOR:
Part Number
Replace with
xxx3491
SN65HVD33:
Better ESD protection (15kV vs 2kV or not specified) Higher Signaling
Rate (25Mbps vs 20Mbps) Fractional Unit Load (64 Nodes vs 32)
MAX3491E
SN65HVD33:
Higher Signaling Rate (25Mbps vs 12Mbps) Fractional Unit Load
(64 Nodes vs 32)
MAX3076E
SN65HVD33:
Higher Signaling Rate (25Mbps vs 16Mbps) Lower Standby Current
(1 µA vs 10 µA)
MAX3073E
SN65HVD34:
Higher Signaling Rate (5Mbps vs 500kbps) Lower Standby Current
(1 µA vs 10 µA)
MAX3070E
SN65HVD35:
Higher Signaling Rate (1Mbps vs 250kbps) Lower Standby Current
(1 µA vs 10 µA)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665 – SEPTEMBER 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
SN65HVD30, SN65HVD31, SN65HVD32, SN65HVD36,
SN65HVD37
SN65HVD33, SN65HVD34, SN65HVD35, SN65HVD38,
SN65HVD39
D PACKAGE (TOP VIEW)
VCC
R
D
GND
R
D
1
8
2
7
3
6
4
5
8
2
A
7
6
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
VCC
A
B
Z
Y
NC
NC - No internal connection
B
5
3
NC
R
RE
DE
D
GND
GND
A
B
Z
Y
Y
Z
AVAILABLE OPTIONS
2
SIGNALING
RATE
UNIT LOADS
RECEIVER
EQUALIZATION
ENABLES
BASE
PART NUMBER
SOIC MARKING
25 Mbps
1/2
No
No
SN65HVD30
PREVIEW
5 Mbps
1/8
No
No
SN65HVD31
PREVIEW
1 Mbps
1/8
No
No
SN65HVD32
PREVIEW
25 Mbps
1/2
No
Yes
SN65HVD33
65HVD33
5 Mbps
1/8
No
Yes
SN65HVD34
65HVD34
1 Mbps
1/8
No
Yes
SN65HVD35
65HVD35
25 Mbps
1/2
Yes
No
SN65HVD36
PREVIEW
5 Mbps
1/8
Yes
No
SN65HVD37
PREVIEW
25 Mbps
1/2
Yes
Yes
SN65HVD38
PREVIEW
5 Mbps
1/8
Yes
Yes
SN65HVD39
PREVIEW
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665 – SEPTEMBER 2005
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1) (2)
UNIT
VCC
Supply voltage range, VCC
–0.3 V to 6 V
Voltage range at any bus terminal (A, B, Y, Z)
–9 V to 14 V
Voltage input, transient pulse through 100 Ω. See Figure 12 (A, B, Y,
VI
Z) (3)
–50 to 50 V
Input voltage range (D, DE, RE)
-0.5 V to 7 V
Continuous total power dissipation
IO
(1)
(2)
(3)
Internally limited
Output current (receiver output only, R)
11 mA
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
This tests survivability only and the output state of the receiver is not specified.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range unless otherwise noted
PARAMETER
MIN
VCC
Supply voltage
VI or
VIC
Voltage at any bus terminal (separately or common mode)
1/tUI
Signaling rate
NOM
MAX
3.0
3.6
–7 (1)
12
SN65HVD30, SN65HVD33, SN65HVD36, SN65HVD38
25
SN65HVD31, SN65HVD34, SN65HVD37, SN65HVD39
5
SN65HVD32, SN65HVD35
VIH
High-level input voltage
D, DE, RE
2
VCC
VIL
Low-level input voltage
D, DE, RE
0
0.8
VID
Differential input voltage
–12
12
IOL
Low-level output current
TA
Ambient still-air temperature
(1)
Mbps
54
Ω
Differential load resistance
High-level output current
V
1
RL
IOH
UNIT
Driver
60
–60
Receiver
V
mA
–8
Driver
60
Receiver
8
–40
85
mA
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
ELECTROSTATIC DISCHARGE PROTECTION
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
Bus terminals and GND
Human body model (2)
All pins
±4
Charged-device-model (3)
All pins
±1
(1)
(2)
(3)
MAX
UNIT
±16
Human body model
kV
All typical values at 25°C with 3.3-V supply.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
3
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665 – SEPTEMBER 2005
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
VI(K)
TEST CONDITIONS
Input clamp voltage
|VOD(SS)|
II = –18 mA
Steady-state differential output voltage
IO = 0
2.5
RL = 54 Ω, See Figure 1
(RS-485)
1.5
2.0
RL = 100 Ω, See Figure 1 (2)
(RS-422)
2.0
2.3
Vtest = –7 V to 12 V,
See Figure 2
1.5
Change in magnitude of steady-state
RL = 54 Ω, See Figure 1
differential output voltage between states and Figure 2
VOD(RING)
Differential Output Voltage overshoot
and undershoot
VOC(PP)
Peak-to-peak
common-mode
output voltage
∆VOC(SS)
Steady-state common-mode
output voltage
Change in steady-state common-mode
output voltage
RL = 54 Ω, CL = 50 pF,
See Figure 5 and Figure 3
0.05 |VOD(SS)|
HVD33, HVD34,
HVD35, HVD38,
HVD39
IZ(S) or IY(S)
Short Circuit output Current
II
Input current
C(OD)
Differential output
capacitance
(1)
(2)
4
V
0.5
See Figure 4
0.25
1.6
2.3
–0.05
0.05
See Figure 4
VCC = 0 V, VZ or VY = –7 V,
Other input at 0 V
High-impedance state
output current
UNIT
0.2
VCC = 0 V, VZ or VY = 12 V,
Other input at 0 V
IZ(Z) or IY(Z)
MAX
VCC
–0.2
HVD30, HVD33,
HVD36, HVD38
HVD31, HVD34,
HVD37, HVD39,
HVD32, HVD35
TYP (1)
–1.5
∆|VOD(SS)|
VOC(SS)
MIN
VCC = 5 V or 0 V,
DE = 0 V
VZ or VY = 12 V
Other input
VCC = 5 V or 0 V, at 0 V
DE = 0 V
VZ or VY = –7 V
VZ or VY = –7 V
VZ or VY = 12 V
Other input
at 0 V
D, DE
VOD = 0.4 sin (4E6πt) + 0.5 V,
DE at 0 V
All typical values are at 25°C and with a 3.3-V supply.
VCC is 3.3 Vdc ± 5%
90
–10
90
µA
–10
–250
250
–250
250
0
100
16
mA
µA
pF
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665 – SEPTEMBER 2005
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
Propagation delay time,
low-to-high-level output
tPLH
TEST CONDITIONS
HVD30, HVD33, HVD36, HVD38
4
10
18
HVD31, HVD34, HVD37, HVD39
25
38
65
HVD32, HVD35
Propagation delay time,
high-to-low-level output
tPHL
Differential output signal
rise time
tr
Differential output signal fall
time
tf
120
175
305
HVD30, HVD33, HVD36, HVD38
4
9
18
HVD31, HVD34, HVD37, HVD39
25
38
65
HVD32, HVD35
120
175
305
HVD30, HVD33, HVD36, HVD38
2.5
5
12
20
37
60
HVD32, HVD35
120
185
300
HVD30, HVD33, HVD36, HVD38
2.5
5
12
HVD31, HVD34, HVD37, HVD39
20
35
60
120
180
300
HVD31, HVD34, HVD37, HVD39
RL = 54 Ω, CL = 50 pF,
See Figure 5
HVD32, HVD35
tsk(p)
tPZH1
Propagation delay time,
high-impedance-to-highlevel output
Propagation delay time,
high-level-to-highimpedance output
tPHZ
tPZL1
HVD30, HVD33, HVD36, HVD38
2
HVD31, HVD34, HVD37, HVD39
4
HVD32, HVD35
7
HVD33, HVD38
45
HVD34, HVD39
235
HVD35
HVD33, HVD38
HVD34, HVD39
tPZH2
tPZL2
RL = 110 Ω, RE at 0 V,
D = 3 V and S1 = Y, or
D = 0 V and S1 = Z
See Figure 6
HVD35
HVD33, HVD38
Propagation delay time,
high-impedance-to-low-level HVD34, HVD39
output
HVD35
HVD33, HVD38
Propagation delay time,
low-level-to-high-impedance HVD34, HVD39
output
HVD35
tPLZ
(1)
Pulse skew (|tPHL - tPLH|)
MIN TYP (1) MAX
UNIT
ns
ns
ns
ns
ns
ns
490
25
65
ns
165
35
RL = 110 Ω, RE at 0 V,
D = 3 V and S1 = Z, or
D = 0 V and S1 = Y
See Figure 7
190
ns
490
30
120
ns
290
Propagation delay time, standby-to-high-level output
RL = 110 Ω, RE at 3 V,
D = 3 V and S1 = Y, or
D = 0 V and S1 = Z
See Figure 6
4000
ns
Propagation delay time, standby-to-low-level output
RL = 110 Ω, RE at 3 V,
D = 3 V and S1 = Z, or
D = 0 V and S1 = Y
See Figure 7
4000
ns
All typical values are at 25°C and with a 3.3-V supply.
5
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665 – SEPTEMBER 2005
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
VIT+
Positive-going differential input
threshold voltage
IO = –8 mA
VIT-
Negative-going differential input
threshold voltage
IO = 8 mA
Vhys
Hysteresis voltage (VIT+ - VIT-)
VIK
Enable-input clamp voltage
Output voltage
IO(Z)
High-impedance-state output
current
HVD30, HVD33,
HVD36, HVD38
50
II = –18 mA
VO = 0 or VCC, RE at VCC
V
2.4
0.4
–1
1
VA or VB = 12 V
0.05
0.10
VA or VB = 12 V, VCC = 0 V
0.06
0.10
VA or VB = -7 V
Other input
at 0V
–0.10
–0.04
–0.10
–0.03
VA or VB = 12 V
0.20
0.35
VA or VB = 12 V, VCC = 0 V
0.24
0.40
VA or VB = -7 V
Other input
at 0 V
VA or VB = -7 V, VCC = 0 V
Input current, RE
VIH = 0.8 V or 2 V
CID
Differential input capacitance
VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
–0.35
–0.18
–0.25
–0.13
–60
HVD34, HVD35
HVD38, HVD39
ICC
Supply current
HVD33, HVD34,
HVD35, HVD38,
HVD39
15
HVD38
RE at VCC, D at VCC, DE at 0 V,
No load (Receiver disabled and
driver disabled)
6
mA
2.2
mA
3.8
0.022
1
µA
2.1
RE at 0 V, D at 0 V or VCC, DE at VCC,
No load (Receiver enabled and
driver enabled)
6.5
3.5
HVD33
1.8
RE at VCC, D at 0 V or VCC, DE at VCC
No load (Receiver disabled and
driver enabled)
HVD39
(1)
mA
1.8
RE at 0 V, D at 0 V or VCC, DE at 0 V,
No load (Receiver enabled and
driver disabled)
8.0
HVD38
mA
7.9
HVD39
HVD34, HVD35
µA
pF
6.4
D at 0 V or VCC and No Load
HVD33
HVD34, HVD35
V
µA
HVD36, HVD37
HVD33
mV
–1.5
IIH
HVD30, HVD31,
HVD32
UNIT
V
VA or VB = -7 V, VCC = 0 V
Bus input
current
MAX
–0.20
VID = –200 mV, IO = 8 mA, See Figure 8
HVD31, HVD32,
HVD34, HVD35,
HVD37, HVD39
IA or IB
TYP (1)
–0.02
VID = 200 mV, IO = –8 mA, See Figure 8
VO
MIN
All typical values are at 25°C and with a 3.3-V supply.
6.2
2.5
7.0
mA
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
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SLLS665 – SEPTEMBER 2005
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
TYP (1)
MAX
HVD30, HVD33, HVD36, HVD38
26
45
HVD31, HVD32, HVD34, HVD35,
HVD37, HVD39
47
70
HVD30, HVD33, HVD36, HVD38
29
45
49
70
PARAMETER
tPLH
Propagation delay time,
low-to-high-level output
tPHL
Propagation delay time,
high-to-low-level output
tsk(p)
Pulse skew (|tPHL - tPLH|)
TEST CONDITIONS
HVD31, HVD32, HVD34, HVD35,
HVD37, HVD39
HVD30, HVD33, HVD36, HVD37,
HVD38, HVD39
MIN
VID = -1.5 V to 1.5 V,
CL = 15 pF,
See Figure 9
7
HVD31, HVD34, HVD32, HVD35
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Output disable time from high level
tPZH1
Output enable time to high level
tPZH2
Propagation delay time, standby-to-high-level output
tPLZ
Output disable time from low level
tPZL1
Output enable time to low level
tPZL2
Propagation delay time, standby-to-low-level output
(1)
UNIT
10
5
ns
6
DE at 3 V
20
CL = 15 pF
See Figure 10
20
DE at 0 V
DE at 3 V
4000
20
CL = 15 pF
See Figure 11
20
DE at 0 V
4000
All typical values are at 25°C and with a 3.3-V supply
RECEIVER EQUALIZATION CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
DEVICE
0m
100 m
25 Mbps
150 m
200 m
200 m
tj(pp)
Peak-to-peak
eye-pattern
jitter
Pseudo-random NRZ
code with a bit pattern
length o 216-1, Belden
3105A cable
10 Mbps
300 m
5 Mbps
3 Mbps
1 Mbps
(1)
(2)
250 m
500 m
500 m
1000 m
MIN
TYP (1)
HVD36, HVD38
PREVIEW
HVD33 (2)
PREVIEW
HVD36, HVD38
PREVIEW
HVD33 (2)
PREVIEW
HVD36, HVD38
PREVIEW
HVD33 (2)
PREVIEW
HVD36, HVD38
PREVIEW
HVD33 (2)
PREVIEW
HVD36, HVD38
PREVIEW
HVD33 (2)
PREVIEW
HVD36, HVD38
PREVIEW
HVD33 (2)
PREVIEW
HVD36, HVD38
PREVIEW
HVD34 (2)
PREVIEW
HVD37, HVD39
PREVIEW
HVD33 (2)
PREVIEW
HVD34 (2)
PREVIEW
HVD36, HVD38
PREVIEW
HVD37, HVD39
PREVIEW
HVD34 (2)
PREVIEW
HVD37, HVD39
PREVIEW
MAX
UNIT
ns
All typical values are at VCC = 5 V, and temperature = 25°C.
The HVD33 and the HVD34 do not have receiver equalization but are specified for comparison.
7
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665 – SEPTEMBER 2005
DEVICE POWER DISSIPATION - PD
8
TEST CONDITIONS
DEVICE
RL = 60 , CL = 50 pF, Input to D a 50% duty
cycle square wave at indicated signaling rate
TA = 85°C
RL = 60 , CL = 50 pF, DE at VCC, RE at 0 V,
Input to D a 50% duty cycle square wave at
indicated signaling rate TA = 85°C
MIN
TYP
MAX
UNIT
HVD30, HVD36 (25 Mbps)
197
mW
HVD31, HVD37 (5 Mbps)
213
HVD32 (1 Mbps)
193
HVD33, HVD38 (25 Mbps)
197
HVD34, HVD39 (5 Mbps)
193
HVD35 (1 Mbps)
248
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
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SLLS665 – SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION
VCC
DE
II
IY
Y
VOD
0 or 3 V
Z
RL
IZ
VI
VZ
VY
Figure 1. Driver VOD Test Circuit and Voltage and Current Definitions
375 Ω ±1%
VCC
DE
D
Y
VOD
0 or 3 V
60 Ω ±1%
+
_ −7 V < V(test) < 12 V
Z
375 Ω ±1%
Figure 2. Driver VOD With Common-Mode Loading Test Circuit
VOD(SS)
VOD(RING)
0 V Differential
VOD(RING)
-VOD(SS)
Figure 3. VOD(RING) Waveform and Definitions
VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from
theVOD(H) and VOD(L) steady state values.
VCC
DE
Input
D
27 Ω ± 1%
Y
Y
VY
Z
VZ
VOC(PP)
Z
27 Ω ± 1%
CL = 50 pF ±20%
VOC
∆VOC(SS)
VOC
CL Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,t r <6ns, t f <6ns, ZO = 50 Ω
Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
9
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
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SLLS665 – SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Y
»
W
Z
W
»
W
Figure 5. Driver Switching Test Circuit and Voltage Waveforms
D
3V
0V
3V
S1
Y
Z
Y
S1
D
VO
1.5 V
1.5 V
VI
0.5 V
t PZH(1 & 2)
Z
0V
V OH
DE
Input
Generator
CL = 50 pF
±20%
50 W
VI
RL = 110 W
±1%
VO
2.3 V
~0V
tPHZ
Generator: PRR = 500kHz, 50% Duty Cycle, t r<6 ns, t f < 6ns, Z 0 = 50 W
CL Includes Fixture and Instrumentation Capacitance
Figure 6. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
D
3V
0V
VCC
S1
Z
Y
Y
D
VI
3V
VI
S1
1.5 V
1.5 V
VO
DE
Input
Generator
RL = 110 Ω
± 1%
0V
Z
t PZL(1&2)
t PLZ
VCC
CL = 50 pF ±20%
50 Ω
0.5 V
CL Includes Fixture
and Instrumentation
Capacitance
VO
2.3 V
VOL
Generator: PRR = 500 kHz, 50% Duty Cycle, t r <6 ns, t f <6 ns, Zo = 50 Ω
Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
IA
VA
VA + VB
2
VIC
A
R
VID
IO
B
VB
IB
RE
II
VO
VI
Figure 8. Receiver Voltage and Current Definitions
10
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
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SLLS665 – SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
A
VI
50 Ω
1.5 V
0V
3V
VO
R
Input
Generator
1.5 V
VI
B
0V
CL = 15 pF
±20%
RE
1.5 V
t PHL
t PLH
VO
CL Includes Fixture and Instrumentation Capacitance
1.5 V
10%
Generator: PRR = 500 kHz, 50% Duty Cycle, t r <6 ns, t f <6 ns, Zo = 50 Ω
VOH
90% 90%
tr
1.5 V
10% V
OL
tf
Figure 9. Receiver Switching Test Circuit and Voltage Waveforms
V CC
A
1.5 V
R
B
0V
VI
3V
A
S1
VI
C L = 15 pF
±20%
RE
Input
Generator
VO
1 k W ±1%
1.5V
1.5V
B
0V
t PHZ
t PZH(1 & 2)
V OH
50 W
1.5 V
VO
C L Includes Fixture and
Instrumentation Capacitance
0.5V
~0 V
Generator: PRR = 500kHz, 50%, Duty Cycle, t r<6 ns, t f < 6ns, Z 0 = 50 W
Figure 10. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
0V
V CC
A
R
1.5 V
B
RE
Input
V
Generator I
V O 1 k W ±1%
S1
C L = 15 pF
±20%
3V
A
VI
1.5V
1.5V
0V
B
tPZL(1 & 2)
50 W
C L Includes Fixture
and Instrumentation
Capacitance
tPLZ
V CC
1.5 V
VO
0.5V
V OL
Generator: PRR = 500 kHz, 50% Duty Cycle, t r<6 ns, t f < 6ns, Z 0 = 50 W
Figure 11. Receiver Enable Time From Standby (Driver Disabled)
0 V or 3 V
DE
A
Y
D
R
Z
100 W
±1%
+
-
Pulse Generator
15 ms duration
1% Duty Cycle
tr, tf £ 100 ns
100 W
±1%
B
RE
0 V or 3 V
+
-
Figure 12. Test Circuit, Transient Over Voltage Test
11
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665 – SEPTEMBER 2005
DEVICE INFORMATION
LOW-POWER SHUTDOWN MODE
When both the driver and receiver are disabled (DE low and RE high) the device is in shutdown mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter shutdown mode. This guards against
inadvertently entering shutdown mode during driver/receiver enabling. Only when the enable inputs are held in
this state for 300 ns or more, the device is assured to be in shutdown mode. In this low-power shutdown mode,
most internal circuitry is powered down, and the supply current is typically less than 1 nA. When either the driver
or the receiver is re-enabled, the internal circuitry becomes active.
12
A
2
R
11
B
RE
3
Low-Power
Shutdown
DE
4
9
Y
5
D
10
Z
Figure 13. Low-Power Shutdown Logic Diagram
If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after
the enable times given by tPZH2 and tPZL2 in the driver switching characteristics. If the D input is open when the
driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe feature.
If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the
bus inputs (A and B) after the enable times given by tPZH2 and tPZL2 in the receiver switching characteristics. If
there is no valid state on the bus the receiver responds as described in the failsafe operation section.
If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state
of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the
active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver
outputs are valid.
12
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665 – SEPTEMBER 2005
DEVICE INFORMATION (continued)
FUNCTION TABLES
SN65HVD33, SN65HVD34, SN65HVD35, SN65HVD38,
SN65HVD39 DRIVER
INPUTS
OUTPUTS
D
DE
Y
Z
H
H
H
L
H
L
H
L
X
L or open
Z
Z
Open
H
L
H
SN65HVD33, SN65HVD34, SN65HVD35, SN65HVD38,
SN65HVD39 RECEIVER
DIFFERENTIAL INPUTS
VID = VA - VB
ENABLE
RE
OUTPUT
R
VID ≤ –0.2 V
L
L
–0.2 V < VID < –0.02 V
L
?
–0.02 V ≤ VID
L
H
X
H or open
Z
Open Circuit
L
H
Idle circuit
L
H
Short Circuit, VA=VB
L
H
SN65HVD30, SN65HVD31, SN65HVD32, SN65HVD36,
SN65HVD37 DRIVER
OUTPUTS
INPUT
D
Y
Z
H
H
L
L
L
H
Open
L
H
SN65HVD30, SN65HVD31, SN65HVD32, SN65HVD36,
SN65HVD37 RECEIVER
DIFFERENTIAL INPUTS
VID = VA - VB
OUTPUT
R
VID ≤ –0.2 V
L
–0.2 V < VID < –0.02 V
?
–0.02 V ≤ VID
H
Open Circuit
H
Idle circuit
H
Short Circuit, VA=VB
H
13
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665 – SEPTEMBER 2005
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and DE Input
RE Input
VCC
VCC
130 kW
Input
470 W
Input
9V
470 W
9V
125 kW
A Input
B Input
VCC
VCC
R1
22 V
R1
22 V
R3
R3
Input
Input
22 V
R2
22 V
R2
R Output
Y and Z Outputs
VCC
VCC
16 V
5W
Output
16 V
SN65HVD30, SN65HVD33, SN65HVD36, SN65HVD38
9V
R1/R2
R3
9 kΩ
45 kΩ
SN65HVD31, SN65HVD32, SN65HVD34, SN65HVD35 SN65HVD37, 36 kΩ
SN65HVD38, SN65HVD39
14
Output
180 kΩ
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665 – SEPTEMBER 2005
TYPICAL CHARACTERISTICS
HD30, HD33 RMS Supply Current
vs
Signaling Rate
HD31, HD34 RMS Supply Current
vs
Signaling Rate
60
55
TA =25°C RL = 54 W
RE = VCC CL = 50 pF
DE = VCC
55
ICC - RMS Supply Current - mA
50
45
VCC = 3.3 V
40
35
50
VCC = 3.3 V
45
40
35
30
30
0
5
10
15
20
0
25
1
2
3
Signaling Rate - Mbps
Signaling Rate - Mbps
Figure 14.
Figure 15.
4
5
HD32, HD35 RMS Supply Current
vs
Signaling Rate
60
TA =25°C RL = 54 W
RE = VCC CL = 50 pF
DE = VCC
55
ICC - RMS Supply Current - mA
ICC - RMS Supply Current - mA
TA =25°C RL = 54 W
RE = VCC CL = 50 pF
DE = VCC
50
VCC = 3.3 V
45
40
35
30
0
0.2
0.4
0.6
0.8
1
Signaling Rate - Mbps
Figure 16.
15
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665 – SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
HVD30, HVD33
Bus Input Current
vs
Input Voltage
HVD31, HVD32, HVD34, HVD35
Bus Input Current
vs
Input Voltage
250
60
TA = 25°C
RE = 0 V
DE = 0 V
200
TA = 25°C
RE = 0 V
DE = 0 V
40
100
II - Bus Input Current - uA
II - Bus Input Current - uA
150
50
VCC = 3.3 V
0
-50
-100
20
0
VCC = 3.3 V
-20
-40
-150
-200
-60
-7
-4
-1
2
5
8
11
-7
14
-4
5
8
Figure 17.
Figure 18.
Driver Low-Level Output Current
vs
Low-Level Output Voltage
Driver High-Level Output Current
vs
High-Level Output Voltage
11
14
0.01
0.14
VCC = 3.3 V
DE = VCC
D=0V
0.12
VCC = 3.3 V
DE = VCC
D=0V
-0.01
0.1
IOH - High-level Output Current - A
IOL - Low-level Output Current - A
2
VI - Bus Input Voltage - V
VI - Bus Input Voltage - V
0.08
0.06
0.04
0.02
0
-0.02
-0.03
-0.05
-0.07
-0.09
-0.11
-0.13
0
0.5
1
1.5
2
2.5
VOL - Low-Level Output Voltage - V
Figure 19.
16
-1
3
3.5
0
0.5
1
1.5
2
2.5
VOH - High-Level Output Voltage - V
Figure 20.
3
3.5
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665 – SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
Driver Differential Output Voltage
vs
Free-Air Temperature
Driver Output Current
vs
Supply Voltage
2.2
40
TA = 25°C
RL = 54 W
D = VCC
DE = VCC
35
IO - Driver Output Current - mA
VOD - Driver Differential Voltage - V
VCC = 3.3 V
DE = VCC
D = VCC
2.1
2.0
1.9
30
VCC = 3.3 V
25
20
15
10
5
0
1.8
-40
-15
10
35
60
85
0
0.5
1
1.5
2
2.5
TA - Free Air Temperature - °C
VCC Supply Voltage - V
Figure 21.
Figure 22.
3
3.5
17
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN65HVD33D
PREVIEW
SOIC
D
14
50
TBD
Call TI
Call TI
SN65HVD33DR
PREVIEW
SOIC
D
14
2500
TBD
Call TI
Call TI
SN65HVD34D
PREVIEW
SOIC
D
14
50
TBD
Call TI
Call TI
SN65HVD34DR
PREVIEW
SOIC
D
14
50
TBD
Call TI
Call TI
SN65HVD35D
PREVIEW
SOIC
D
14
50
TBD
Call TI
Call TI
SN65HVD35DR
PREVIEW
SOIC
D
14
2500
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65HVD33D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD33DG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD33DR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD33DRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD34D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD34DG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD34DR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD34DRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD35D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD35DG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD35DR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD35DRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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