TI SN75LBC176AD

SLLS376C− MAY 2000 − REVISED DECEMBER 2000
D High-Speed Low-Power LinBiCMOS
Circuitry Designed for Signaling Rates† Up
D
D
D
D
D
D
D
D
D
D
D
D
D
to 30 Mbps
Bus-Pin ESD Protection Exceeds 12 kV
HBM
Compatible With ANSI Standard
TIA/EIA-485-A and ISO 8482:1987(E)
Low Skew
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
Very Low Disabled Supply-Current
Requirements . . . 700 µA Maximum
Common Mode Voltage Range of −7 V
to 12 V
Thermal-Shutdown Protection
Driver Positive and Negative Current
Limiting
Open-Circuit Fail-Safe Receiver Design
Receiver Input Sensitivity . . . ± 200 mV Max
Receiver Input Hysteresis . . . 50 mV Typ
Glitch-Free Power-Up and Power-Down
Protection
Available in Q-Temp Automotive
High Reliability Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
description
The SN65LBC176A, SN65LBC176AQ, and
SN75LBC176A differential bus transceivers are
monolithic, integrated circuits designed for
bidirectional data communication on multipoint
bus-transmission lines. They are designed for
balanced transmission lines and are compatible
with ANSI standard TIA/EIA-485-A and ISO 8482.
The A version offers improved switching performance over its predecessors without sacrificing
significantly more power.
SN65LBC176AQD (Marked as B176AQ)
SN65LBC176AD (Marked as BL176A)
SN65LBC176AP (Marked as 65LBC176A)
SN75LBC176AD (Marked as LB176A)
SN75LBC176AP (Marked as 75LBC176A)
(TOP VIEW)
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
logic diagram (positive logic)
DE
3
4
D
RE
R
2
6
1
7
A
Bus
B
Function Tables
DRIVER
INPUT
D
H
L
X
Open
ENABLE
DE
H
H
L
H
OUTPUTS
A
B
H
L
L
H
Z
Z
H
L
RECEIVER
DIFFERENTIAL INPUTS
VA −VB
VID ≥ 0.2 V
−0.2 V < VID < 0.2 V
VID ≤ − 0.2 V
X
Open
H = high level,
X = irrelevant,
ENABLE
RE
L
L
L
H
L
OUTPUT
R
H
?
L
Z
H
L = low level, ? = indeterminate,
Z = high impedance (off)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† Signaling rate by TIA/EIA-485-A definition restrict transition times to 30% of the bit length, and much higher signaling rates may be achieved
without this requirement as displayed in the TYPICAL CHARACTERISTICS of this device.
LinBiCMOS and LinASIC are trademarks of Texas Instruments.
Copyright  2000, Texas Instruments Incorporated
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLLS376C− MAY 2000 − REVISED DECEMBER 2000
description (continued)
The SN65LBC176A, SN65LBC176AQ, and SN75LBC176A combine a 3-state, differential line driver and a
differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver
have active-high and active-low enables, respectively, which can externally connect together to function as a
direction control. The driver differential outputs and the receiver differential inputs connect internally to form a
differential input/output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver
is disabled or VCC = 0. This port features wide positive and negative common-mode voltage ranges, making
the device suitable for party-line applications. Very low device supply current can be achieved by disabling the
driver and the receiver.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(D)
PLASTIC
DUAL-IN-LINE
0°C to 70°C
SN75LBC176AD
SN75LBC176AP
−40°C to 85°C
SN65LBC176AD
SN65LBC176AP
−40°C to 125°C
SN65LBC176AQD
—
schematics of inputs and outputs
A Input
VCC
D, DE, and RE Inputs
VCC
16 V
100 kΩ
100 kΩ
4 kΩ
18 kΩ
1 kΩ
Input
Input
16 V
8V
4 kΩ
B Input
R Output
VCC
VCC
16 V
40 Ω
4 kΩ
Output
18 kΩ
Input
100 kΩ
8V
2
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16 V
• DALLAS, TEXAS 75265
4 kΩ
SLLS376C− MAY 2000 − REVISED DECEMBER 2000
absolute maximum ratings†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Voltage range at any bus terminal (A or B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 V to 15 V
Input voltage, VI (D, DE, R, or RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.5 V
Electrostatic discharge: Bus terminals and GND, Class 3, A: (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 12 kV
Bus terminals and GND, Class 3, B: (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 400 V
All terminals, Class 3, A: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV
All terminals, Class 3, B: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 V
Continuous total power dissipation (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.
2. The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature.
3. Tested in accordance with MIL−STD−883C, Method 3015.7
PACKAGE
TA ≤ 25°C
POWER RATING
DISSIPATION RATING TABLE
DERATING FACTOR‡
TA = 70°C
POWER RATING
ABOVE TA = 25°C
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
725 mW
5.8 mW/°C
464 mW
377 mW
145 mW
P
1000 mW
8.0 mW/°C
640 mW
520 mW
—
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
12
Voltage at any bus terminal (separately or common mode), VI or VIC
High-level input voltage, VIH (output recessive)
D, DE, and RE
2
Low-level input voltage, VIL (output dominant)
D, DE, and RE
0
−12§
Differential input voltage, VID (see Note 4)
Driver
High-level output current, IOH
Receiver
Operating free-air temperature, TA
VCC
0.8
V
12
V
V
−60
mA
−8
Driver
Low-level output current, IOL
V
−7
60
Receiver
8
SN65LBC176AQ
−40
125
SN65LBC176A
−40
85
SN75LBC176A
0
70
mA
°C
C
§ The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
NOTE 4: Differential input /output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
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3
SLLS376C− MAY 2000 − REVISED DECEMBER 2000
driver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
VIK
Input clamp voltage
TEST CONDITIONS
II = − 18 mA
SN65LBC176AQ
IO = 0
| VOD |
Differential output voltage
TYP†
−1.5
−0.8
1.5
4
SN65LBC176A,
SN75LBC176A
See Figure 1
Vtest = − 7 V to 12 V, See Figure 2
6
1.5
3
SN75LBC176A
1.1
1.5
3
SN65LBC176AQ
0.9
1.5
6
SN65LBC176A
1
1.5
3
V
SN75LBC176A
1.1
1.5
3
V
0.2
V
∆ VOC(SS)
Change in steady-state
common-mode output
voltage†
IOZ
High-impedance output
current
See receiver input currents
IIH
High-level enable input
current
VI = 2 V
−100
VI = 0.8 V
−7 V ≤ VO ≤ 12 V
−100
ICC
Supply current
See Figures 1 and 2
VI = 0 or VCC,
No load
V
1.5
Steady-state common-mode
output voltage
Short-circuit output current
6
1
VOC(SS)
Low-level enable input current
V
0.9
Change in magnitude of
differential output voltage
−0.2
See Figure 1
UNIT
SN65LBC176A
∆| VOD |
IIL
IOS
MAX
4
SN65LBC176AQ
RL = 54 Ω,
MIN
SN65LBC176AQ
1.8
2.4
3
SN65LBC176A,
SN75LBC176A
1.8
2.4
2.8
SN65LBC176AQ
−0.2
0.2
SN65LBC176A,
SN75LBC176A
−0.1
0.1
−250
V
V
V
µA
µA
±70
250
Receiver disabled and driver enabled
5
9
Receiver disabled and driver disabled
0.4
0.7
Receiver enabled and driver enabled
8.5
15
mA
mA
† All typical values are at VCC = 5 V, TA = 25°C.
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
TEST
CONDITIONS
PARAMETER
SN65LBC176A
SN75LBC176A
SN65LBC176AQ
MIN
TYP†
UNIT
MAX
MIN
TYP†
MAX
tPLH
tPHL
Propagation delay time, low-to-high-level output
2
12
2
6
12
ns
Propagation delay time, high-to-low-level output
2
12
2
6
12
ns
tsk(p)
tr
Pulse skew ( | tPLH − tPHL | )
0.3
1
ns
tf
Differential output signal fall time
tPZH
Propagation delay time, high-impedance-to-highlevel output
RL = 110 Ω,
See Figure 4
tPZL
Propagation delay time, high-impedance-to-lowlevel output
tPHZ
tPLZ
Differential output signal rise time
RL = 54 Ω,
CL = 50 pF,
See Figure 3
2
1.2
11
4
7.5
11
ns
1.2
11
4
7.5
11
ns
22
12
22
ns
RL = 110 Ω,
See Figure 5
25
12
22
ns
Propagation delay time, high-level-to-highimpedance output
RL = 110 Ω,
See Figure 4
22
12
22
ns
Propagation delay time, low-level-to-highimpedance output
RL = 110 Ω,
See Figure 5
22
12
22
ns
† All typical values are at VCC = 5 V, TA = 25°C.
4
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SLLS376C− MAY 2000 − REVISED DECEMBER 2000
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
VIT +
Positive-going input threshold
voltage
VIT −
Negative-going input threshold
voltage
TEST CONDITIONS
VOH
VOL
High-level output voltage
II = − 18 mA
VID = 200 mV,
Low-level output voltage
VID = 200 mV,
High-impedance-state output current
II
Bus input current
IIH
IIL
High-level enable-input current
ICC
Supply current
Low-level enable-input current
MAX
0.2
−0.2
IO = 8 mA
Hysteresis voltage (VIT + − VIT −)
IOZ
TYP†
IO = −8 mA
Vhys
VIK
Enable-input clamp voltage
MIN
VO = 0 to VCC
VIH = 12 V,
VIH = 12 V,
VCC = 5 V
VCC = 0
VIH = − 7 V,
VIH = − 7 V,
VCC = 5 V
VCC = 0
See Figure 6
−0.8
V
4
4.9
V
0.1
0.8
SN65LBC176AQ
−10
10
SN65LBC176A,
SN75LBC176A
−1
1
VIH = 2 V
VIL = 0.8 V
VI = 0 or VCC,
No load
mV
−1.5
See Figure 6
Other input at 0 V
V
V
50
IOH = − 8 mA,
IOL = 8 mA,
UNIT
0.4
1
0.5
1
−0.8
−0.4
−0.8
−0.3
V
µA
mA
−100
µA
−100
µA
Receiver enabled and driver disabled
4
7
Receiver disabled and driver disabled
0.4
0.7
Receiver enabled and driver enabled
8.5
15
mA
† All typical values are at VCC = 5 V, TA = 25°C.
receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
SN65LBC176A
SN75LBC176A
SN65LBC176AQ
TYP†
UNIT
MAX
MIN
TYP†
MAX
7
30
7
13
20
ns
7
30
7
MIN
tPLH
tPHL
Propagation delay time, output↑
13
20
ns
tsk(p)
tr
Pulse skew ( | tPHL − tPLH | )
6
0.5
1.5
ns
Rise time, output
5
2.1
3.3
ns
tf
Fall time, output
5
2.1
3.3
ns
tPZH
tPZL
Output enable time to high level
50
30
45
ns
50
30
45
ns
60
20
40
ns
40
20
40
ns
Propagation delay time, output↓
Output enable time to low level
tPHZ
Output disable time from high level
tPLZ
Output disable time from low level
† All typical values are at VCC = 5 V, TA = 25°C.
VID = − 1.5 V to 1.5 V,
See Figure 7
See Figure 7
CL = 10 pF,
See Figure 8
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5
SLLS376C− MAY 2000 − REVISED DECEMBER 2000
PARAMETER MEASUREMENT INFORMATION
Vtest
R1
375 Ω
Y
27 Ω
VOD
0 or 3 V
D
RL = 60 Ω
0 V or 3 V
VOD
27 Ω VOC
Z
Figure 1. Driver VOD and VOC
R2
375 Ω
−7 V < Vtest < 12 V
Vtest
Figure 2. Driver VOD3
3V
Input
Generator
(see Note A)
50 Ω
RL = 54 Ω
CL = 50 pF
(see Note B)
1.5 V
1.5 V
0V
tPLH
VO
Output
TEST CIRCUIT
tPHL
90%
50%
≈ 1.5 V
10%
≈ − 1.5 V
tr
tf
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 3. Driver Test Circuit and Voltage Waveforms
Output
3V
S1
Input
1.5 V
1.5 V
3V
Generator
(see Note A)
50 Ω
CL = 50 pF
(see Note B)
tPZH
RL = 110 Ω
0V
0.5 V
VOH
Output
TEST CIRCUIT
2.3 V
tPHZ
Voff ≈ 0 V
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 4. Driver Test Circuit and Voltage Waveforms
6
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SLLS376C− MAY 2000 − REVISED DECEMBER 2000
PARAMETER MEASUREMENT INFORMATION
5V
S1
0V
Generator
(see Note A)
3V
Input
RL = 110 Ω
1.5 V
1.5 V
0V
tPZL
Output
tPLZ
CL = 50 pF
(see Note B)
50 Ω
5V
0.5 V
2.3 V
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 5. Driver Test Circuit and Voltage Waveforms
IO
VID
VO
Figure 6. Receiver VOH and VOL
3V
Input
Generator
(see Note A)
1.5 V
1.5 V
Output
50 Ω
1.5 V
CL = 10 pF
(see Note B)
0V
Output
0V
tPHL
tPLH
1.3 V
10%
1.3 V
tR
TEST CIRCUIT
VOH
90%
VOL
tF
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 7. Receiver Test Circuit and Voltage Waveforms
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7
SLLS376C− MAY 2000 − REVISED DECEMBER 2000
PARAMETER MEASUREMENT INFORMATION
S1
1.5 V
2 kΩ
−1.5 V
S2
5V
CL = 10 pF
(see Note B)
Generator
(see Note A)
5 kΩ
50 Ω
S3
TEST CIRCUIT
Input
1.5 V
3V
S1 to 1.5 V
S2 Open
S3 Closed
0V
Input
1.5 V
tPZH
3V
S1 to −1.5 V
S2 Closed
S3 Open
0V
tPZL
VOH
≈ 4.5 V
1.5 V
Output
Output
1.5 V
0V
VOL
1.5 V
Input
3V
S1 to 1.5 V
S2 Closed
S3 Closed
0V
Input
tPHZ
3V
S1 to −1.5 V
S2 Closed
S3 Closed
0V
1.5 V
tPLZ
≈ 1.3 V
VOH
Output
0.5 V
Output
0.5 V
≈ 1.3 V
VOL
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 8. Receiver Test Circuit and Voltage Waveforms
8
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SLLS376C− MAY 2000 − REVISED DECEMBER 2000
TYPICAL CHARACTERISTICS
Receiver Output
Driver Input
120 Ω
120 Ω
Driver Input
Receiver Output
Figure 9. Typical Waveform of Non-Return-To-Zero (NRZ), Pseudorandom Binary Sequence (PRBS) Data
at 100 Mbps Through 15m, of CAT 5 Unshielded Twisted Pair (UTP) Cable
TIA/EIA-485-A defines a maximum signaling rate as that in which the transition time of the voltage transition
of a logic-state change remains less than or equal to 30% of the bit length. Transition times of greater length
perform quite well even though they do not meet the standard by definition.
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SLLS376C− MAY 2000 − REVISED DECEMBER 2000
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
vs
FREQUENCY
LOGIC INPUT CURRENT
vs
INPUT VOLTAGE
40
−30
Driver
−25
30
I I − Input Current − µ A
I CC − Average Supply Current − mA
35
25
20
15
10
−20
−15
−10
Receiver
−5
5
0
0.05
0.5
1
2
5
10
20
0
30
0
1
f − Frequency − MHz
Figure 10
800
2.00
600
1.75
VOL − Low-Level Output voltage − V
I I − Input Current − µ A
5
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
400
200
0
−200
Bus Input Current
−400
1.50
VCC = 5
1.25
1.00
0.75
0.50
0.25
0.00
−6
−4
−2
0
2
4
6
8
10
12
VI − Input Voltage − V
0
10
20
30
40
Figure 13
POST OFFICE BOX 655303
50
60
70
IOL − Low-Level Output Current − mA
Figure 12
10
4
3
Figure 11
INPUT CURRENT
vs
INPUT VOLTAGE
−600
−8
2
VI − Input Voltage − V
• DALLAS, TEXAS 75265
80
SLLS376C− MAY 2000 − REVISED DECEMBER 2000
TYPICAL CHARACTERISTICS
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
AVERAGE CASE TEMPERATURE
5
VOD − Average Differential Output Voltage − V
2
VOH − High-Level Output Voltage − V
4.5
4
VCC = 5.25 V
3.5
3
2.5
VCC = 5 V
2
VCC = 4.75 V
1.5
1
0.5
0
1.5
1
0.5
0
0
−10
−20
−30
−40
−50
−60
−70
−80
−40
Figure 14
70
85
DRIVER PROPAGATION DELAY TIME
vs
CASE TEMPERATURE
13.8
7.4
13.7
7.2
13.6
7
Propagation Delay Time − ns
TPHL Receiver (ns)
25
Figure 15
RECEIVER PROPAGATION TIME
vs
CASE TEMPERATURE
13.5
13.4
13.3
13.2
13.1
13
12.9
−40
0
Average Case Temperature − °C
I OH − High-Level Output Current − (mA)
6.8
6.6
6.4
6.2
6
5.8
0
70
25
80
5.6
−40
Case Temperature ° C
0
25
70
85
Case Temperature − ° C
Figure 16
Figure 17
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11
SLLS376C− MAY 2000 − REVISED DECEMBER 2000
TYPICAL CHARACTERISTICS
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
90
I O − Output Current − mA
65
40
15
IOH
−10
−35
−60
−85
−110
−135
IOL
−160
−185
−210
0
3
5
4
VCC − Supply Voltage − V
Figure 18
12
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6
SLLS376C− MAY 2000 − REVISED DECEMBER 2000
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°−ā 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SLLS376C− MAY 2000 − REVISED DECEMBER 2000
MECHANICAL INFORMATION
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65LBC176AD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC176ADG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC176ADR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC176ADRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC176AP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN65LBC176APE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
SN65LBC176AQD
ACTIVE
SOIC
D
8
75
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65LBC176AQDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LBC176AQDR
ACTIVE
SOIC
D
8
2500
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65LBC176AQDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC176AD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC176ADG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC176ADR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC176ADRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LBC176AP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN75LBC176APE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2007
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65LBC176ADR
D
8
SITE 27
330
12
6.4
5.2
2.1
8
12
Q1
SN65LBC176ADR
D
8
SITE 60
330
12
6.4
5.2
2.1
8
12
Q1
SN75LBC176ADR
D
8
SITE 27
330
12
6.4
5.2
2.1
8
12
Q1
SN75LBC176ADR
D
8
SITE 60
330
12
6.4
5.2
2.1
8
12
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN65LBC176ADR
D
8
SITE 27
342.9
336.6
20.64
SN65LBC176ADR
D
8
SITE 60
346.0
346.0
29.0
SN75LBC176ADR
D
8
SITE 27
342.9
336.6
20.64
SN75LBC176ADR
D
8
SITE 60
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
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