TI SN74LV126APW

SN54LV126A, SN74LV126A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCES131C – MARCH 1998 – REVISED JULY 1998
D
D
D
D
D
EPIC (Enhanced-Performance Implanted
CMOS) Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC, TA = 25°C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
SN54LV126A . . . J OR W PACKAGE
SN74LV126A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1OE
1A
1Y
2OE
2A
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4OE
4A
4Y
3OE
3A
3Y
SN54LV126A . . . FK PACKAGE
(TOP VIEW)
1A
1OE
NC
VCC
4OE
D
1Y
NC
2OE
NC
2A
description
These quadruple bus buffer gates are designed
for 2-V to 5.5-V VCC operation.
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3OE
2Y
GND
NC
3Y
3A
The ’LV126A devices feature independent line
drivers with 3-state outputs. Each output is
disabled when the associated output-enable (OE)
input is low.
4
NC – No internal connection
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
The SN54LV126A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV126A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1998, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54LV126A, SN74LV126A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCES131C – MARCH 1998 – REVISED JULY 1998
logic symbol†
1OE
1A
2OE
2A
3OE
3A
4OE
4A
1
EN
1
3
2
4
6
5
10
8
9
13
11
12
1Y
2Y
3Y
4Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
logic diagram (positive logic)
1OE
1A
2OE
2A
1
2
3OE
3
1Y
3A
4
5
4OE
6
2Y
4A
10
9
8
3Y
13
12
11
4Y
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LV126A, SN74LV126A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCES131C – MARCH 1998 – REVISED JULY 1998
recommended operating conditions (see Note 4)
SN54LV126A
VCC
VIH
High level input voltage
High-level
VIL
Low level input voltage
Low-level
VI
Input voltage
VO
IOH
IOL
∆t/∆v
MAX
2
5.5
Supply voltage
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
5.5
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
0.5
High or low state
0
3-state
0
UNIT
V
V
0.5
VCC × 0.3
VCC × 0.3
VCC × 0.3
VCC × 0.3
VCC × 0.3
5.5
0
VCC
5.5
VCC × 0.3
5.5
0
0
V
V
VCC
5.5
V
µA
VCC = 2 V
VCC = 2.3 V to 2.7 V
–50
–50
–2
–2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
–8
–8
–16
–16
VCC = 2 V
VCC = 2.3 V to 2.7 V
50
50
2
2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
8
8
16
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
Input transition rise or fall rate
2
VCC × 0.7
VCC × 0.7
0
Low level output current
Low-level
MAX
1.5
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
High level output current
High-level
MIN
1.5
VCC = 2 V
VCC = 2.3 V to 2.7 V
Output voltage
SN74LV126A
MIN
mA
µA
mA
16
0
200
0
200
0
100
0
100
ns/V
VCC = 4.5 V to 5.5 V
0
20
0
20
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
SN54LV126A
TEST CONDITIONS
IOH = –50 µA
IOH = –2 mA
2 V to 5.5 V
IOL = 50 µA
IOL = 2 mA
ICC
Ioff
VI = VCC or GND,
VI or VO = 0 to 5.5 V
Ci
VI = VCC or GND
TYP
IO = 0
SN74LV126A
MAX
MIN
VCC–0.1
2
3V
2.48
2.48
4.5 V
3.8
TYP
MAX
UNIT
V
3.8
2 V to 5.5 V
IOL = 8 mA
IOL = 16 mA
VI = VCC or GND
VO = VCC or GND
MIN
VCC–0.1
2
2.3 V
IOH = –8 mA
IOH = –16 mA
II
IOZ
VCC
0.1
0.1
2.3 V
0.4
0.4
3V
0.44
0.44
4.5 V
0.55
0.55
5.5 V
±1
±1
µA
5.5 V
±5
±5
µA
5.5 V
20
20
µA
5
µA
0V
3.3 V
5
1.6
1.6
V
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54LV126A, SN74LV126A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCES131C – MARCH 1998 – REVISED JULY 1998
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
tpd*
ten*
FROM
(INPUT)
TO
(OUTPUT)
A
Y
LOAD
CAPACITANCE
MIN
TA = 25°C
TYP
MAX
7.1
CL = 15 pF
SN54LV126A
SN74LV126A
MIN
MAX
MIN
MAX
13
1
15.5
1
15.5
OE
Y
7.4
13
1
15.5
1
15.5
tdis*
tpd
OE
Y
5.7
14.7
1
17
1
17
A
Y
9.2
16.5
1
18.5
1
18.5
ten
tdis
OE
Y
9.5
16.5
1
18.5
1
18.5
OE
Y
8.1
18.2
15
20.5
1
20.5
CL = 50 pF
tsk(o)†
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
† Skew between any two outputs of the same package switching in the same direction
2
UNIT
ns
ns
2
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
tpd*
ten*
FROM
(INPUT)
TO
(OUTPUT)
A
Y
LOAD
CAPACITANCE
TA = 25°C
MIN
TYP
MAX
5
CL = 15 pF
SN54LV126A
SN74LV126A
MIN
MAX
MIN
MAX
8
1
9.5
1
9.5
OE
Y
5.1
8
1
9.5
1
9.5
tdis*
tpd
OE
Y
4.4
9.7
1
11.5
1
11.5
A
Y
6.4
11.5
1
13
1
13
ten
tdis
OE
Y
6.6
11.5
1
13
1
13
OE
Y
6.1
13.2
1
15
1
15
CL = 50 pF
tsk(o)†
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
† Skew between any two outputs of the same package switching in the same direction
1.5
UNIT
ns
ns
1.5
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tpd*
ten*
FROM
(INPUT)
TO
(OUTPUT)
A
Y
OE
Y
tdis*
tpd
OE
A
ten
tdis
OE
Y
OE
Y
LOAD
CAPACITANCE
MIN
TA = 25°C
TYP
MAX
SN74LV126A
MIN
MAX
MIN
MAX
3.5
5.5
1
6.5
1
6.5
3.6
5.1
1
6
1
6
Y
3.3
6.8
1
8
1
8
Y
4.6
7.5
1
8.5
1
8.5
4.6
7.1
1
8
1
8
4.3
8.8
1
10
1
10
CL = 15 pF
CL = 50 pF
tsk(o)†
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
† Skew between any two outputs of the same package switching in the same direction
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
SN54LV126A
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
1
UNIT
ns
ns
SN54LV126A, SN74LV126A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCES131C – MARCH 1998 – REVISED JULY 1998
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
SN74LV126A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.32
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.23
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
3.06
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
V
2.31
V
0.97
V
VCC
3.3 V
TYP
UNIT
5V
15.9
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
POST OFFICE BOX 655303
CL = 50 pF,
pF
• DALLAS, TEXAS 75265
f = 10 MHz
14.4
pF
5
SN54LV126A, SN74LV126A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCES131C – MARCH 1998 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
From Output
Under Test
Test
Point
From Output
Under Test
VCC
Open
S1
TEST
GND
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
CL
(see Note A)
CL
(see Note A)
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
Input
50% VCC
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
0V
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
VOH
50% VCC
VOL
50% VCC
tPZL
tPHL
tPHL
Out-of-Phase
Output
0V
VCC
Output
Control
tPLZ
50% VCC
tPZH
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
≈ VCC
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
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• DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright  1998, Texas Instruments Incorporated