SCES598C – JULY 2004 – REVISED OCTOBER 2004
D Available in the Texas Instruments
D
D
D
D
D
D
D
DBV OR DCK PACKAGE
(TOP VIEW)
NanoStar and NanoFree Packages
Control Inputs VIH/VIL Levels Are
Referenced to VCCA Voltage
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
I/Os Are 4.6-V Tolerant
Ioff Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
VCCA
GND
A
1
6
2
5
3
4
VCCB
DIR
B
YEP OR YZP PACKAGE
(BOTTOM VIEW)
A
GND
VCCA
3 4
2 5
1 6
B
DIR
VCCB
description/ordering information
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track
VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional
translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCH1T45 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input.
The SN74AVCH1T45 is designed so that the DIR input is powered by VCCA.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
−40°C to 85°C
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
TOP-SIDE
MARKING‡
SN74AVCH1T45YEPR
Tape and reel
_ _ _TF_
SN74AVCH1T45YZPR
SOT (SOT-23) − DBV
Tape and reel
SN74AVCH1T45DBVR
ET1_
SOT (SC-70) − DCK
Tape and reel
SN74AVCH1T45DCKR
TF_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright 2004, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCES598C – JULY 2004 – REVISED OCTOBER 2004
description/ordering information (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, then both outputs are in the high-impedance
state. The bus-hold circuitry on the powered-up side always stays active.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
FUNCTION TABLE
INPUT
DIR
OPERATION
L
B data to A bus
H
A data to B bus
logic diagram (positive logic)
DIR
A
5
3
4
VCCA
2
POST OFFICE BOX 655303
VCCB
• DALLAS, TEXAS 75265
B
SCES598C – JULY 2004 – REVISED OCTOBER 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCCA and VCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1): I/O ports (A port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
I/O ports (B port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCA + 0.5 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCCB + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCCA, VCCB, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SCES598C – JULY 2004 – REVISED OCTOBER 2004
recommended operating conditions (see Notes 4 through 8)
VCCI
VCCA
VCCB
VCCO
MIN
MAX
Supply voltage
1.2
3.6
V
Supply voltage
1.2
3.6
V
VCCI × 0.65
1.6
1.2 V to 1.95 V
VIH
High-level input
voltage
Data inputs
(see Note 7)
1.95 V to 2.7 V
2.7 V to 3.6 V
VIL
Data inputs
(see Note 7)
VCCI × 0.35
0.7
1.95 V to 2.7 V
2.7 V to 3.6 V
VIH
VIL
VI
VO
IOH
IOL
∆t/∆v
High-level input
voltage
Low-level input
voltage
DIR
(referenced to VCCA)
(see Note 8)
DIR
(referenced to VCCA)
(see Note 8)
V
0.8
VCCA × 0.65
1.6
1.2 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
V
2
VCCA × 0.35
0.7
1.2 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
V
0.8
Input voltage
Output voltage
V
2
1.2 V to 1.95 V
Low-level input
voltage
UNIT
0
3.6
V
Active state
0
3-state
0
VCCO
3.6
V
High-level output current
Low-level output current
1.2 V
−3
1.4 V to 1.6 V
−6
1.65 V to 1.95 V
−8
2.3 V to 2.7 V
−9
3 V to 3.6 V
−12
1.2 V
3
1.4 V to 1.6 V
6
1.65 V to 1.95 V
8
2.3 V to 2.7 V
9
3 V to 3.6 V
12
Input transition rise or fall rate
5
mA
mA
ns/V
TA
Operating free-air temperature
−40
85
°C
NOTES: 4. VCCI is the VCC associated with the data input port.
5. VCCO is the VCC associated with the output port.
6. All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7. For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
8. For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES598C – JULY 2004 – REVISED OCTOBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Notes 9 and 10)
PARAMETER
TEST CONDITIONS
1.2 V to 3.6 V
1.2 V to 3.6 V
1.2 V
1.2 V
1.4 V
1.4 V
1.05
1.65 V
1.65 V
1.2
IOH = −9 mA
IOH = −12 mA
2.3 V
2.3 V
1.75
3V
3V
2.3
IOL = 100 µA
IOL = 3 mA
1.2 V to 3.6 V
1.2 V to 3.6 V
1.2 V
1.2 V
IOH = −6 mA
IOH = −8 mA
IOL = 6 mA
IOL = 8 mA
VOL
II
IBHL†
IBHH‡
IBHHO¶
MIN
MAX
VCCO − 0.2 V
V
0.2
0.15
1.4 V
0.35
1.65 V
0.45
2.3 V
2.3 V
0.55
3V
3V
0.7
1.2 V to 3.6 V
1.2 V to 3.6 V
VI = 0.42 V
VI = 0.49 V
1.2 V
1.2 V
1.4 V
1.4 V
15
VI = 0.58 V
VI = 0.7 V
1.65 V
1.65 V
25
2.3 V
2.3 V
45
VI = 0.8 V
VI = 0.78 V
3.3 V
3.3 V
100
1.2 V
1.2 V
VI = 0.91 V
VI = 1.07 V
1.4 V
1.4 V
−15
1.65 V
1.65 V
−25
2.3 V
2.3 V
−45
3.3 V
3.3 V
−100
1.2 V
1.2 V
1.6 V
1.6 V
125
1.95 V
1.95 V
200
2.7 V
2.7 V
300
3.6 V
3.6 V
1.2 V
1.2 V
VI = VCCA or GND
VI = 0 to VCC
VI = 0 to VCC
VI = VIL
UNIT
0.95
1.4 V
VI = 1.6 V
VI = 2 V
IBHLO§
VI = VIH
MIN
1.65 V
IOL = 9 mA
IOL = 12 mA
DIR
input
−40°C to 85°C
VCCB
IOH = −100 µA
IOH = −3 mA
VOH
TA = 25°C
TYP
MAX
VCCA
±0.025
±0.25
±1
V
µA
25
µA
−25
µA
50
µA
500
−50
1.6 V
1.6 V
−125
1.95 V
1.95 V
−200
2.7 V
2.7 V
−300
3.6 V
3.6 V
−500
µA
† The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
‡ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
§ An external driver must source at least IBHLO to switch this node from low to high.
¶ An external driver must sink at least IBHHO to switch this node from high to low.
NOTES: 9. VCCO is the VCC associated with the output port.
10. VCCI is the VCC associated with the input port.
POST OFFICE BOX 655303
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5
SCES598C – JULY 2004 – REVISED OCTOBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Notes 9 and 10) (continued)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
MIN
TA = 25°C
TYP
MAX
−40°C to 85°C
MIN
MAX
UNIT
0V
0 to 3.6 V
Ioff
VI or VO = 0 to 3.6 V
±0.1
±1
±5
B port
0 to 3.6 V
0V
±0.1
±1
±5
IOZ
A or B
ports
VO = VCCO or GND
1.2 V to 3.6 V
1.2 V to 3.6 V
±0.5
±2.5
±5
1.2 V to 3.6 V
1.2 V to 3.6 V
10
0V
3.6 V
−2
3.6 V
0V
10
1.2 V to 3.6 V
1.2 V to 3.6 V
10
0V
3.6 V
10
3.6 V
0V
−2
1.2 V to 3.6 V
1.2 V to 3.6 V
20
VI = 3.3 V or GND
3.3 V
3.3 V
2.5
pF
VO = 3.3 V or GND
3.3 V
3.3 V
6
pF
A port
ICCA
VI = VCCI or GND,
ICCB
VI = VCCI or GND,
ICCA ) ICCB
Control
Ci
inputs
Cio
IO = 0
A or B
ports
IO = 0
VI = VCCI or GND,
IO = 0
µA
A
µA
µA
µA
µA
NOTES: 9. VCCO is the VCC associated with the output port.
10. VCCI is the VCC associated with the input port.
switching characteristics over recommended operating free-air temperature range,
VCCA = 1.2 V (see Figure 11)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
B
tPLH
tPHL
B
A
tPHZ
tPLZ
DIR
A
DIR
B
DIR
A
DIR
B
tPHZ
tPLZ
tPZH†
tPZL†
tPZH†
tPZL†
VCCB = 1.2 V
TYP
VCCB = 1.5 V
TYP
VCCB = 1.8 V
TYP
VCCB = 2.5 V
TYP
3.3
2.7
2.4
2.3
2.4
3.3
2.7
2.4
2.3
2.4
3.3
3.1
2.9
2.8
2.7
3.3
3.1
2.9
2.8
2.7
5.1
5.2
5.3
5.2
3.7
5.1
5.2
5.3
5.2
3.7
5.3
4.3
4
3.3
3.7
5.3
4.3
4
3.3
3.7
8.5
6.9
6.4
5.5
6.1
8.5
6.9
6.4
5.5
6.1
8.3
7.8
7.7
7.5
5.9
8.3
7.8
7.7
7.5
5.9
† The enable time is a calculated value, derived using the formula shown in the enable times section, page 16.
6
VCCB = 3.3 V
TYP
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
ns
ns
SCES598C – JULY 2004 – REVISED OCTOBER 2004
switching characteristics over recommended operating free-air temperature range,
VCCA = 1.5 V ± 0.1 V (see Figure 11)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
B
tPLH
tPHL
B
A
tPHZ
tPLZ
DIR
A
DIR
B
DIR
A
DIR
B
PARAMETER
tPHZ
tPLZ
tPZH†
tPZL†
tPZH†
tPZL†
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.9
0.7
5.6
0.6
5.2
0.5
4.2
0.5
3.8
2.9
0.7
5.6
0.6
5.2
0.5
4.2
0.5
3.8
2.6
0.6
5.5
0.4
5.3
0.3
4.9
0.3
4.8
2.6
0.6
5.5
0.4
5.3
0.3
4.9
0.3
4.8
3.8
1.6
6.7
1.5
6.8
0.3
6.9
0.9
6.9
3.8
1.6
6.7
1.5
6.8
0.3
6.9
0.9
6.9
5.1
1.8
8.1
1.6
7.1
1.1
4.7
1.4
4.5
5.1
1.8
8.1
1.6
7.1
1.1
4.7
1.4
4.5
7.7
13.6
12.4
9.6
9.3
7.7
13.6
12.4
9.6
9.3
6.7
12.3
12
11.1
10.7
6.7
12.3
12
11.1
10.7
UNIT
ns
ns
ns
ns
ns
ns
† The enable time is a calculated value, derived using the formula shown in the enable times section, page 16.
switching characteristics over recommended operating free-air temperature range,
VCCA = 1.8 V ± 0.15 V (see Figure 11)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
B
tPLH
tPHL
B
A
tPHZ
tPLZ
DIR
A
DIR
B
DIR
A
DIR
B
PARAMETER
tPHZ
tPLZ
tPZH†
tPZL†
tPZH†
tPZL†
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.8
0.6
5.3
0.5
5
0.4
3.9
0.4
3.4
2.8
0.6
5.3
0.5
5
0.4
3.9
0.4
3.4
2.3
0.5
5.2
0.4
5
0.3
4.6
0.2
4.4
2.3
0.5
5.2
0.4
5
0.3
4.6
0.2
4.4
3.8
1.6
5.9
1.6
5.9
1.6
5.9
0.5
6
3.8
1.6
5.9
1.6
5.9
1.6
5.9
0.5
6
5
1.8
7.7
1.4
6.8
1
4.4
1.4
4.3
5
1.89
7.7
1.4
6.8
1
4.4
1.4
4.3
7.3
12.9
11.8
9
8.7
7.3
12.9
11.8
9
8.7
6.5
11.2
10.9
9.8
9.4
6.5
11.2
10.9
9.8
9.4
UNIT
ns
ns
ns
ns
ns
ns
† The enable time is a calculated value, derived using the formula shown in the enable times section, page 16.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SCES598C – JULY 2004 – REVISED OCTOBER 2004
switching characteristics over recommended operating free-air temperature range,
VCCA = 2.5 V ± 0.2 V (see Figure 11)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
B
tPLH
tPHL
B
A
tPHZ
tPLZ
DIR
A
DIR
B
DIR
A
DIR
B
PARAMETER
tPHZ
tPLZ
tPZH†
tPZL†
tPZH†
tPZL†
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.6
0.5
4.9
0.4
4.6
0.3
3.4
0.3
3
2.6
0.5
4.9
0.4
4.6
0.3
3.4
0.3
3
2.2
0.4
4.2
0.3
3.8
0.2
3.4
0.2
3.3
2.2
0.4
4.2
0.3
3.8
0.2
3.4
0.2
3.3
2.8
0.3
3.8
0.8
3.8
0.4
3.8
0.5
3.8
2.8
0.3
3.8
0.8
3.8
0.4
3.8
0.5
3.8
4.9
2
7.6
1.5
6.5
0.6
4.1
1
4
4.9
2
7.6
1.5
6.5
0.6
4.1
1
4
7.1
11.8
10.3
7.5
7.3
7.1
11.8
10.3
7.5
7.3
5.4
8.6
8.1
7
6.6
5.4
8.6
8.1
7
6.6
UNIT
ns
ns
ns
ns
ns
ns
† The enable time is a calculated value, derived using the formula shown in the enable times section, page 16.
switching characteristics over recommended operating free-air temperature range,
VCCA = 3.3 V ± 0.3 V (see Figure 11)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
B
tPLH
tPHL
B
A
tPHZ
tPLZ
DIR
A
DIR
B
DIR
A
DIR
B
PARAMETER
tPHZ
tPLZ
tPZH†
tPZL†
tPZH†
tPZL†
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.6
0.4
4.7
0.3
4.4
0.2
3.3
0.2
2.8
2.6
0.4
4.7
0.3
4.4
0.2
3.3
0.2
2.8
2.2
0.4
3.8
0.3
3.4
0.2
3
0.1
2.8
2.2
0.4
3.8
0.3
3.4
0.2
3
0.1
2.8
3.1
1.3
4.3
1.3
4.3
1.3
4.3
1.3
4.3
3.1
1.3
4.3
1.3
4.3
1.3
4.3
1.3
4.3
4
0.7
7.4
0.6
6.5
0.7
4
1.5
3.9
4
0.7
7.4
0.6
6.5
0.7
4
1.5
3.9
6.2
11.2
9.9
7
6.7
6.2
11.2
9.9
7
6.7
5.7
8.9
8.5
7.2
6.8
5.7
8.9
8.5
7.2
6.8
† The enable time is a calculated value, derived using the formula shown in the enable times section, page 16.
8
VCCB = 3.3 V
± 0.3 V
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UNIT
ns
ns
ns
ns
ns
ns
SCES598C – JULY 2004 – REVISED OCTOBER 2004
operating characteristics, TA = 25°C
PARAMETER
CpdA†
CpdB†
A-port input,
B-port output
B-port input,
A-port output
A-port input,
B-port output
B-port input,
A-port output
TEST
CONDITIONS
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
VCCA =
VCCB = 1.2 V
VCCA =
VCCB = 1.5 V
VCCA =
VCCB = 1.8 V
VCCA =
VCCB = 2.5 V
VCCA =
VCCB = 3.3 V
TYP
TYP
TYP
TYP
TYP
3
3
3
3
4
14
14
14
15
16
14
14
14
15
16
3
3
3
3
4
UNIT
pF
pF
† Power-dissipation capacitance per transceiver
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9
SCES598C – JULY 2004 – REVISED OCTOBER 2004
power-up considerations
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,
oscillations, or other anomalies. To guard against such power-up problems, take the following precautions:
1. Connect ground before any supply voltage is applied.
2. Power up VCCA.
3. VCCB can be ramped up along with or after VCCA.
typical total static power consumption (ICCA + ICCB)
Table 1
VCCB
10
VCCA
0V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0V
0
<0.5
<0.5
<0.5
<0.5
<0.5
1.2 V
<0.5
<1
<1
<1
<1
1
1.5 V
<0.5
<1
<1
<1
<1
1
1.8 V
<0.5
<1
<1
<1
<1
<1
2.5 V
<0.5
1
<1
<1
<1
<1
3.3 V
<0.5
1
<1
<1
<1
<1
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UNIT
µA
A
SCES598C – JULY 2004 – REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
6
6
5
5
4
4
tPHL − ns
tPLH − ns
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 1.2 V
3
2
2
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
1
3
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
1
VCCB = 2.5 V
VCCB = 3.3 V
0
0
10
20
30
40
50
VCCB = 2.5 V
VCCB = 3.3 V
0
60
0
10
20
CL − pF
Figure 1
30
CL − pF
40
50
60
Figure 2
6
6
5
5
4
4
tPHL − ns
tPLH − ns
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 1.5 V
3
2
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
1
3
2
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
1
VCCB = 2.5 V
VCCB = 3.3 V
0
0
10
20
30
40
50
60
VCCB = 2.5 V
VCCB = 3.3 V
0
0
10
CL − pF
Figure 3
20
30
CL − pF
40
50
60
Figure 4
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11
SCES598C – JULY 2004 – REVISED OCTOBER 2004
6
6
5
5
4
4
tPHL − ns
tPLH − ns
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 1.8 V
3
2
2
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
1
0
3
1
VCCB = 2.5 V
VCCB = 3.3 V
0
10
20
30
40
50
0
60
VCCB = 2.5 V
VCCB = 3.3 V
0
10
20
CL − pF
30
CL − pF
40
50
60
40
50
60
Figure 6
Figure 5
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 2.5 V
6
6
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
5
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
5
VCCB = 2.5 V
VCCB = 3.3 V
4
tPHL − ns
tPLH − ns
4
3
3
2
2
1
1
0
VCCB = 2.5 V
VCCB = 3.3 V
0
10
20
30
40
50
60
0
0
10
CL − pF
Figure 7
12
20
30
CL − pF
Figure 8
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SCES598C – JULY 2004 – REVISED OCTOBER 2004
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 3.3 V
6
6
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
5
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
5
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 2.5 V
VCCB = 3.3 V
4
tPHL − ns
tPLH − ns
4
3
3
2
2
1
1
0
0
10
20
30
40
50
60
0
0
10
CL − pF
Figure 9
20
30
CL − pF
40
50
60
Figure 10
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13
SCES598C – JULY 2004 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
1.2 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
CL
RL
15 pF
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
VTP
0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
0V
tPLZ
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VOH
VCCO/2
VOL
VCCO/2
VCCA/2
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
VCCO/2
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VTP
VCCO/2
VOH − VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns,
dv/dt ≥1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
Figure 11. Load Circuit and Voltage Waveforms
14
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SCES598C – JULY 2004 – REVISED OCTOBER 2004
APPLICATION INFORMATION
Figure 12 shows an example of the SN74AVCH1T45 being used in a unidirectional logic level-shifting application.
VCC1
VCC1
VCC2
1
6
2
5
3
4
SYSTEM-1
VCC2
SYSTEM-2
PIN
NAME
1
VCCA
FUNCTION
VCC1
SYSTEM-1 supply voltage (1.2 V to 3.6 V)
DESCRIPTION
2
GND
GND
Device GND
3
A
OUT
Output level depends on VCC1 voltage.
4
B
IN
5
DIR
DIR
6
VCCB
VCC2
Input threshold value depends on VCC2 voltage.
GND (low level) determines B-port to A-port direction.
SYSTEM-2 supply voltage (1.2 V to 3.6 V)
Figure 12. Unidirectional Logic Level-Shifting Application
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15
SCES598C – JULY 2004 – REVISED OCTOBER 2004
APPLICATION INFORMATION
Figure 13 shows the SN74AVCH1T45 being used in a bidirectional logic level-shifting application. Since the
SN74AVCH1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
VCC1
VCC1
VCC2
I/O-1
VCC2
I/O-2
1
6
2
5
3
4
DIR CTRL
SYSTEM-1
SYSTEM-2
Following is a sequence that illustrates data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2
to SYSTEM-1.
STATE
DIR CTRL
I/O-1
I/O-2
DESCRIPTION
1
H
Out
In
2
H
Hi-Z
Hi-Z
SYSTEM-2 is getting ready to send data to
SYSTEM-1. I/O-1 and I/O-2 are disabled.
The bus-line state depends on bus hold.
3
L
Hi-Z
Hi-Z
DIR bit is flipped. I/O-1 and I/O-2 are still disabled.
The bus-line state depends on bus hold.
4
L
Out
In
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 data to SYSTEM-1
Figure 13. Bidirectional Logic Level-Shifting Application
enable times
Calculate the enable times for the SN74AVCH1T45 using the following formulas:
tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVCH1T45 initially is transmitting from A to B,
then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After
the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
16
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MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
6
0,10 M
4
1,40
1,10
1
0,13 NOM
2,40
1,80
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553-3/D 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
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