TI BQ4010YMA-70

bq4010/bq4010Y
8Kx8 Nonvolatile SRAM
Features
General Description
➤ Data retention in the absence of
power
The CMOS bq4010 is a nonvolatile
65,536-bit static RAM organized as
8,192 words by 8 bits. The integral
control circuitry and lithium energy
source provide reliable nonvolatility
coupled with the unlimited write
cycles of standard SRAM.
➤ Automatic write-protection
during power-up/power-down
cycles
➤ Industry-standard 28-pin 8K x 8
pinout
➤ Conventional SRAM operation;
unlimited write cycles
➤ 10-year minimum data retention
in absence of power
The control circuitry constantly
monitors the single 5V supply for an
out-of-tolerance condition. When VCC
falls out of tolerance, the SRAM is
unconditionally write-protected to
prevent inadvertent write operation.
At this time the integral energy
source is switched on to sustain the
memory until after VCC returns valid.
The bq4010 uses an extremely low
standby current CMOS SRAM,
coupled with a small lithium coin
cell to provide nonvolatility without
long write-cycle times and the writecycle limitations associated with
EEPROM.
The bq4010 requires no external circuitry and is socket-compatible with
industry-standard SRAMs and most
EPROMs and EEPROMs.
➤ Battery internally isolated until
power is applied
Pin Connections
Pin Names
Block Diagram
A0 –A12
Address inputs
DQ0–DQ7
Data input/output
CE
Chip enable input
OE
Output enable input
WE
Write enable input
NC
No connect
VCC
+5 volt supply input
VSS
Ground
Selection Guide
Part
Number
Maximum
Access
Time (ns)
Negative
Supply
Tolerance
Part
Number
bq4010Y -70
Maximum
Access
Time (ns)
Negative
Supply
Tolerance
70
-10%
bq4010 -85
85
-5%
bq4010Y -85
85
-10%
bq4010 -150
150
-5%
bq4010Y -150
150
-10%
-5%
bq4010Y -200
200
-10%
bq4010 -200
200
Sept. 1996 D
1
bq4010/bq4010Y
Functional Description
When power is valid, the bq4010 operates as a standard
CMOS SRAM. During power-down and power-up cycles,
the bq4010 acts as a nonvolatile memory, automatically
protecting and preserving the memory contents.
Power-down/power-up control circuitry constantly
monitors the VCC supply for a power-fail-detect threshold
VPFD. The bq4010 monitors for VPFD = 4.62V typical for
use in systems with 5% supply tolerance. The bq4010Y
monitors for VPFD = 4.37V typical for use in systems with
10% supply tolerance.
When VCC falls below the VPFD threshold, the SRAM
automatically write-protects the data. All outputs
become high impedance, and all inputs are treated as
“don’t care.” If a valid access is in process at the time of
power-fail detection, the memory cycle continues to completion. If the memory cycle fails to terminate within
time tWPT, write-protection takes place.
As VCC falls past VPFD and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
which provides data retention until valid VCC is applied.
When VCC returns to a level above the internal backup
cell voltage, the supply is switched back to VCC. After
VCC ramps above the VPFD threshold, write-protection
continues for a time tCER (120ms maximum) to allow for
processor stabilization. Normal memory operation may
resume after this time.
The internal coin cell used by the bq4010 has an
extremely long shelf life and provides data retention for
more than 10 years in the absence of system power.
As shipped from Benchmarq, the integral lithium cell is
electrically isolated from the memory. (Self-discharge in
this condition is approximately 0.5% per year.) Following
the first application of VCC, this isolation is broken, and
the lithium backup cell provides data retention on
subsequent power-downs.
Truth Table
CE
WE
OE
I/O Operation
Power
Not selected
Mode
H
X
X
High Z
Standby
Output disable
L
H
H
High Z
Active
Read
L
H
L
DOUT
Active
Write
L
L
X
DIN
Active
Absolute Maximum Ratings
Value
Unit
VCC
Symbol
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
VT
DC voltage applied on any pin excluding VCC
relative to VSS
-0.3 to 7.0
V
VT ≤ VCC + 0.3
0 to +70
°C
Commercial
TOPR
Operating temperature
-40 to +85
°C
Industrial “N”
TSTG
Storage temperature
TBIAS
Temperature under bias
TSOLDER
Soldering temperature
Note:
Parameter
Conditions
-40 to +70
°C
Commercial
-40 to +85
°C
Industrial “N”
-10 to +70
°C
Commercial
-40 to +85
°C
Industrial “N”
+260
°C
For 10 seconds
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Sept. 1996 D
6-2
bq4010/bq4010Y
Recommended DC Operating Conditions (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
4.5
5.0
5.5
V
bq4010Y/bq4010Y-xxxN
4.75
5.0
5.5
V
bq4010
0
0
0
V
VCC
Supply voltage
VSS
Supply voltage
VIL
Input low voltage
-0.3
-
0.8
V
VIH
Input high voltage
2.2
-
VCC + 0.3
V
Note:
Typical values indicate operation at TA = 25°C.
DC Electrical Characteristics (TA = TOPR, VCCmin
Symbol
Notes
Parameter
≤ VCC ≤ VCCmax)
Minimum
Typical
Maximum
Unit
Conditions/Notes
ILI
Input leakage current
-
-
±1
µA
VIN = VSS to VCC
ILO
Output leakage current
-
-
±1
µA
CE = VIH or OE = VIH or
WE = VIL
VOH
Output high voltage
2.4
-
-
V
IOH = -1.0 mA
VOL
Output low voltage
-
-
0.4
V
IOL = 2.1 mA
ISB1
Standby supply current
-
4
7
mA
CE = VIH
ISB2
Standby supply current
-
2.5
4
mA
CE ≥ VCC - 0.2V,
0V ≤ VIN ≤ 0.2V,
or VIN ≥ VCC - 0.2V
ICC
Operating supply current
-
65
75
mA
Min. cycle, duty = 100%,
CE = VIL, II/O = 0mA
4.55
4.62
4.75
V
bq4010
VPFD
Power-fail-detect voltage
4.30
4.37
4.50
V
bq4010Y
VSO
Supply switch-over voltage
-
3
-
V
Note:
Typical values indicate operation at TA = 25°C, VCC = 5V.
Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions
CI/O
Input/output capacitance
-
-
10
pF
Output voltage = 0V
CIN
Input capacitance
-
-
10
pF
Input voltage = 0V
Note:
These parameters are sampled and not 100% tested.
Sept. 1996 D
6-3
bq4010/bq4010Y
AC Test Conditions
Parameter
Test Conditions
Input pulse levels
0V to 3.0V
Input rise and fall times
5 ns
Input and output timing reference levels
1.5 V (unless otherwise specified)
Output load (including scope and jig)
See Figures 1 and 2
Figure 1. Output Load A
Read Cycle (TA = TOPR, VCCmin
Figure 2. Output Load B
≤ VCC ≤ VCCmax)
-70/-70N
Symbol
Parameter
-85/-85N
-150/-150N
-200
Conditions
Max.
Min.
Max.
Min.
70
-
85
-
150
-
200
-
ns
Address access time
-
70
-
85
-
150
-
200
ns
Output load A
Chip enable access time
-
70
-
85
-
150
-
200
ns
Output load A
tOE
Output enable to output
valid
-
35
-
45
-
70
-
90
ns
Output load A
tCLZ
Chip enable to output
in low Z
5
-
5
-
10
-
10
-
ns
Output load B
tOLZ
Output enable to output
in low Z
5
-
5
-
5
-
5
-
ns
Output load B
tCHZ
Chip disable to output
in high Z
0
25
0
40
0
60
0
70
ns
Output load B
tOHZ
Output disable to
output in high Z
0
25
0
30
0
50
0
70
ns
Output load B
tOH
Output hold from
address change
10
-
10
-
10
-
10
-
ns
Output load A
Read cycle time
tAA
tACE
Max. Min.
Unit
Min.
tRC
Max.
Sept. 1996 D
6-4
bq4010/bq4010Y
Read Cycle No. 1 (Address Access) 1,2
Read Cycle No. 2 (CE Access) 1,3,4
Read Cycle No. 3 (OE Access) 1,5
Notes:
1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = VIL.
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Device is continuously selected: CE = VIL.
Sept. 1996 D
6-5
bq4010/bq4010Y
Write Cycle
(TA = TOPR, VCCmin ≤ VCC ≤ V CCmax)
-70/-70N
-85/-85N
-150/-150N
-200
Min.
Max.
Min.
Max.
Min.
Max.
Min.
tWC
Write cycle time
70
-
85
-
150
-
200
-
ns
tCW
Chip enable to end
of write
55
-
75
-
100
-
150
-
ns
(1)
tAW
Address valid to end
of write
55
-
75
-
90
-
150
-
ns
(1)
tAS
Address setup time
0
-
0
-
0
-
0
-
ns
Measured from
address valid to
beginning of write. (2)
tWP
Write pulse width
55
-
65
-
90
-
130
-
ns
Measured from
beginning of write to
end of write. (1)
tWR1
Write recovery time
(write cycle 1)
5
-
5
-
5
-
5
-
ns
Measured from WE
going high to end of
write cycle. (3)
tWR2
Write recovery time
(write cycle 2)
15
-
15
-
15
-
15
-
ns
Measured from CE
going high to end of
write cycle. (3)
tDW
Data valid to end of
write
30
-
35
-
50
-
70
-
ns
Measured from first
low-to-high transition
of either CE or WE.
tDH1
Data hold time
(write cycle 1)
0
-
0
-
0
-
0
-
ns
Measured from WE
going high to end of
write cycle. (4)
tDH2
Data hold time
(write cycle 2)
10
-
10
-
0
-
0
-
ns
Measured from CE
going high to end of
write cycle. (4)
tWZ
Write enabled to
output in high Z
0
25
0
30
0
50
0
70
ns
I/O pins are in output
state. (5)
tOW
Output active from
end of write
5
-
5
-
5
-
5
-
ns
I/O pins are in output
state. (5)
Symbol
Notes:
Parameter
Max. Units
Conditions/Notes
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
Sept. 1996 D
6-6
bq4010/bq4010Y
Write Cycle No. 1 (WE-Controlled) 1,2,3
Write Cycle No. 2 (CE-Controlled) 1,2,3,4,5
Notes:
1. CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. If OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
Sept. 1996 D
6-7
bq4010/bq4010Y
Power-Down/Power-Up Cycle (TA = TOPR)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
tPF
VCC slew, 4.75 to 4.25 V
300
-
-
µs
tFS
VCC slew, 4.25 to VSO
10
-
-
µs
tPU
VCC slew, VSO to VPFD (max.)
0
-
-
µs
tCER
Chip enable recovery time
40
80
120
ms
tDR
Data-retention time in
absence of VCC
10
-
-
years
TA = 25°C. (2)
tDR-N
Data-retention time in
absence of VCC
6
-
-
years
TA = 25°C (2); industrial
temperature range (-N) only.
tWPT
Write-protect time
40
100
150
µs
Notes:
Time during which SRAM is
write-protected after VCC passes
VPFD on power-up.
Delay after VCC slews down past
VPFD before SRAM is writeprotected.
1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Battery is disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
Sept. 1996 D
6-8
bq4010/bq4010Y
Data Sheet Revision History
Change No.
Page No.
1
2, 3, 4, 6, 8, 9
2
1, 4, 6, 9
3
1
Notes:
Description
Added industrial temperature range for bq4010YMA-85N and -150N.
Added 70 ns speed grade for bq4010-70 and bq4010Y-70 and added
industrial temperature range for bq4010YMA-70N.
Removed 70ns speed grade for bq4010-70.
Change 1 = Sept 1991 B changes from Sept. 1990 A.
Change 2 = Feb. 1994 C changes from Sept. 1991 B.
Change 3 = Sept. 1996 D changes from Feb. 1994 C.
MA: 28-Pin A-Type Module
28-Pin MA (A-Type Module)
Inches
Sept. 1996 D
6-9
Millimeters
Dimension
Min.
Max.
Min.
Max.
A
0.365
0.375
9.27
9.53
A1
0.015
-
0.38
-
B
0.017
0.023
0.43
0.58
C
0.008
0.013
0.20
0.33
D
1.470
1.500
37.34
38.10
E
0.710
0.740
18.03
18.80
e
0.590
0.630
14.99
16.00
G
0.090
0.110
2.29
2.79
L
0.120
0.150
3.05
3.81
S
0.075
0.110
1.91
2.79
bq4010/bq4010Y
Ordering Information
bq4010
MA Temperature:
blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)*
Speed Options:
85 = 85 ns
150 = 150 ns
200 = 200 ns
Package Option:
MA = A-type module
Supply Tolerance:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance
Device:
bq4010
*Note:
8K x 8 NVSRAM
Only 10% supply (“Y”) version is available in industrial
temperature range; contact factory for speed grade
availability.
Sept. 1996 D
6-10
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ4010MA-150
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4010MA-200
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4010MA-70
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4010MA-85
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4010YMA-150
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4010YMA-150N
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4010YMA-200
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4010YMA-70
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4010YMA-70N
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4010YMA-85
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
BQ4010YMA-85N
ACTIVE
DIP MOD
ULE
MA
0
1
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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