MOTOROLA Order this document by MCM6227A/D SEMICONDUCTOR TECHNICAL DATA MCM6227A 1M x 1 Bit Static Random Access Memory The MCM6227A is a 1,048,576 bit static random–access memory organized as 1,048,576 words of 1 bit, fabricated using high–performance silicon–gate CMOS technology. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6227A is equipped with a chip enable (E) pin. In less than a cycle time after E goes high, the part enters a low–power standby mode, remaining in that state until E goes low again. The MCM6227A is available in 400 mil, 28–lead surface–mount SOJ packages. • • • • • • Single 5 V ± 10% Power Supply Fast Access Times: 20, 25, 35, and 45 ns Equal Address and Chip Enable Access Times Input and Output are TTL Compatible Three–State Output Low Power Operation: 160/140/130/120 mA Maximum, Active AC BLOCK DIAGRAM A0 V CC A1 VSS A2 A3 A4 A5 MEMORY MATRIX 1024 ROWS x 1024 COLUMNS ROW DECODER PIN ASSIGNMENT A0 1 28 VCC A1 2 27 A19 A2 3 26 A18 A3 4 25 A17 A4 5 24 A16 A5 6 23 A15 NC 7 22 A14 A6 8 21 NC A7 9 20 A13 A8 10 19 A12 A9 11 18 A11 Q 12 17 A10 W 13 16 D VSS 14 15 E PIN NAMES A6 A0 – A19 . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . . Write Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable D . . . . . . . . . . . . . . . . . . . . . . . . Data Input Q . . . . . . . . . . . . . . . . . . . . . Data Output NC . . . . . . . . . . . . . . . . . . No Connection VCC . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . Ground A7 A8 A9 D WJ PACKAGE 400 MIL SOJ CASE 810–03 COLUMN I/O INPUT DATA CONTROL Q COLUMN DECODER E A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 W REV 4 5/95 Motorola, Inc. 1994 MOTOROLA FAST SRAM MCM6227A 1 MCM6227A TRUTH TABLE E W Mode I/O Pin Cycle Current H X Not Selected High–Z — ISB1, ISB2 L H Read Dout Read ICCA L L Write High–Z Write ICCA H = High, L = Low, X = Don’t Care ABSOLUTE MAXIMUM RATINGS (See Note) Rating Symbol Value Unit VCC – 0.5 to 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current Iout ± 20 mA Power Dissipation PD 1.1 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC Storage Temperature Tstg – 55 to + 150 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high–impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit Supply Voltage (Operating Voltage Range) Parameter VCC 4.5 5.5 V Input High Voltage VIH 2.2 VCC + 0.3** V Input Low Voltage VIL – 0.5* 0.8 V * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns). ** VIH (max) = VCC = 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns). DC CHARACTERISTICS AND SUPPLY CURRENTS Parameter Symbol Min Typ* Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(I) — — ±1 µA Output Leakage Current (E = VIH, Vout = 0 to VCC) Ilkg(O) — — ±1 µA — — — — 120 110 100 90 160 140 130 120 AC Active Supply Current (Iout = 0 mA, VCC = max) MCM6227A–20: tAVAV = 20 ns MCM6227A–25: tAVAV = 25 ns MCM6227A–35: tAVAV = 35 ns MCM6227A–45: tAVAV = 45 ns ICCA mA AC Standby Current (VCC = max, E = VIH, f = fmax) ISB1 — 7 20 mA CMOS Standby Current (E ≥ VCC – 0.2 V, Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V, VCC = max, f = 0 MHz) ISB2 — 4 15 mA Output Low Voltage (IOL = + 8.0 mA) VOL — — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — — V * Typical values are measured at 25°C, VCC = 5 V. MCM6227A 2 MOTOROLA FAST SRAM CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Characteristic Input Capacitance All Inputs Except Clocks and D, Q E and W Input and Output Capacitance D, Q Symbol Typ Max Unit Cin 4 5 6 8 pF Cin, Cout 5 8 pF AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1A READ CYCLE TIMING (See Notes 1 and 2) 6227A–20 Parameter Symbol Min Read Cycle Time tAVAV Address Access Time tAVQV Enable Access Time 6227A–25 Max Min 20 — — 20 tELQV — Output Hold from Address Change tAXQX Enable Low to Output Active Enable High to Output High–Z 6227A–35 Max Min 25 — — 25 20 — 5 — tELQX 5 tEHQZ 0 6227A–45 Max Min Max Unit Notes 35 — — 35 45 — ns 2,3 — 45 ns 25 — 35 — 45 ns 5 — 5 — 5 — ns — 5 — 5 — 5 — ns 5, 6, 7 9 0 10 0 12 — 18 ns 5, 6, 7 Power Up Time tELICCH 0 — 0 — 0 — 0 — ns Power Down Time tEHICCL — 20 — 25 — 35 — 45 ns 4 NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. At any given voltage and temperature, tEHQZ max is less than tELQX min, both for a given device and from device to device. 6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. 7. This parameter is sampled and not 100% tested. 8. Device is continuously selected (E ≤ VIL). TIMING LIMITS AC TEST LOADS +5V RL = 50 Ω OUTPUT 480 Ω OUTPUT Z0 = 50 Ω 255 Ω 5 pF VL = 1.5 V Figure 1A MOTOROLA FAST SRAM Figure 1B The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. MCM6227A 3 READ CYCLE 1 (See Notes 1, 2, and 8) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV READ CYCLE 2 (See Note 4) tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tEHQZ tELQX Q (DATA OUT) ICC SUPPLY CURRENT ISB MCM6227A 4 HIGH–Z DATA VALID tAVQV tELICCH tEHICCL MOTOROLA FAST SRAM WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) 6227A–20 Parameter Write Cycle Time 6227A–25 6227A–35 6227A–45 Symbol Min Max Min Max Min Max Min Max Unit Notes tAVAV 20 — 25 — 35 — 45 — ns 3 Address Setup Time tAVWL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 15 — 17 — 20 — 25 — ns Write Pulse Width tWLWH, tWLEH 15 — 17 — 20 — 25 — ns Data Valid to End of Write tDVWH 10 — 10 — 15 — 20 — ns Data Hold TIme tWHDX 0 — 0 — 0 — 0 — ns Write Low to Data High–Z tWLQZ 0 9 0 10 0 15 0 20 ns 4, 5, 6 Write High to Output Active tWHQX 5 — 5 — 5 — 5 — ns 4, 5, 6 Write Recovery Time tWHAX 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device. WRITE CYCLE 1 (W Controlled See Notes 1 and 2) tAVAV A (ADDRESS) tWHAX tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL tDVWH D (DATA IN) DATA VALID tWLQZ Q (DATA OUT) tWHDX HIGH–Z MOTOROLA FAST SRAM tWHDX HIGH–Z MCM6227A 5 WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) 6227A–20 Parameter 6227A–25 6227A–35 6227A–45 Symbol Min Max Min Max Min Max Min Max Unit Notes tAVAV 20 — 25 — 35 — 45 — ns 3 Write Cycle Time Address Setup Time tAVEL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 15 — 17 — 20 — 25 — ns Enable to End of Write tELEH, tELWH 15 — 17 — 20 — 25 — ns Write Pulse Width tWLEH 15 — 17 — 20 — 25 — ns Data Valid to End of Write tDVEH 10 — 10 — 15 — 20 — ns Data Hold Time tEHDX 0 — 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — 0 — ns 4, 5 NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high–impedance state. 5. If E goes high coincident with or before W goes high, the output will remain in a high–impedance state. WRITE CYCLE 2 (E Controlled See Notes 1 and 2) tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL tELWH tEHAX tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX HIGH–Z Q (DATA OUT) ORDERING INFORMATION (Order by Full Part Number) MCM 6227A WJ XX XX Motorola Memory Prefix Shipping Method (R2 = Tape and Reel, Blank = Rails) Part Number Speed (20 = 20 ns, 25 = 25 ns, 35 = 35 ns, 45 = 45 ns) Package (WJ = 400 mil SOJ) Full Part Numbers — MCM6227AWJ20 MCM6227AWJ25 MCM6227AWJ35 MCM6227AWJ45 MCM6227A 6 MCM6227AWJ20R2 MCM6227AWJ25R2 MCM6227AWJ35R2 MCM6227AWJ45R2 MOTOROLA FAST SRAM PACKAGE DIMENSIONS 28 LEAD 400 MIL SOJ CASE 810–03 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. DIM A B C D E F G H K L M N P R S MOTOROLA FAST SRAM MILLIMETERS MIN MAX 18.29 18.54 10.04 10.28 3.75 3.26 0.50 0.39 2.48 2.24 0.81 0.67 1.27 BSC 0.50 — 1.14 0.89 0.64 BSC 5° 0° 1.14 0.76 11.30 11.05 9.65 9.15 1.01 0.77 INCHES MIN MAX 0.720 0.730 0.395 0.405 0.128 0.148 0.015 0.020 0.088 0.098 0.026 0.032 0.050 BSC — 0.020 0.035 0.045 0.025 BSC 5° 0° 0.030 0.045 0.435 0.445 0.360 0.380 0.030 0.040 MCM6227A 7 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. 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Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MCM6227A 8 ◊ CODELINE TO BE PLACED HERE *MCM6227A/D* MCM6227A/D MOTOROLA FAST SRAM