SN54AC86, SN74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCAS533A – AUGUST 1995 – REVISED MAY 1996 D D EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK) and Flatpacks (W), and Standard Plastic (N) and Ceramic (J) DIPs SN54AC86 . . . J OR W PACKAGE SN74AC86 . . . D, DB, N, OR PW PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND description The ’AC86 are quadruple 2-input exclusive-OR gates. The devices perform the Boolean function Y = A B or Y = AB + AB in positive logic. A B OUTPUT Y L L L L H H H L H H H L 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y SN54AC86 . . . FK PACKAGE (TOP VIEW) 1Y NC 2A NC 2B FUNCTION TABLE (each gate) INPUTS 13 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A The SN54AC86 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74AC86 is characterized for operation from –40°C to 85°C. 14 2 1B 1A NC VCC 4B A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output. 1 NC – No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AC86, SN74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCAS533A – AUGUST 1995 – REVISED MAY 1996 logic symbol† 1A 1B 2A 2B 3A 3B 4A 4B 1 =1 2 4 3 6 5 1Y 2Y 9 8 10 12 11 13 3Y 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, PW, and W packages. exclusive-OR logic An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. EXCLUSIVE OR =1 These five equivalent exclusive-OR symbols are valid for an ’AC86 gate in positive logic; negation may be shown at any two ports. LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT = 2k The output is active (low) if all inputs stand at the same logic level (i.e., A = B). 2 The output is active (low) if an even number of inputs (i.e., 0 or 2) are active. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ODD-PARITY ELEMENT 2k + 1 The output is active (high) if an odd number of inputs (i.e., only 1 of the 2) are active. SN54AC86, SN74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCAS533A – AUGUST 1995 – REVISED MAY 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . 1.25 W DB package . . . . . . . . . . . . . . . . . . . 0.5 W N package . . . . . . . . . . . . . . . . . . . . 1.1 W PW package . . . . . . . . . . . . . . . . . . . 0.5 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils, except for the N package, which has a trace length of zero. recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V SN54AC86 SN74AC86 MIN MAX MIN MAX 2 6 2 6 2.1 2.1 3.15 3.15 3.85 3.85 VIL Low-level input voltage VI VO Input voltage 0 Output voltage 0 IOH High-level output current IOL ∆t/∆v VCC = 4.5 V VCC = 5.5 V Low-level output current 0.9 1.35 0 VCC VCC –12 –12 –24 –24 VCC = 5.5 V VCC = 3 V –24 –24 12 12 VCC = 4.5 V VCC = 5.5 V 24 24 24 24 Input transition rise or fall rate • DALLAS, TEXAS 75265 V 1.65 0 VCC = 3 V VCC = 4.5 V TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 0.9 1.65 V V 1.35 VCC VCC UNIT V V mA mA 0 8 0 8 ns/V –55 125 –40 85 °C 3 SN54AC86, SN74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCAS533A – AUGUST 1995 – REVISED MAY 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –50 µA IOH = –12 mA VOH IOH = –24 24 mA IOH = –50 mA† IOH = –75 mA† TA = 25°C TYP MAX SN54AC86 SN74AC86 MIN MIN MAX 3V 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 5.5 V 5.4 5.4 5.4 3V 2.56 2.4 2.46 4.5 V 3.86 3.7 3.76 5.5 V 4.86 4.7 4.76 5.5 V IOL = 12 mA IOL = 24 mA 3.85 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 5.5 V 0.001 0.1 0.1 0.1 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 5.5 V 0.36 0.5 0.44 5.5 V II ICC VI = VCC or GND VI = VCC or GND, 5.5 V Ci VI = VCC or GND UNIT V 3V IOL = 50 mA† IOL = 75 mA† V 1.65 5.5 V IO = 0 MAX 3.85 5.5 V IOL = 50 µA VOL MIN 1.65 5.5 V 5V ±0.1 ±1 ±1 µA 2 40 20 µA 2.6 pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. " switching characteristics over recommended operating free-air temperature range, 0.3 V (unless otherwise noted) (see Figure 1) VCC = 3.3 V PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B Y TA = 25°C MIN TYP MAX SN54AC86 SN74AC86 MIN MAX MIN MAX 2 6.5 11.5 1 14 1.5 12.5 2 6 11.5 1 14 1.5 12.5 UNIT ns " switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B Y TA = 25°C MIN TYP MAX SN54AC86 SN74AC86 MIN MAX MIN MAX 1.5 4.5 8.5 1 10 1 9 1.5 4.5 8.5 1 10 1 9.5 UNIT ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance CL = 50 pF, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP 25 UNIT pF SN54AC86, SN74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCAS533A – AUGUST 1995 – REVISED MAY 1996 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test CL = 50 pF (see Note A) Open TEST S1 tPLH/tPHL Open 500 Ω LOAD CIRCUIT tw 2.7 V Input 50% VCC 50% VCC 0V VCC 50% VCC Input VOLTAGE WAVEFORMS 50% VCC tPHL tPLH VCC 50% VCC Timing Input 0V tsu Data Input In-Phase Output VCC 50% VCC VOH 50% VCC VOL 50% VCC tPLH tPHL th 50% VCC 0V Out-of-Phase Output 0V VOH 50% VCC VOL 50% VCC VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr C. The outputs are measured one at a time with one input transition per measurement. v 2.5 ns, tf v 2.5 ns. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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