SN54ACT1284, SN74ACT1284 7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996 D D D D SN54ACT1284 . . . J OR W PACKAGE SN74ACT1284 . . . DB, DW, N, OR PW PACKAGE (TOP VIEW) 3-State Outputs Directly Drive Bus Lines Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Designed for the IEEE 1284-I (Level 1 Type) and IEEE 1284-II (Level 2 Type) Electrical Specifications Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and DIP (N) Packages, Ceramic Chip Carriers (FK), Flat (W), and DIP (J) Packages A1 A2 A3 A4 GND GND A5 A6 A7 DIR 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 B1 B2 B3 B4 VCC VCC B5 B6 B7 HD FK PACKAGE (TOP VIEW) A3 A2 A1 B1 B2 D D description The ’ACT1284 are designed for asynchronous two-way communication between data buses. The control function minimizes external timing requirements. A4 GND GND A5 A6 The devices allow data transmission in either the A-to-B or the B-to-A direction for bits 1, 2, 3, and 4, depending on the logic level at the direction-control (DIR) input. Bits 5, 6, and 7, however, always transmit in the A-to-B direction. 4 3 2 1 20 19 18 5 17 6 16 7 15 14 8 B3 B4 VCC VCC B5 A7 DIR HD B7 B6 9 10 11 12 13 The output drive for each mode is determined by the high drive (HD) control pin. When HD is high, the high drive is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the drive requirements as specified in the IEEE 1284-I (level 1 type) and the IEEE 1284-II (level 2 type) parallel peripheral-interface specification. The SN54ACT1284 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ACT1284 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUT MODE Open drain A to B: Bits 5, 6, 7 DIR HD L L Totem pole B to A: Bits 1, 2, 3, 4 L H Totem pole B to A: Bits 1, 2, 3, 4 and A to B: Bits 5, 6, 7 H L Open drain A to B: Bits 1, 2, 3, 4, 5, 6, 7 H H Totem pole A to B: Bits 1, 2, 3, 4, 5, 6, 7 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ACT1284, SN74ACT1284 7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996 logic diagram (positive logic) HD DIR A1, A2, A3, A4 B1, B2, B3, B4 B5, B6, B7 A5, A6, A7 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V B-port input and output voltage range, VI and VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . –2 V to 7 V A-port input and output voltage range, VI and VO (see Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The ac input voltage pulsewidth is limited to 20 ns if the input voltage goes more negative than –0.5 V. 3. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ACT1284, SN74ACT1284 7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996 recommended operating conditions SN54ACT1284 VCC VIH Supply voltage VIL VI Low-level input voltage VO Open drain output voltage IOH High level output current High-level IOL Low level output current Low-level TA Operating free-air temperature SN74ACT1284 MIN MAX MIN MAX 4.7 5.5 4.7 5.5 High-level input voltage 2 2 0.8 Input voltage 0 HD low 0 B port, HD high VCC 5.5 0 0 0.8 V VCC 5.5 V –14 –14 –4 –4 B port 14 14 A port 4 4 125 0 V V A port –55 UNIT 70 V mA mA °C electrical characteristics over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted) PARAMETER Vh hys VOH II IOZ IOFF ICC B port Ci Control inputs Cio A or B ports SN74ACT1284 MAX MIN 0.4 0.2 0.2 IOH = –14 mA 4.7 V 2.4 2.4 IOH = –50 µA MIN to MAX VCC–0.2 VCC –0.2 IOH = –4 mA IOL = 14 mA 4.7 V 3.7 TYP MAX UNIT V V 3.7 4.7 V IOL = 50 µA IOL = 4 mA A or B ports‡ TYP 0.4 B port A port MIN 5V VIT IT+ – VIT IT– for all inputs A port SN54ACT1284 VCC† 4.7 V Input hysteresis B port VOL TEST CONDITIONS 47V 4.7 0.4 0.4 0.2 0.2 0.4 0.4 ±1 ±1 µA µA V VI = VCC or GND VO = VCC or GND 5.5 V 5.5 V ±20 ±20 VI or VO ≤ 7 V VI = VCC or GND, 0V ±100 ±100 µA 1.5 1.5 mA IO = 0 VI = VCC or GND VO = VCC or GND 5.5 V 5V 4 4 pF 5V 12 12 pF ZO B port IOH = –20 mA, IOH = –50 mA 5V 8 30 † For I/O ports, the parameter IOZ includes the input leakage current II. ‡ For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. 8 30 Ω switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL Totem pole SR Totem pole FROM (INPUT) TO (OUTPUT) A or B B or A B output tpd(EN) tpd(DIS) Totem pole HD B tr, tf Open drain A B SN54ACT1284 SN74ACT1284 MIN MAX MIN MAX 1 20 1 20 1 20 1 20 0.05 0.4 0.05 0.4 1 20 1 20 1 20 1 20 120 120 UNIT ns V/ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ACT1284, SN74ACT1284 7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION VCC From B Output Under Test 62 Ω CL = 50 pF (see Note A) TP1 tPHL 33 Ω Input (see Note C) 1.5 V 0V Output (see Note D) Sink Load 3V 1.5 V tPLH tPHL VOH VOH – 1.4 V VOL VOH VOL + 1.4 V tPLH VOL Source Load 62 Ω VOLTAGE WAVEFORMS MEASURED AT TP1 PROPAGATION DELAY TIMES (A to B) CL = 50 pF (see Note A) A-TO-B LOAD (totem pole) Input (see Note F) VCC 3V 1.5 V 1.5 V 0V TP1 VOL (see Note E) 500 Ω 2V 0.8 V 2V 0.8 V VOH VOL tf tr From B Output VOLTAGE WAVEFORMS MEASURED AT TP1 (B SIDE) CL = 50 pF (see Note A) A-TO-B LOAD (open drain) Input (see Note F) 0V From A Output Under Test CL = 50 pF (see Note A) 3V 1.5 V 1.5 V tPLH 500 Ω tPHL VOH Output 50% VCC 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B to A) B-TO-A LOAD (totem pole) NOTES: A. B. C. D. E. F. CL includes probe and jig capacitance. The outputs are measured one at a time with one transition per measurement. Input rise and fall times are 3 ns, 150 ns < pulsewidth <10 µs for both low-to-high and high-to-low transitions. Slew rate is defined as 10% and 90% of the transition times. Rise and fall times, open drain, are <120 ns. Input rise and fall times are 3 ns. Figure 1. Load Circuits and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated