Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Freescale Semiconductor, Inc... 8M Late Write HSTL The MCM63R836/918 is an 8M–bit synchronous late write fast static RAM designed to provide high performance in secondary cache and ATM switch, Telecom, and other high speed memory applications. The MCM63R918 (organized as 512K words by 18 bits) and the MCM63R836 (organized as 256K words by 36 bits) are fabricated in Motorola’s high performance silicon gate CMOS technology. The differential clock (CK) inputs control the timing of read/write operations of the RAM. At the rising edge of CK; all addresses, write enables, and synchronous selects are registered. An internal buffer and special logic enable the memory to accept write data on the rising edge of CK, a cycle after address and control signals. Read data is also driven on the rising edge of CK. The RAM uses HSTL inputs and outputs. The adjustable input trip–point (Vref) and output voltage (V DDQ ) gives the system designer greater flexibility in optimizing system performance. The synchronous write and byte enables allow writing to individual bytes or the entire word. The impedance of the output buffers is programmable, allowing the outputs to match the impedance of the circuit traces which reduces signal reflections. Order this document by MCM63R836/D MCM63R836 MCM63R918 FC PACKAGE PBGA CASE 999D–01 • • • • • • • • • • Byte Write Control 2.5 V – 5% to 3.3 V + 10% Operation HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible) HSTL — User Selectable Input Trip–Point HSTL — Compatible Programmable Impedance Output Drivers Register to Register Synchronous Operation Boundary Scan (JTAG) IEEE 1149.1 Compatible Differential Clock Inputs Optional x18 or x36 Organization MCM63R836/918–3.0 = 3.0 ns MCM63R836/918–3.3 = 3.3 ns MCM63R836/918–3.7 = 3.7 ns MCM63R836/918–4.0 = 4.0 ns • Sleep Mode Operation (ZZ pin) • 119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Flipped Chip Plastic Ball Grid Array (PBGA) REV 1 10/12/00 Motorola, Inc. 2000 MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63R836•MCM63R918 1 Freescale Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM ADDRESS REGISTERS SA DATA IN REGISTER MEMORY ARRAY DQ DATA OUT REGISTER SW SW REGISTERS SBx CONTROL LOGIC CK Freescale Semiconductor, Inc... G SS REGISTERS SS PIN ASSIGNMENTS TOP VIEW MCM63R918 MCM63R836 A B C D 1 2 3 4 5 6 7 VDDQ SA SA NC SA SA VDDQ NC NC DQc NC SA DQc SA SA VSS NC VDD ZQ SA SA VSS SA SA DQb NC NC DQb E DQc VDDQ DQc VSS VSS SS G VSS VSS DQb K DQb VDDQ DQc DQc DQc VDDQ VDD DQd DQd SBc VSS Vref VSS NC NC VDD CK SBb VSS Vref VSS DQb DQb DQb VDD VDDQ DQa DQa DQd DQd T U 4 5 6 7 VDDQ SA SA NC SA SA VDDQ NC NC SA NC SA SA NC NC SA SA VDD SA SA NC DQb NC VSS ZQ VSS DQa NC NC DQb VSS SS VSS NC DQa VDDQ NC VSS G VSS DQa VDDQ NC DQb SBb NC VSS NC DQa J DQb NC VSS NC VSS DQa NC K VDDQ VDD Vref VDD Vref VDD VDDQ SBd CK SBa DQa DQa NC DQb VSS CK VSS NC DQa DQb NC VSS CK SBa DQa NC VDDQ DQb VSS SW VSS NC VDDQ M VDDQ DQd R H L M P F DQb L N D 3 G DQc J C DQb G H B 2 E DQc F A 1 DQd DQd NC NC DQd DQd SA NC VDDQ TMS VSS VSS VSS VSS SA TDI MCM63R836•MCM63R918 2 SW SA SA VDD SA TCK VSS VSS VSS VDD SA TDO DQa VDDQ DQa DQa SA NC DQa DQa NC ZZ NC VDDQ N P R DQb NC VSS SA VSS DQa NC NC DQb VSS SA VSS NC DQa NC SA VSS VDD VDD SA NC NC SA SA NC SA SA ZZ TDI TCK TDO T U VDDQ TMS For More Information On This Product, Go to: www.freescale.com NC VDDQ MOTOROLA FAST SRAM Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MCM63R836 PIN DESCRIPTIONS Pin Locations Symbol Type 4K CK Input Address, data in, and control input register clock. Active high. 4L CK Input Address, data in, and control input register clock. Active low. (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P DQx I/O 4F G Input Output Enable functionality not supported. Must be tied to VSS or driven to ≤ VIL Max. 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T SA Input Synchronous Address Inputs: Registered on the rising clock edge. 5L, 5G, 3G, 3L (a), (b), (c), (d) SBx Input Synchronous Byte Write Enable: Enables writes to byte x in conjunction with the SW input. Has no effect on read cycles, active low. 4E SS Input Synchronous Chip Enable: Registered on the rising clock edge, active low. 4M SW Input Synchronous Write: Registered on the rising clock edge, active low. Writes all enabled bytes. 4U TCK Input Test Clock (JTAG). 3U TDI Input Test Data In (JTAG). 5U TDO Output 2U TMS Input Test Mode Select (JTAG). 4D ZQ Input Programmable Output Impedance: Programming pin. 7T ZZ Input Enables sleep mode, active high. 4C, 2J, 4J, 6J, 4R, 5R VDD Supply Core Power Supply. 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VDDQ Supply Output Power Supply: Provides operating power for output buffers. 3J, 5J Vref Supply Input Reference: Provides reference voltage for input buffers. 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 3R VSS Supply Ground. 4A, 1B, 2B, 4B, 7B, 1C, 7C, 4G, 4H, 1R, 7R, 1T, 2T, 6T, 6U NC — MOTOROLA FAST SRAM Description Synchronous Data I/O. Test Data Out (JTAG). No Connection: There is no connection to the chip. For More Information On This Product, Go to: www.freescale.com MCM63R836•MCM63R918 3 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MCM63R918 PIN DESCRIPTIONS Pin Locations Symbol Type 4K CK Input Address, data in, and control input register clock. Active high. 4L CK Input Address, data in, and control input register clock. Active low. (a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P DQx I/O 4F G Input Output Enable functionality not supported. Must be tied to VSS or driven to ≤ VIL Max. 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C, 6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T SA Input Synchronous Address Inputs: Registered on the rising clock edge. 5L, 3G (a), (b) SBx Input Synchronous Byte Write Enable: Enables writes to byte x in conjunction with the SW input. Has no effect on read cycles, active low. 4E SS Input Synchronous Chip Enable: Registered on the rising clock edge, active low. 4M SW Input Synchronous Write: Registered on the rising clock edge, active low. Writes all enabled bytes. 4U TCK Input Test Clock (JTAG). 3U TDI Input Test Data In (JTAG). 5U TDO Output 2U TMS Input Test Mode Select (JTAG). 4D ZQ Input Programmable Output Impedance: Programming pin. 7T ZZ Input Enables sleep mode, active high. 4C, 2J, 4J, 6J, 4R, 5R VDD Supply Core Power Supply. 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VDDQ Supply Output Power Supply: Provides operating power for output buffers. 3J, 5J Vref Supply Input Reference: Provides reference voltage for input buffers. 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 3R VSS Supply Ground. 4A, 1B, 2B, 4B, 7B, 1C, 7C, 2D, 7D, 1E, 6E, 2F, 1G, 4G, 6G, 2H, 4H, 7H, 1K, 6K, 2L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U NC — MCM63R836•MCM63R918 4 Description Synchronous Data I/O. Test Data Out (JTAG). No Connection: There is no connection to the chip. For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS, See Note) Symbol Value Unit VDD –0.5 to 3.9 V VDDQ –0.5 to 2.5 V Vin –0.5 to 2.5 V VJTAG –0.5 to 3.9 V Iin ±50 mA Output Current (per I/O) Iout ±25 mA Operating Temperature TA 0 to 70 °C Temperature Under Bias Tbias –10 to 85 °C Tstg –55 to 125 °C Rating Core Supply Voltage Output Supply Voltage Voltage On Any Pin Other Than JTAG Voltage On Any JTAG Pin Input Current (per I/O) Freescale Semiconductor, Inc... Storage Temperature This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High–Z at power up. NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. PBGA PACKAGE THERMAL CHARACTERISTICS Rating Junction to Ambient (Still Air) Symbol Max Unit Notes RθJA 50 °C/W 1, 2 Junction to Ambient (@200 ft/min) Single–Layer Board RθJA 39 °C/W 1, 2 Junction to Ambient (@200 ft/min) Four–Layer Board RθJA 27 °C/W 3 Junction to Board (Bottom) RθJB 23 °C/W 4 Junction to Case (Top) RθJC 1 °C/W 5 NOTES: 1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38–87. 3. Measured using a four–layer test board with two internal planes. 4. Indicates the average thermal resistance between the die and the printed circuit board as measured by the ring cold plate method. 5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883 Method 1012.1). CLOCK TRUTH TABLE K ZZ SS SW SBa L–H L L H X X X L–H L L L L H H L–H L L L H L H L–H L L L H H L–H L L L H L–H L L L L–H L L L–H L H L–H L H X H X MOTOROLA FAST SRAM SBb SBc SBd DQ (n) DQ (n + 1) Mode X X Dout 0 – 35 Read Cycle All Bytes H High–Z Din 0 – 8 Write Cycle 1st Byte H High–Z Din 9 – 17 Write Cycle 2nd Byte L H High–Z Din 18 – 26 Write Cycle 3rd Byte H H L High–Z Din 27 – 35 Write Cycle 4th Byte L L L L High–Z Din 0 – 35 Write Cycle All Bytes L H H H H High–Z High–Z Abort Write Cycle H X X X X X High–Z Deselect Cycle L X X X X High–Z High–Z Deselect Cycle X X X X X High–Z High–Z Sleep Mode For More Information On This Product, Go to: www.freescale.com MCM63R836•MCM63R918 5 Freescale Semiconductor, Inc. DC OPERATING CONDITIONS AND CHARACTERISTICS (2.375 V ≤ VDD ≤ 3.6 V, 0°C ≤ TA ≤ 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (See Notes 1 through 4) Parameter Core Power Supply Voltage Min Max –3.0 Max –3.3 Max –3.7 Max –4.0 Max Unit Notes VDD 2.375 — — — — 3.6 V VDDQ 1.4 — — — — 2.0 V AC Supply Current x36 (Device Selected, x18 All Outputs Open, Freq = Max, VDD = Max, VDDQ = Max). Includes Supply Currents for VDD. IDD1 — — 500 450 480 430 460 410 440 390 500 450 mA 5 Quiescent Active Power Supply Current (Device Selected, All Outputs Open, Freq = 0, VDD = Max, VDDQ = Max). Includes Supply Currents for VDD. IDD2 — 175 175 175 175 175 mA 6 Active Standby Power Supply Current (Device Deselected, Freq = Max, VDD = Max, VDDQ = Max). ISB1 — 200 195 190 185 200 mA 7 CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static at CMOS Levels). ISB2 — 175 175 175 175 175 mA 6, 7 IZZ — 50 50 50 50 50 mA 6, 7 Vref (dc) 0.6 — — — — 1.3 V 8 Output Driver Supply Voltage Freescale Semiconductor, Inc... Symbol Sleep Mode Current (ZZ = VIH, VDD = Max, VDDQ = Max) Input Reference DC Voltage NOTES: 1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps. 2. Supply voltage applied to VDD connections. 3. Supply voltage applied to VDDQ connections. 4. All power supply currents measured with outputs open or deselected. 5. All inputs are zero. 6. CMOS levels for I/Os are VIC ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. 7. Device deselected as defined by the Truth Table. 8. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak to peak ac component superimposed on Vref may not exceed 5% of the dc component of Vref. DC INPUT CHARACTERISTICS Parameter Symbol Min Max Unit DC Input Logic High VIH (dc) Vref + 0.1 VDDQ + 0.3 V DC Input Logic Low VIL (dc) –0.3 Vref – 0.1 V Ilkg(I) — ±5 µA Vin (dc) –0.3 2.5 V Clock Input Differential Voltage VDIF (dc) 0.2 2.5 V 3 Clock Input Common Mode Voltage Range (See Figure 2) VCM (dc) 0.60 1.3 V 4 Clock Input Crossing Point Voltage Range (See Figure 2) VX 0.60 1.3 V Input Leakage Current Clock Input Signal Voltage Notes 1, 2 NOTES: 1. 0 V ≤ Vin ≤ VDDQ for all pins. 2. Measured at Vref = 0.75 V. 3. Minimum instantaneous differential input voltage required for differential input clock operation. 4. Maximum rejectable common mode input voltage variation. MCM63R836•MCM63R918 6 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. DC OUTPUT BUFFER CHARACTERISTICS — PROGRAMMABLE IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE (2.375 V ≤ VDD ≤ 3.6 V, 0°C ≤ TA ≤ 70°C, ZQ = IZQ (out) (RQ)) (See Notes 1 and 2) Parameter Symbol Min Max Unit Notes Output Logic Low IOL (VDDQ/2) / [(RQ/5) + 10%] (VDDQ/2) / [(RQ/5) – 10%] mA 3 Output Logic High IOH (VDDQ/2) / [(RQ/5) + 10%] (VDDQ/2) / [(RQ/5) – 10%] mA 4 Light Load Output Logic Low VOL VSS 0.4 V 5 Light Load Output Logic High VOH VDDQ – 0.4 VDDQ V 6 ZQ [(RQ/5) – 10%] [(RQ/5) + 10%] Ω 7 Freescale Semiconductor, Inc... Programmable Impedance NOTES: 1. The impedance controlled mode is expected to be used in point–to–point applications, driving high–impedance inputs. 2. The ZQ pin is connected through RQ to VSS for the controlled impedance mode. 3. VOL = VDDQ/2. 4. VOH = VDDQ/2. 5. IOL ≤ 100 µA. 6. | IOH | ≤ 100 µA. 7. 175 ≤ RQ ≤ 375. DC OUTPUT BUFFER CHARACTERISTICS — MINIMUM IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE (2.375 V ≤ VDD ≤ 3.6 V, 0°C ≤ TA ≤ 70°C) (See Notes 1 and 2) Parameter Symbol Min Max Unit Notes Output Logic Low VOL2 VSS 0.4 V 3 Output Logic High VOH2 VDDQ – 0.4 VDDQ V 4 Light Load Output Logic Low VOL3 VSS 0.2 V 5 Light Load Output Logic High VOH3 VDDQ – 0.2 VDDQ V 6 NOTES: 1. The push–pull output mode is expected to be used in bussed applications and may be series or parallel terminated. Conforms to the JEDEC Standard JESD8–6 Class I. 2. The ZQ pin is connected to a 100 Ω resistor to VSS to enable the minimum impedance mode. 3. IOL ≥ 8 mA. 4. | IOH | ≥ 8 mA. 5. IOL ≤ 100 µA. 6. | IOH | ≤ 100 µA. CAPACITANCE (f = 1.0 MHz, dV = 30 mV, 2.375 V ≤ VDD ≤ 3.6 V, 0°C ≤ TA ≤ 70°C, Periodically Sampled Rather Than 100% Tested) Symbol Typ Max Unit Input Capacitance Cin 3.2 5 pF Input/Output Capacitance CI/O 3.8 6 pF CK, CK Capacitance CCK 3.7 5 pF Characteristic MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63R836•MCM63R918 7 Freescale Semiconductor, Inc. AC OPERATING CONDITIONS AND CHARACTERISTICS (2.375 V ≤ VDD ≤ 3.6 V, 0°C ≤ TA ≤ 70°C, Unless Otherwise Noted) Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.25 to 1.25 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%) Input Timing Measurement Reference Level . . . . . . . . . . . . . . 0.75 V Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 V Clock Input Timing Reference Level . . . . . . Differential Cross–Point ZQ for 50 Ω Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Ω RθJA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22C/W READ/WRITE CYCLE TIMING (See Note 1) Freescale Semiconductor, Inc... Parameter Symbol 63R836–3.0 63R918–3.0 63R836–3.3 63R918–3.3 63R836–3.7 63R918–3.7 63R836–4.0 63R918–4.0 Min Max Min Max Min Max Min Max Unit Notes Cycle Time tKHKH 3 — 3.3 — 3.7 — 4 — ns Clock High Pulse Width tKHKL 1.2 — 1.2 — 1.5 — 1.5 — ns Clock Low Pulse Width tKLKH 1.2 — 1.2 — 1.5 — 1.5 — ns Clock High to Output Low–Z tKHQX1 0.5 — 0.5 — 0.5 — 0.5 — ns Clock High to Output Valid tKHQV — 1.5 — 1.65 — 1.85 — 2 ns Clock High to Output Hold tKHQX 0.5 — 0.5 — 0.5 — 0.5 — ns 1 Clock High to Output High–Z 1, 3 tKHQZ — 1.5 — 1.6 — 1.7 — 2 ns ZZ High to Sleep Mode tZZE 3 — 3.3 — 3.7 — 4 — ns ZZ Low to Recovery tZZR — 10 — 10 — 10 — 10 ns Setup Times: Address Data In Chip Select Write Enable tAVKH tDVKH tSVKH tWVKH 0.5 — 0.5 — 0.5 — 0.5 — ns Hold Times: Address Data In Chip Select Write Enable tKHAX tKHDX tKHSX tKHWX 0.5 — 0.5 — 0.5 — 0.5 — ns 1, 2 NOTES: 1. This parameter is sampled and not 100% tested. 2. Measured at ± 200 mV from steady state. 3. Measured at ± 200 mV from steady state. See Test Load Figure 1b. MCM63R836•MCM63R918 8 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. TIMING LIMITS 0.75 V VDDQ/2 Vref DEVICE UNDER TEST ZQ The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. 50 Ω 50 Ω 250 Ω a. Test Load 16.7 Ω Freescale Semiconductor, Inc... DQ 50 Ω 50 Ω 16.7 Ω 0.75 V 5 pF 16.7 Ω 50 Ω 50 Ω 0.75 V 5 pF 0.75 V b. Test Load Figure 1. Test Loads AC INPUT CHARACTERISTICS (See Note 1) Symbol Min Max AC Input Logic High (See Figure 4) VIH (ac) Vref + 200 mV — AC Input Logic Low (See Figures 2 and 4) VIL (ac) — Vref – 200 mV 2 Input Reference Peak to Peak ac Voltage Vref (ac) — 5% Vref (dc) 3 Clock Input Differential Voltage Vdif (ac) 400 mV VDDQ + 500 mV 4 Parameter Notes NOTES: 1. Inputs may overshoot to 3.3 V for up to 35% tKHKH or 1.0 ns, whichever is smaller, and 3.8 V instantaneous peak overshoot. See Figure 2. 2. Inputs may undershoot to VSS – 1.0 V for up to 35% tKHKH or 1.0 ns, whichever is smaller, and VSS – 1.5 V instantaneous peak undershoot. See Figure 2. 3. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak to peak ac component superimposed on Vref may not exceed 5% of the dc component of Vref. 4. Minimum instantaneous differential input voltage required for differential input clock operation. MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63R836•MCM63R918 9 Freescale Semiconductor, Inc. VIH VSS – 1.0 V – 1.5 V 35% tKHKH Freescale Semiconductor, Inc... Figure 2. Undershoot Voltage VDDQ VTR CROSSING POINT VDIF VCM* VCP VSS * VCM, the Common Mode Input Voltage, equals VTR – [(VTR – VCP)/2]. Figure 3. Differential Inputs/Common Mode Input Voltage VDDQ VIH(ac) Vref VIL(ac) VSS Figure 4. AC Input Conditions MCM63R836•MCM63R918 10 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. REGISTER/REGISTER READ–WRITE–READ CYCLES t KHKH t KHKL CK t AVKH t KLKH t KHAX SA A0 A1 t SVKH A2 A3 A4 t KHSX SS t WVKH t KHWX Freescale Semiconductor, Inc... SW SBx G VIL t KHQZ t KHQX t KHQV t KHQX1 t KHDX t DVKH t KHQX DQx MOTOROLA FAST SRAM Q–1 Q0 Q1 D2 For More Information On This Product, Go to: www.freescale.com Q3 MCM63R836•MCM63R918 11 tZZR I ZZ NO READS OR WRITES ALLOWED IN SLEEP MODE ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ NO NEW READS OR WRITES ALLOWED SLEEP MODE TIMING tZZE ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ MCM63R836•MCM63R918 12 For More Information On This Product, Go to: www.freescale.com IDD ZZ DQ G V IL SW ADDR K NORMAL OPERATION Freescale Semiconductor, Inc... NORMAL OPERATION Freescale Semiconductor, Inc. MOTOROLA FAST SRAM Freescale Semiconductor, Inc. FUNCTIONAL OPERATION READ AND WRITE OPERATIONS All control signals are registered on the rising edge of the CK clock. These signals must meet the setup and hold times shown in the AC Characteristics table. On the rising edge of the following clock, read data is clocked into the output register and available at the outputs at tKHQV. During this same cycle a new read address can be applied to the address pins. A deselect cycle (dead cycle) must occur prior to a write cycle. Read cycles may follow write cycles immediately. SS and SW control output drive. Chip deselect via a high on SS at the rising edge of the CK clock has its effect on the output drivers after the next rising edge of the CK clock. SW low deselects the output drivers immediately (on the same cycle). Freescale Semiconductor, Inc... WRITE AND BYTE WRITE FUNCTIONS Note that in the following discussion the term “byte” refers to nine bits of the RAM I/O bus. In all cases, the timing parameters described for synchronous write input (SW) apply to each of the byte write enable inputs (SBa, SBb, etc.). Byte write enable inputs have no effect on read cycles. This allows the system designer not interested in performing byte writes to connect the byte enable inputs to active low (VSS). Reads of all bytes proceed normally and write cycles, activated via a low on SW, and the rising edge of the CK clock, write the entire RAM I/O width. This way the designer is spared having to drive multiple write input buffer loads. Byte writes are performed using the byte write enable inputs in conjunction with the synchronous write input (SW). It is important to note that writing any one byte will inhibit a read of all bytes at the current address. The RAM cannot simultaneously read one byte and write another at the same address. A write cycle initiated with none of the byte write enable inputs active is neither a read or a write. No write will occur, but the outputs will be deselected as in a normal write cycle. MOTOROLA FAST SRAM LATE WRITE The write address is sampled on the first rising edge of clock and write data is sampled on the following rising edge. The late write feature is implemented with single stage write buffering. Write buffering is transparent to the user. A comparator monitors the address bus and, when necessary, routes buffer contents to the outputs to assure coherent operation. This occurs in all cases whether there is a byte write or a full word is written. PROGRAMMABLE IMPEDANCE OPERATION The designer can program the RAMs output buffer impedance by terminating the ZQ pin to VSS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. For example, 250 Ω resistor will give an output impedance of 50 Ω. Impedance updates occur during write and deselect cycles. The actual change in the impedance occurs in small increments and is binary. The binary impedance has 256 values and therefore, there are no significant disturbances that occur on the output because of this smooth update method. At power up, the output impedance will take up to 65,000 cycles for the impedance to be completely updated. At recovery from sleep mode, the previously programmed value will be recovered. POWER UP AND INITIALIZATION The following supply voltage application sequence is recommended: VSS, VDD, then VDDQ. Please note, per the Absolute Maximum Ratings table, VDDQ is not to exceed VDDQ + 0.5 V or 2.0 V max, whatever the instantaneous value of VDD . Once supplies have reached specification levels, a minimum dwell of 1.0 ms with CK clock inputs cycling is required before beginning normal operations. At power up the output impedance will be set at approximately 50 Ω as stated above. For More Information On This Product, Go to: www.freescale.com MCM63R836•MCM63R918 13 Freescale Semiconductor, Inc. SLEEP MODE This device is equipped with an optional sleep or low power mode. The sleep mode pine is asynchronous and active high. During normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the chip will enter sleep mode where the device will meet lowest possible power conditions. The sleep mode timing diagram shows the modes of operation: Normal Operation, No Read/Write Allowed, and Sleep Mode. is not allowed. If a write or read operation occurs during these periods, the memory array may be corrupted. Validity of data out from the RAM can not be guaranteed immediately after ZZ is asserted (prior to being in sleep). During sleep mode recovery, the output impedance must be given additional time above and beyond tZZR in order to match desired impedance (see explanation in output impedance circuitry section). Normal Operation All inputs must meet setup and hold times prior to sleep and tZZR nanoseconds after recovering from sleep. Clock (K) must also meet cycle high and low times during these periods. Two cycles prior to sleep, initiation of either a read or write operation is not allowed. Freescale Semiconductor, Inc... No Read/Write Allowed During the period of time just prior to sleep and during recovery from sleep, the assertion of any write or read signal Sleep Mode The RAM automatically deselects itself. The RAM disconnects its internal clock buffer. The external clock may continue to run without impacting the RAMs sleep current (IZZ). All outputs will remain in a high–Z state while in sleep mode. All inputs are allowed to toggle. The RAM will not be selected, and will not perform any reads or writes. SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION OVERVIEW The serial boundary scan test access port (TAP) on this RAM is designed to operate in a manner consistent with IEEE Standard 1149.1–1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the RAMs critical speed path. Nevertheless, the RAM supports the standard TAP controller architecture. (The TAP controller is the state machine that controls the TAPs operation) and can be expected to function in a manner that does not conflict with the operation of devices with IEEE 1149.1 compliant TAPs. The TAP operates using conventional JEDEC Standard 8–1B low voltage (3.3 V) TTL/CMOS logic level signaling. DISABLING THE TEST ACCESS PORT It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid–level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a 1 k resistor. TDO should be left unconnected. TAP DC OPERATING CHARACTERISTICS (2.375 V ≤ VDD ≤ 3.6 V, 0°C ≤ TA ≤ 70°C, Unless Otherwise Noted) Parameter Symbol Min Max Unit Logic Input Logic High VIH1 1.2 VDD + 0.3 V Logic Input Logic Low VIL1 – 0.3 0.4 V Notes Ilkg — ±5 µA 1 CMOS Output Logic Low VOL1 — 0.2 V 2 CMOS Output Logic High VOH1 VDD – 0.2 — V 3 TTL Output Logic Low VOL2 — 0.4 V 4 TTL Output Logic High VOH2 2.4 — V 5 Logic Input Leakage Current NOTES: 1. 0 V ≤ Vin ≤ VDD for all logic input pins. 2. IOL1 ≤ 100 µA @ VOL = 0.2 V. Sampled, not 100% tested. 3. |IOH1| ≤ 100 µA @ VDDQ – 0.2 V. Sampled, not 100% tested. 4. IOL2 ≤ 8 mA @ VOL = 0.4 V. 5. |IOH2| ≤ 8 mA @ VOH = 2.4 V. MCM63R836•MCM63R918 14 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. TAP AC OPERATING CONDITIONS AND CHARACTERISTICS (2.375 V ≤ VDD ≤ 3.6 V, 0°C ≤ TA ≤ 70°C, Unless Otherwise Noted) Output Test Load . . . . . . 50 Ω Parallel Terminated T–line with 20 pF Receiver Input Capacitance Test Load Termination Supply Voltage (VT) . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V TAP CONTROLLER TIMING Freescale Semiconductor, Inc... Parameter Symbol Min Max Unit Cycle Time tTHTH 100 — ns Clock High Time tTHTL 40 — ns Clock Low Time tTLTH 40 — ns TMS Setup tMVTH 10 — ns TMS Hold tTHMX 10 — ns TDI Valid to TCK High tDVTH 10 — ns TCK High to TDI Don’t Care tTHDX 10 — ns tCS 10 — ns 1 1 Capture Setup Capture Hold tCH 10 — ns TCK Low to TDO Unknown tTLQX 0 — ns TCK Low to TDO Valid tTLOV — 20 ns Notes NOTE: 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure accurate pad data capture. AC TEST LOAD 1.5 V 50 Ω DEVICE UNDER TEST 50 Ω 20 pF TAP CONTROLLER TIMING DIAGRAM tTHTH tTLTH TEST CLOCK (TCK) tTHTL tTHMX tMVTH TEST MODE SELECT (TMS) tTHDX tDVTH TEST DATA IN (TDI) tTLQV tTLQX TEST DATA OUT (TDO) MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63R836•MCM63R918 15 Freescale Semiconductor, Inc. TEST ACCESS PORT PINS TCK — TEST CLOCK (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. Freescale Semiconductor, Inc... TMS — TEST MODE SELECT (INPUT) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic 1 input level. TDI — TEST DATA IN (INPUT) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (see Figure 6). An undriven TDI pin will produce the same result as a logic 1 input level. TDO — TEST DATA OUT (OUTPUT) Output that is active depending on the state of the TAP state machine (see Figure 6). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TRST — TAP RESET This device does not have a TRST pin. TRST is optional in IEEE 1149.1. The test–logic reset state is entered while TMS is held high for five rising edges of TCK. Power on reset circuitry is included internally. This type of reset does not affect the operation of the system logic. The reset affects test logic only. TEST ACCESS PORT REGISTERS OVERVIEW The various TAP registers are selected (one at a time) via the sequences of 1s and 0s input to the TMS pin as the TCK is strobed. Each of the TAPs registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on subsequent falling edge of TCK. When a register is selected it is “placed” between the TDI and TDO pins. INSTRUCTION REGISTER The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are 3 bits long. The register can be loaded when it is placed between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE instruction at power–up or whenever the controller is placed in test–logic–reset state. BOUNDARY SCAN REGISTER The boundary scan register is identical in length to the number of active input and I/O connections on the RAM (not counting the TAP pins). This also includes a number of place holder locations (always set to a logic 1) reserved for density upgrade address pins. There are a total of 70 bits in the case of the x36 device and 51 bits in the case of the x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture–DR state and then is placed between the TDI and TDO pins when the controller is moved to shift–DR state. Several TAP instructions can be used to activate the boundary scan register. The Bump/Bit Scan Order tables describe which device bump connects to each boundary scan register location. The first column defines the bit’s position in the boundary scan register. The shift register bit nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the input or I/O at the bump and the third column is the bump number. IDENTIFICATION (ID) REGISTER The ID register is a 32–bit register that is loaded with a device and vendor specific 32–bit code when the controller is put in capture–DR state with the IDCODE command loaded in the instruction register. The code is loaded from a 32–bit on–chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into shift–DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Presence Indicator Bit No. 0 Value 1 Motorola JEDEC ID Code (Compressed Format, per IEEE Standard 1149.1 – 1990 Bit No. 11 10 9 8 7 6 5 4 3 2 1 Value 0 0 0 0 0 0 0 1 1 1 0 Reserved For Future Use Bit No. 17 16 15 14 13 12 Value x x x x x x Configuration Bit No. 22 21 20 19 18 256K x 36 Value 0 0 1 0 0 512K x 18 Value 0 0 0 1 1 Configuration Bit No. 27 26 25 24 23 256K x 36 Value 0 0 1 1 0 512K x 18 Value 0 0 1 1 1 Device Width Device Depth Revision Number BYPASS REGISTER The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs TAP to another device in the scan chain with as little delay as possible. MCM63R836•MCM63R918 16 Bit No. 31 30 29 28 Value x x x x Figure 5. ID Register Bit Meanings For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MCM63R836 Bump/Bit Scan Order Bit No. Signal g Name Bump p ID Bit No. 1 M2 5R 2 SA 4P 3 SA 4 SA 5 SA MCM63R918 Bump/Bit Scan Order Signal g Name Bump p ID Bit No. Signal g Name Bump p ID Bit No. Signal g Name Bump p ID 36 SA 3B 1 M2 5R 36 SBb 3G 37 NC 2B 2 SA 6T 37 ZQ 4D 4T 38 SA 3A 3 SA 4P 38 SS 4E 6R 39 SA 3C 4 SA 6R 39 NC 4G 5T 40 SA 2C 5 SA 5T 40 NC 4H 6 ZZ 7T 41 SA 2A 6 ZZ 7T 41 SW 4M 7 DQa 6P 42 DQc 2D 7 DQa 7P 42 DQb 2K 8 DQa 7P 43 DQc 1D 8 DQa 6N 43 DQb 1L 9 DQa 6N 44 DQc 2E 9 DQa 6L 44 DQb 2M 10 DQa 7N 45 DQc 1E 10 DQa 7K 45 DQb 1N 11 DQa 6M 46 DQc 2F 11 SBa 5L 46 DQb 2P 12 DQa 6L 47 DQc 2G 12 CK 4L 47 SA 3T 13 DQa 7L 48 DQc 1G 13 CK 4K 48 SA 2R 14 DQa 6K 49 DQc 2H 14 G 4F 49 SA 4N 15 DQa 7K 50 DQc 1H 15 DQa 6H 50 SA 2T 16 SBa 5L 51 SBc 3G 16 DQa 7G 51 M1 3R 17 CK 4L 52 ZQ 4D 17 DQa 6F 18 CK 4K 53 SS 4E 18 DQa 7E 19 G 4F 54 NC 4G 19 DQa 6D 20 SBb 5G 55 NC 4H 20 SA 6A 21 DQb 7H 56 SW 4M 21 SA 6C 22 DQb 6H 57 SBd 3L 22 SA 5C 23 DQb 7G 58 DQd 1K 23 SA 5A 24 DQb 6G 59 DQd 2K 24 SA 6B 25 DQb 6F 60 DQd 1L 25 SA 5B 26 DQb 7E 61 DQd 2L 26 SA 3B 27 DQb 6E 62 DQd 2M 27 NC 2B 28 DQb 7D 63 DQd 1N 28 SA 3A 29 DQb 6D 64 DQd 2N 29 SA 3C 30 SA 6A 65 DQd 1P 30 SA 2C 31 SA 6C 66 DQd 2P 31 SA 2A 32 SA 5C 67 SA 3T 32 DQb 1D 33 SA 5A 68 SA 2R 33 DQb 2E 34 SA 6B 69 SA 4N 34 DQb 2G 35 SA 5B 70 M1 3R 35 DQb 1H NOTES: 1. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a “place holder” bit that is forced to logic 1. These pads are reserved for use as address inputs on higher density RAMs that follow this pad out and scan order standard. 2. In scan mode, differential inputs CK and CK are referenced to each other and must be at opposite logic levels for reliable operation. 3. ZQ, M1, and M2 are not ordinary inputs and may not respond to standard I/O logic levels. ZQ, M1, and M2 must be driven to within 100 mV of a VDD or VSS supply rail to ensure consistent results. 4. ZZ must remain at VIL during boundary scan to ensure consistent results. MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63R836•MCM63R918 17 Freescale Semiconductor, Inc. TAP CONTROLLER INSTRUCTION SET Freescale Semiconductor, Inc... OVERVIEW There are two classes of instructions defined in the IEEE Standard 1149.1–1990; the standard (public) instructions and device specific (private) instructions. Some public instructions, are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the IEEE 1149.1 conventions, it is not IEEE 1149.1 compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the RAM or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in capture–IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the shift–IR state the instruction register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to update–IR state. The TAP instruction sets for this device are listed in the following tables. STANDARD (PUBLIC) INSTRUCTIONS BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift–DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is an IEEE 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture–DR state, loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK), it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be MCM63R836•MCM63R918 18 expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup, plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift–DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the update–DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the pause–DR command. This functionality is not IEEE 1149.1 compliant. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented in this device. Therefore, this device is not IEEE 1149.1 compliant. Nevertheless, this RAMs TAP does respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the instruction register, the RAM responds just as it does in response to the SAMPLE/PRELOAD instruction described above, except the DQ pins are forced to high–Z any time the instruction is loaded. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture–DR mode and places the ID register between the TDI and TDO pins in shift–DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the test–logic–reset state. THE DEVICE SPECIFIC (PUBLIC) INSTRUCTION SAMPLE–Z If the SAMPLE–Z instruction is loaded in the instruction register, all DQ pins are forced to an inactive drive state (high–Z) and the boundary scan register is connected between TDI and TDO when the TAP controller is moved to the shift–DR state. THE DEVICE SPECIFIC (PRIVATE) INSTRUCTION NO OP Do not use these instructions; they are reserved for future use. For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. STANDARD (PUBLIC) INSTRUCTION CODES Instruction Code* EXTEST 000 IDCODE 001** Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all DQ pins to High–Z state. NOT IEEE 1149.1 COMPLIANT. Preloads ID register and places it between TDI and TDO. Does not affect RAM operation. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect RAM operation. Does not implement IEEE 1149.1 PRELOAD function. NOT IEEE 1149.1 COMPLIANT. BYPASS 111 Places bypass register between TDI and TDO. Does not affect RAM operation. SAMPLE–Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all DQ pins drivers to High–Z state. * Instruction codes expressed in binary; MSB on left, LSB on right. ** Default instruction automatically loaded at power–up and in test–logic–reset state. Freescale Semiconductor, Inc... STANDARD (PRIVATE) INSTRUCTION CODES Instruction Code* Description NO OP 011 Do not use these instructions; they are reserved for future use. NO OP 101 Do not use these instructions; they are reserved for future use. NO OP 110 Do not use these instructions; they are reserved for future use. * Instruction codes expressed in binary; MSB on left, LSB on right. 1 TEST–LOGIC RESET 0 RUN–TEST/ IDLE 0 1 SELECT DR–SCAN SELECT IR–SCAN 1 0 1 1 0 1 CAPTURE–DR CAPTURE–IR 0 0 SHIFT–DR SHIFT–IR 0 1 0 1 1 1 EXIT1–DR EXIT1–IR 0 0 PAUSE–DR PAUSE–IR 0 1 0 EXIT2–DR 0 EXIT2–IR 1 1 UPDATE–DR 1 0 1 0 UPDATE–IR 1 0 NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK. Figure 6. TAP Controller State Diagram MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63R836•MCM63R918 19 Freescale Semiconductor, Inc. ORDERING INFORMATION (Order by Full Part Number) 63R836 63R918 MCM XX X X Motorola Memory Prefix R = Tape and Reel, Blank = Tray Part Number Speed (3.0= 3.0 ns, 3.3 = 3.3 ns, 3.7 = 3.7 ns, 4.0 = 4.0 ns) Package (FC = Flipped Chip PBGA) Full Part Numbers — MCM63R836FC3.0 MCM63R836FC3.3 MCM63R836FC3.7 MCM63R836FC4.0 MCM63R918FC3.0 MCM63R918FC3.3 MCM63R918FC3.7 MCM63R918FC4.0 MCM63R836FC3.0R MCM63R836FC3.3R MCM63R836FC3.7R MCM63R836FC4.0R MCM63R918FC3.0R MCM63R918FC3.3R MCM63R918FC3.7R MCM63R918FC4.0R Freescale Semiconductor, Inc... PACKAGE DIMENSIONS FC PACKAGE 7 X 17 BUMP PBGA CASE 999D–01 0.2 4X C E PIN A1 INDEX B 0.2 A E3 5 0.25 A D3 SEATING PLANE D2 0.35 A D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M,1992. 2. ALL DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM PLANE A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. AN AI INDEX MARK WILL BE LOCATED IN THIS AREA. 6. D2 AND E2 DEFINE THE AREA OCCUPIED BY THE DIE. D3 AND E3 ARE THE MINIMUM CLEARANCE FROM THE PACKAGE EDGE TO THE CHIP CAPACITORS. 7. CAPACITORS MAY NOT BE PRESENT ON ALL DEVICES. 8. CAUTION MUST BE TAKEN NOT TO SHORT EXPOSED METAL CAPACITOR PADS ON PACKAGE TOP. E2 TOP VIEW E1 6X U T R P N M L K J H G F E D C B A e 16X e A4 A3 A2 D1 A1 DIM A A1 A2 A3 A4 D D1 D2 D3 E E1 E2 E3 b e MILLIMETERS MIN MAX ––– 2.77 0.50 0.70 1.75 2.07 0.80 0.92 0.92 1.15 22.00 BSC 20.32 BSC 12.10 12.40 1.10 14.00 BSC 7.62 BSC 7.26 7.46 1.10 0.60 0.90 1.27 BSC A SIDE VIEW 1 2 3 4 5 6 7 119X BOTTOM VIEW b 3 0.3 0.15 MCM63R836•MCM63R918 20 M M A B C A For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE : http://motorola.com/semiconductors / MOTOROLA FAST SRAM JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong. 852-26668334 ◊For More Information On This Product, Go to: www.freescale.com MCM63R836/D MCM63R836•MCM63R918 21