FUJITSU SEMICONDUCTOR DATA SHEET DS05-11424-4E MEMORY Mobile FCRAMTM CMOS 16 Mbit (1 M word × 16 bit) Mobile Phone Application Specific Memory MB82D01181E-60L ■ DESCRIPTION MB82D01181E is a Fast Cycle Random Access Memory (FCRAM) with asynchronous Static Random Access Memory (SRAM) interface containing 16,777,216 storages accessible in a 16-bit format. MB82D01181E is suited for mobile applications such as Cellular Handset and PDA. Note: FCRAM is a trademark of Fujitsu Limited, Japan. ■ FEATURES • • • • • • • • • • • Asynchronous SRAM Interface 1 M word × 16 bit Organization Low-voltage Operating Conditions Wide Operating Temperature Read/Write Cycle Time Fast Random Access Time Active current Standby current Power down current Byte Control Shipping Form : VDD = 2.3 V to 3.5 V : TA = 0 °C to + 70 °C : tRC = tWC = 70 ns Min : tAA = tCE = 60 ns Max : IDDA1 = 20 mA Max : IDDs1 = 100 µA Max (VDD ≤ 3.1 V) : IDDP = 10 µA Max : Wafer/Chip, 48-pin plastic FBGA Copyright©2004-2006 FUJITSU LIMITED All rights reserved MB82D01181E-60L ■ PIN ASSIGNMENT (TOP VIEW) 1 2 3 4 5 6 A LB OE A0 A1 A2 CE2 B DQ9 UB A3 A4 CE1 DQ1 C DQ10 DQ11 A5 A6 DQ2 DQ3 D VSS DQ12 A17 A7 DQ4 VDD E VDD DQ13 NC A16 DQ5 VSS F DQ15 DQ14 A14 A15 DQ6 DQ7 G DQ16 A19 A12 A13 WE DQ8 H A18 A8 A9 A10 A11 NC (BGA-48P-M18) SRAM compatible FBGA (suffix PBN) ■ PIN DESCRIPTION Pin Name A19 to A0 2 Description Address Input CE1 Chip Enable (Low Active) CE2 Chip Enable (High Active) WE Write Enable (Low Active) OE Output Enable (Low Active) LB Lower Byte Control (Low Active) UB Upper Byte Control (Low Active) DQ8 to DQ1 Lower Byte Data Input/Output DQ16 to DQ9 Upper Byte Data Input/Output VDD Power Supply VSS Ground NC No Connection MB82D01181E-60L ■ BLOCK DIAGRAM VDD VSS A19 to A0 Address Latch & Buffer DQ8 to DQ1 I/O Buffer DQ16 to DQ9 Row Decoder Input Data Latch & Control Memory Cell Array 16,777,216 bits Sense / Switch Output Data Control Column Decoder Address Latch & Buffer CE2 CE1 Power Control Timing Control WE LB UB OE 3 MB82D01181E-60L ■ FUNCTION TRUTH TABLE Mode CE2 CE1 WE OE LB UB X X X X X High-Z High-Z H H X X *3 High-Z High-Z No Read H H Valid High-Z High-Z Read (Upper Byte) H L Valid High-Z Output Valid L H Valid Output Valid High-Z L L Valid Output Valid Output Valid No Write H H Valid Invalid Invalid Write (Upper Byte) H L Valid Invalid Input Valid L H Valid Input Valid Invalid L L Valid Input Valid Input Valid X X X High-Z High-Z Standby (Deselect) H Output Disable*1 H Read (Lower Byte) Read (Word) H L L L Write (Lower Byte) H Write (Word) Power Down *2 L X X X A19 to A0 DQ8 to DQ1 DQ16 to DQ9 Note : L = VIL, H = VIH, X = either VIL or VIH, High-Z = High impedance *1 : Output disable mode should not be kept longer than 1 µs. *2 : Power down mode can be entered from standby state and all DQ pins are in High-Z state. *3 : Can be either VIL or VIH but must be valid before read or write. 4 IDD Data Retention IDDS IDDA IDDP Yes No MB82D01181E-60L ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Min Max Unit Supply Voltage * VDD −0.5 +3.6 V Input Voltage * VIN −0.5 +3.6 V Output voltage * VOUT −0.5 +3.6 V Short Circuit Output Current IOUT −50 +50 mA Storage Temperature TSTG −55 +125 °C * : All voltages are referenced to VSS. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Min Max VDD (31) 3.1 3.5 V VDD (27) 2.7 3.1 V VDD (23) 2.3 2.7 V VSS 0 0 V VIH (31) VDD × 0.8 VDD + 0.2 and ≤ 3.5 V VIH (23, 27) VDD × 0.8 VDD + 0.2 V Low Level Input Voltage *1, *4 VIL −0.3 VDD × 0.2 V Ambient Temperature TA 0 +70 °C Supply Voltage *1, *2 High Level Input Voltage *1, *2, *3 *1 : All voltages are referenced to VSS. *2 : This device supports three voltage ranges, VDD (31) , VDD (27) , and VDD (23) on identical device. VDD range is divided into three ranges on the table due to VIH varied according to VDD supply voltage. *3 : Overshoot spec. (VIH (Max) = VDD + 1.0 V, pulse width ≤ 5.0 ns) *4 : Undershoot spec. (VIL (Min) = − 1.0 V, pulse width ≤ 5.0 ns) WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 5 MB82D01181E-60L ■ PIN CAPACITANCE Parameter Symbol Conditions Min (f = 1.0 MHz, TA = +25 °C) Value Unit Typ Max Address Input Capacitance CIN1 VIN = 0 V ⎯ ⎯ 5 pF Control Input Capacitance CIN2 VIN = 0 V ⎯ ⎯ 5 pF Data Input/Output Capacitance CIO VIO = 0 V ⎯ ⎯ 8 pF ■ DC CHARACTERISTICS Parameter Symbol Value Conditions Max Unit Input Leakage Current ILI VSS ≤ VIN ≤ VDD −1.0 +1.0 µA Output Leakage Current ILO VSS ≤ VOUT ≤ VDD, Output Disable −1.0 +1.0 µA VOH(31) VDD = VDD(31) Min, IOH = −0.5 mA 2.5 ⎯ V VOH(27) VDD = VDD(27) Min, IOH = −0.5 mA 2.2 ⎯ V VOH(23) VDD = VDD(23) Min, IOH = −0.5 mA 1.8 ⎯ V Output High Voltage Level Output Low Voltage Level VOL IOL = 1 mA ⎯ 0.4 V VDD Power Down Current IDDP VDD = VDD Max, VIN = VIH or VIL, CE2 ≤ 0.2 V ⎯ 10 µA VDD = VDD(31) Max, VIN = VIH or VIL, CE1 = CE2 = VIH ⎯ 2.0 VDD = VDD(27, 23) Max, VIN = VIH or VIL, CE1 = CE2 = VIH ⎯ 1.0 VDD = VDD(31) Max, VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, CE1 = CE2 ≥ VDD − 0.2 V ⎯ 150 VDD = VDD(27, 23) Max, VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, CE1 = CE2 ≥ VDD − 0.2 V ⎯ 100 ⎯ 20 IDDS VDD Standby Current IDDS1 VDD Active Current IDDA1 VDD = VDD Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA tRC / tWC = Min mA µA mA tRC / tWC = 1 µs Notes: • All voltages are referenced to Vss. • DC Characteristics are measured after following POWER-UP timing. • IOUT depends on the output load conditions. 6 Min ⎯ 3.0 MB82D01181E-60L ■ AC CHARACTERISTICS (1) Read Operation Parameter Symbol Value Min Max Unit Notes Read Cycle Time tRC 70 1000 ns *1, *2 CE1 Access Time tCE ⎯ 60 ns *3 OE Access Time tOE ⎯ 40 ns *3 Address Access Time tAA ⎯ 60 ns *3, *5 LB, UB Access Time tBA ⎯ 30 ns *3 Output Data Hold Time tOH 5 ⎯ ns *3 CE1 Low to Output Low-Z tCLZ 5 ⎯ ns *4 OE Low to Output Low-Z tOLZ 0 ⎯ ns *4 LB, UB Low to Output Low-Z tBLZ 0 ⎯ ns *4 CE1 High to Output High-Z tCHZ ⎯ 20 ns *3 OE High to Output High-Z tOHZ ⎯ 20 ns *3 LB, UB High to Output Low-Z tBHZ ⎯ 20 ns *3 Address Setup Time to CE1 Low tASC −5 ⎯ ns Address Setup Time to OE Low tASO 10 ⎯ ns Address Invalid Time tAX ⎯ 10 ns *5 Address Hold Time from CE1 High tCHAH −5 ⎯ ns *6 Address Hold Time from OE High tOHAH −5 ⎯ ns WE High to OE Low Time for Read tWHOL 10 1000 ns tCP 10 ⎯ ns CE1 High Pulse Width *7 *1 : Maximum value is applicable if CE1 is kept at Low without any address change. *2 : Address should not be changed within minimum tRC. *3 : The output load 50 pF with 50 Ω termination to VDD × 0.5 V. *4 : The output load 5 pF without any other load. *5 : Applicable when CE1 is kept at Low. *6 : tRC (Min) must be satisfied. *7 : If the actual value of tWHOL is shorter than specified minimum value, the actual tAA of following Read may become longer by the amount of subtracting actual value from specified minimum value. 7 MB82D01181E-60L (2) Write Operation Value Parameter Symbol Unit Min Max Notes Write Cycle Time tWC 70 1000 ns *1, *2 Address Setup Time tAS 0 ⎯ ns *2 CE1 Write Pulse Width tCW 45 ⎯ ns *3 WE Write Pulse Width tWP 45 ⎯ ns *3 LB, UB Write Pulse Width tBW 45 ⎯ ns *3 LB, UB Byte Mask Setup Time tBS −5 ⎯ ns *4 LB, UB Byte Mask Hold Time tBH −5 ⎯ ns *5 Write Recovery Time tWR 0 ⎯ ns *6 CE1 High Pulse Width tCP 10 ⎯ ns WE High Pulse Width tWHP 10 1000 ns LB, UB High Pulse Width tBHP 10 1000 ns Data Setup Time tDS 15 ⎯ ns Data Hold Time tDH 0 ⎯ ns OE High to Address Setup Time for Write tOES 0 ⎯ ns *8 OE High to CE1 Low Setup Time for Write tOHCL −5 ⎯ ns *7 LB and UB Write Pulse Overlap tBWO 30 ⎯ ns *1 : Maximum value is applicable if CE1 is kept at Low without any address change. *2 : Minimum value must be equal or greater than the sum of write pulse width (tCW, tWP or tBW) and write recovery time (tWR) . *3 : Write pulse width is defined from High to Low transition of CE1, WE, LB or UB, whichever occurs last. *4 : Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1 or WE whichever occurs last. *5 : Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE whichever occurs first. *6 : Write recovery time is defined from Low to High transition of CE1, WE, LB or UB, whichever occurs first. *7 : If OE is Low after minimum tOHCL, read cycle is initiated. In other words, OE must be brought to High within 5 ns after CE1 is brought to Low. *8 : If OE is Low after new address input, read cycle is initiated. In other words, OE must be brought to High at the same time or before new address valid. Note : AC Characteristics are measured after following POWER-UP timing. 8 MB82D01181E-60L (3) Power Down Parameters Parameter Value Symbol Min Max Unit CE2 Low Setup Time for Power Down Entry tCSP 10 ⎯ ns CE2 Low Hold Time after Power Down Entry tC2LP 80 ⎯ ns CE1 High Hold Time following CE2 High after Power Down Exit tCHH 300 ⎯ µs CE1 High Setup Time following CE2 High after Power Down Exit tCHS 0 ⎯ ns Note * * : Applicable also to power-up. (4) Other Timing Parameters Parameter Value Symbol Min Max Unit CE1 High to OE Invalid Time for Standby Entry tCHOX 10 ⎯ ns CE1 High to WE Invalid Time for Standby Entry tCHWX 10 ⎯ ns CE2 Low Hold Time after Power-up tC2LH 50 ⎯ µs CE1 High Hold Time following CE2 High after Power-up tCHH 300 ⎯ µs tT 1 25 ns Input Transition Time Note *1 *2 *1: Some data might be written into any address location if tCHWX (Min) is not satisfied. *2: The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns, it may violate AC specifications of some timing parameters. (5) AC Test Conditions Parameter Symbol Conditions Measured Value Unit Input High Level VIH ⎯ VDD × 0.8 V Input Low level VIL ⎯ VDD × 0.2 V VREF ⎯ VDD × 0.5 V 5 ns Input Timing Measurement Level Input Transition Time tT Between VIL and VIH Note (6) AC Measurement Output Load Circuit VDD 0.5 V 50 VDD 0.1 F VSS Device Under Test OUT 50 pF 9 MB82D01181E-60L ■ TIMING DIAGRAM 1. READ Timing 1 (Basic Timing) tRC Address Address Valid tASC tCHAH tCE tASC CE1 tCP tOE tCHZ OE tOHZ tBA LB, UB tBHZ tBLZ tOLZ DQ (Output) tCLZ tOH Valid Data Output Note : This timing diagram assumes CE2 = “H” and WE = “H”. 2. READ Timing 2 (OE & Address Access) tAX tRC Address Address Valid Address Valid tAA CE1 tRC tAA tOHAH Low tOE tASO OE LB, UB tOLZ tOH DQ tOHZ tOH (Output) Valid Data Output Note : This timing diagram assumes CE2 = “H” and WE = “H”. 10 Valid Data Output MB82D01181E-60L 3. READ Timing 3 (LB, UB Byte Access) tAX tRC Address tAX Address Valid tAA CE1, OE Low tBA tBA LB tBA UB tBHZ tBHZ tBLZ tOH tBLZ tOH DQ8 to DQ1 (Output) Valid Data Output tBLZ DQ16 to DQ9 Valid Data Output tOH tBHZ (Output) Valid Data Output Note : This timing diagram assumes CE2 = “H” and WE = “H”. 4. WRITE Timing 1 (Basic Timing) tWC Address Address Valid tAS tWR tCW CE1 tAS tCP tWP tAS tWR WE tAS tWHP tAS tBW tWR LB, UB tAS tBHP tOHCL OE tDS tDH DQ (Input) Valid Data Input Note : This timing diagram assumes CE2 = “H”. 11 MB82D01181E-60L 5. WRITE Timing 2 (WE Control) Address tWC tWC Address Valid Address Valid tOHAH CE1 Low tAS tWP tWR tAS tWP tWR WE tWHP LB, UB tOES OE tOHZ tDS tDH tDS tDH DQ (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = “H”. 6. WRITE Timing 3-1 (WE, LB, UB Byte Write Control) tWC tWC Address CE1 Address Valid Address Valid Low tAS tWP tAS tWP tWHP WE tWR tBH tBS LB tBS tWR tBH UB tDS tDH DQ8 to DQ1 (Input) DQ16 to DQ9 Valid Data Input tDS tDH (Input) Valid Data Input Note : This timing diagram assumes CE2 = “H” and OE = “H”. 12 MB82D01181E-60L 7. WRITE Timing 3-2 (WE, LB, UB Byte Write Control) Address CE1 tWC tWC Address Valid Address Valid Low tWR tWR tWHP WE tAS tBW tBS tBH LB tBS tAS tBH tBW UB tDS tDH DQ8 to DQ1 (Input) tDS Valid Data Input DQ16 to DQ9 tDH (Input) Valid Data Input Note : This timing diagram assumes CE2 = “H” and OE = “H”. 8. WRITE Timing 3-3 (WE, LB, UB Byte Write Control) tWC Address CE1 tWC Address Valid Address Valid Low WE tWHP tAS tBW tWR tBS tBH LB tBS tBH tAS tBW tWR UB tDS tDH DQ8 to DQ1 (Input) DQ16 to DQ9 Valid Data Input tDS tDH (Input) Valid Data Input Note : This timing diagram assumes CE2 = “H” and OE = “H”. 13 MB82D01181E-60L 9. WRITE Timing 3-4 (WE, LB, UB Byte Write Control) tWC tWC Address CE1 Address Valid Address Valid Low WE tAS tBW tWR tBW tAS tWR tBHP LB tBWO tDS DQ8 to DQ1 tDH tDS Valid Data Input Valid Data Input (Input) tAS tBW tAS tWR UB tDH tWR tBWO tBW tBHP tDS DQ16 to DQ9 tDH tDS Valid Data Input (Input) tDH Valid Data Input Note : This timing diagram assumes CE2 = “H” and OE = “H”. 10. READ/WRITE Timing 1-1 (CE1 Control) tWC Address tRC Read Address Write Address tCHAH tAS tCW tWR tASC tCE tCHAH CE1 tCP tCP WE UB, LB tOHCL OE tCHZ tOH tDS tDH tCLZ tOH DQ Read Data Output Write Data Input Note : This timing diagram assumes CE2 = “H”. Write address is valid from either CE1 or WE of last falling edge. 14 Read Data Output MB82D01181E-60L 11. READ/WRITE Timing 1-2 (CE1, WE, OE Control) tWC Address tRC Write Address tCHAH Read Address tAS tWR tASC tCE tCHAH CE1 tCP tCP tWP WE UB, LB tOHCL tOE OE tCHZ tOH tDS tDH tOLZ tOH DQ Read Data Output Read Data Output Write Data Input Note : This timing diagram assumes CE2 = “H”. OE can be fixed Low during write operation if it is CE1 controlled write at Read-Write-Read sequence. 12. READ/WRITE Timing 2 (OE, WE Control) Address tWC tRC Write Address Read Address tOHAH CE1 Low tAS WE tOHAH tAA tWP tWR tOES UB, LB tOE tASO OE tWHOL tOHZ tOH tDS tDH tOLZ tOHZ tOH DQ Read Data Output Write Data Input Read Data Output Note : This timing diagram assumes CE2 = “H”. CE1 can be tied to Low for WE and OE controlled operation. 15 MB82D01181E-60L 13. READ/WRITE Timing 3 (OE, WE, LB, UB Control) Address tWC tRC Write Address Read Address tAA CE1 Low tOHAH tOHAH WE tOES tAS tWR tBW tBA UB, LB tASO tBHZ OE tWHOL tOH tDS tDH tBLZ tBHZ tOH DQ Read Data Output Write Data Input Note : This timing diagram assumes CE2 = “H”. CE1 can be tied to Low for WE and OE controlled operation. 16 Read Data Output MB82D01181E-60L 14. POWER-UP Timing 1 CE1 tCHS tC2LH tCHH CE2 VDD VDD (Min) 0V Note : tC2LH specifies after VDD reaches specified minimum level. 15. POWER-UP Timing 2 CE1 tCHH CE2 VDD VDD (Min) 0V Note : tCHH specifies after VDD reaches specified minimum level and applicable to both CE1 and CE2. If transition time of VDD (from 0 V to VDD Min) is longer than 100 ms, POWER-UP Timing#1 must be applied. 17 MB82D01181E-60L 16. POWER DOWN Entry and Exit Timing CE1 tCHS CE2 tCSP tC2LP tCHH High-Z DQ Power Down Entry Power Down Mode Power Down Exit Note : This Power Down mode can be also used as a reset timing if POWER-UP timing could not be satisfied. 17. Standby Entry Timing after Read or Write CE1 tCHOX tCHWX OE WE Active (Read) Standby Active (Write) Standby Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (Min) period for Standby mode from CE1 Low to High transition. 18 MB82D01181E-60L ■ BONDING PAD INFORMATION Please contact local FUJITSU representative for pad layout and pad coordinate information. ■ ORDERING INFORMATION Part No. Shipping Form/Package MB82D01181E-60LWT Wafer MB82D01181E-60LPBN 48-pin plastic FBGA (BGA-48P-M18) Remarks SRAM compatible FBGA package tCE = 60 ns Max 19 MB82D01181E-60L ■ PACKAGE DIMENSION 48-pin plastic FBGA Ball pitch 0.75 mm Package width × package length 6.00 × 9.00 mm Lead shape Fine pitch ball Sealing method Plastic mold Mounting height 1.20 mm MAX Weight 0.10 g (BGA-48P-M18) 48-pin plastic FBGA (BGA-48P-M18) +0.15 1.05 –0.10 +.006 (Mounting height) .041 –.004 9.00±0.10(.354±.004) (5.25(.207)) 0.25±0.10 (.010±.004) (Stand off) 0.75(.030) TYP 6 5 6.00±0.10 (.236±.004) 4 (3.75(.148)) 3 2 1 0.75(.030) TYP INDEX AREA H G F E D C B A 48-ø0.35±0.10 (48-ø.014±.004) INDEX MARK 0.08(.003) M 0.20(.008) S S 0.10(.004) S C 20 2001 FUJITSU LIMITED B48018S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. MB82D01181E-60L FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept. F0607