ICS ICS81006AKLFT

ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
GENERAL DESCRIPTION
FEATURES
The ICS81006 is a high performance, low
jitter/low phase noise VCXO and is a
HiPerClockS™
member of the HiPerClockS™ family of high
performance clock solutions from ICS. The
ICS81006 works in conjunction with a
pullable crystal to generate an output clock over the
range of 12MHz - 40MHz and has 6 LVCMOS outputs,
effectively integrating a fanout buffer function.
• Six LVCMOS/LVTTL outputs, 20Ω nominal
output impedance
ICS
• Output Q5 can be selected for ÷1 or ÷2 frequency relative
to the crystal frequency
• Output frequency range: 12MHz to 40MHz
• Crystal pull range: ± 90ppm (typical)
• Synchronous output enable places outputs in High-Z state
The frequency of the VCXO is adjusted by the VC control
voltage input. The output range is ±100ppm around the
nominal crystal frequency. The VC control voltage range
is 0 - V DD. The device is packaged in a small 4mm x 4mm
VFQFN package and is ideal for use on space
constrained boards typically encountered in ADSL/
VDSL applications.
• On-chip filter on VIN to suppress noise modulation of VCXO
• VDD/VDDO combinations
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• 4mm x 4mm 20 Lead VFQFN package is ideal for space
constrained designs
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
VCXO
Q2
XTAL_OUT
Q1
VDDO
20 19 18 17 16
15
XTAL_OUT
2
14
Q2
VDD
3
13
VDDO
VC
4
12
Q3
DIV_SEL_Q5
5
6
7
8
9
11
10
Q4
XTAL_IN
1
Q5
Q1
XTAL_IN
VDDO
Q0
LP Filter
Q0
OE0
SYNC
OE1
VC
(Pullup)
GND
OE0
PIN ASSIGNMENT
GND
BLOCK DIAGRAM
GND
GND
Q3
ICS81006
Q4
0: ÷1
1: ÷2
DIV_SEL_Q5
OE1
81006AK
20-Lead VFQFN
4mm x 4mm x 0.95 package body
K Package
Top View
Q5
(Pulldown)
(Pullup)
SYNC
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1
REV. A JANUARY 4, 2006
ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
TABLE 1. PIN DESCRIPTIONS
Number
3
Name
XTAL_IN,
XTAL_OUT
VDD
Power
4
VC
Input
1, 2
Type
Input
Description
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Core supply pin.
Control voltage input.
Output divider select pin for Q5 output. When LOW, ÷1. When HIGH,
5
DIV_SEL_Q5 Input Pulldown
÷2, LVCMOS/LVTTL interface levels.
Output enable pin. When HIGH, Q5 output is enabled.
6
OE1
Input
Pullup
When LOW, forces Q5 to HiZ state. LVCMOS/LVTTL interface levels.
7, 11, 15, 19
GND
Power
Power supply ground.
8, 10, 12,
Q5, Q4, Q3,
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output
14, 16, 18
Q2, Q1, Q0
15Ω typical output impedance.
9, 13, 17
VDDO
Power
Output supply pins.
Output enable pin. When HIGH, Q0:Q4 outputs are enabled. When
20
OE0
Input
Pullup
LOW, forces Q0:Q4 to HiZ state. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
CPD
Test Conditions
Minimum
OE0, OE1
Power Dissipation Capacitance
Typical
Maximum
4
Units
pF
VDD = VDDO = 3.465V
3
pF
VDD = 3.465V or 2.625V,
VDDO = 2.625V
4
pF
VDD = 3.465V or 2.625V,
VDDO = 2V
6
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
ROUT
Output Impedance
81006AK
VDDO = 3.3V
20
Ω
VDDO = 2.5V
25
Ω
VDDO = 1.8V
38
Ω
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REV. A JANUARY 4, 2006
ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA
38.5°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 3.3V±5% = 2.5V±5% = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
Test Conditions
3.135
3.3
3.465
V
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
1.6
1.8
2.0
V
IDD
Power Supply Current
50
mA
IDDO
Output Supply Current
20
mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 2.5V±5% = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2. 5
2.625
V
2.375
2. 5
2.625
V
1.6
1.8
2.0
V
VDDO
Output Supply Voltage
IDD
Power Supply Current
50
mA
IDDO
Output Supply Current
20
mA
Maximum
Units
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = 0°C TO 85°C
Symbol
Parameter
Test Conditions
VIH
Input High Voltage
VIL
Input Low Voltage
VC
VCXO Control Voltage
IIH
Input High Current
OE0, OE1,
DIV_SEL_Q5
2
VDD + 0.3
V
VDD = 2.5V ± 5%
1.7
VDD + 0.3
V
VDD = 3.3V ± 5%
-0.3
0.8
V
VDD = 2.5V ± 5%
-0.3
0.7
V
0
VDD
V
15 0
µA
VDD = 3.3V or 2.5V ± 5%
OE0, OE1
VDD = 3.3V or 2.5V ± 5%
DIV_SEL_Q5
VDD = 3.3V or 2.5V ± 5%
-5
OE0, OE1
VDD = 3.3V or 2.5V ± 5%
-150
VDD = 3.465V or 2.625V
-100
VDDO = 3.3V ± 5%
2.6
V
VDDO = 2.5V ± 5%
1.8
V
VDDO = 1.8V ± 0.2V
1.5
V
Input Low Current
II
Input Current of VC pin
VOL
Typical
VDD = 3.3V ± 5%
DIV_SEL_Q5
IIL
VOH
Minimum
Output High Voltage;NOTE 1
Output Low Voltage;NOTE 1
5
µA
µA
µA
100
µA
VDDO = 3.3V or 2.5V ± 5%
0.5
V
VDDO = 1.8V ± 0.2V
0.4
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
81006AK
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REV. A JANUARY 4, 2006
ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fOUT
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Q0:Q4
Output Skew;
NOTE 2, 3
Q0:Q5
t jit(Ø)
tsk(o)
tR / tF
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Maximum
Units
12
19.44
40
MHz
Integration Range: 1kHz- 1MHz
0.35
ps
30
DIV_SEL_Q5 = ÷1
20% to 80%
200
odc
Output Duty Cycle
44
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
ps
100
ps
700
ps
56
%
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fOUT
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Q0:Q4
Output Skew;
NOTE 2, 3
Q0:Q5
t jit(Ø)
tsk(o)
t R / tF
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Maximum
Units
12
19.44
40
MHz
Integration Range: 1kHz- 1MHz
0.38
DIV_SEL_Q5 = ÷1
20% to 80%
300
odc
Output Duty Cycle
45
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
ps
20
ps
90
ps
800
ps
55
%
TABLE 4C. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
Parameter
fOUT
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Q0:Q4
Output Skew;
NOTE 2, 3
Q0:Q5
t jit(Ø)
tsk(o)
t R / tF
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Maximum
Units
12
19.44
40
MHz
Integration Range: 1kHz-1MHz
0.27
46
DIV_SEL_Q5 = ÷1
20% to 80%
450
odc
Output Duty Cycle
44
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
81006AK
ps
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4
ps
175
ps
1400
ps
56
%
REV. A JANUARY 4, 2006
ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
TABLE 4D. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fOUT
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Q0:Q4
Output Skew;
NOTE 2, 3
Q0:Q5
t jit(Ø)
tsk(o)
tR / tF
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Maximum
Units
12
19.44
40
MHz
Integration Range: 1kHz-1MHz
0.28
ps
25
DIV_SEL_Q5 = ÷1
20% to 80%
300
odc
Output Duty Cycle
45
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
ps
100
ps
800
ps
55
%
TABLE 4E. AC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
Parameter
fOUT
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Q0:Q4
Output Skew;
NOTE 2, 3
Q0:Q5
t jit(Ø)
tsk(o)
tR / tF
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Maximum
Units
12
19.44
40
MHz
Integration Range: 1kHz-1MHz
0.26
DIV_SEL_Q5 = ÷1
20% to 80%
450
odc
Output Duty Cycle
40
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
81006AK
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5
ps
40
ps
175
ps
1400
ps
60
%
REV. A JANUARY 4, 2006
ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
TYPICAL PHASE NOISE
AT
19.44MHZ @ 3.3V CORE/3.3V OUTPUT
0
-10
-20
-30
19.44MHz
-40
RMS Phase Jitter (Random)
1kHz to 1MHz = 0.35ps (typical)
-50
NOISE POWER dBc
Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
OFFSET FREQUENCY (HZ)
81006AK
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REV. A JANUARY 4, 2006
ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
2.05V±5% 1.25V±5%
SCOPE
VDD,
VDDO
LVCMOS
SCOPE
VDD
VDDO
Qx
Qx
LVCMOS
GND
GND
-1.65V±5%
-1.25V±5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V±5%
2.4V±0.065V 0.9V±0.1V
SCOPE
VDD
VDDO
LVCMOS
SCOPE
VDD,
VDDO
Qx
Qx
LVCMOS
GND
GND
-1.25V±5%
-0.9V±0.1V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.6V±0.025V 0.9V±0.1V
Noise Power
Phase Noise Plot
SCOPE
VDD
VDDO
LVCMOS
Qx
Phase Noise Mask
GND
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-0.9V±0.1V
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
81006AK
RMS PHASE JITTER
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REV. A JANUARY 4, 2006
ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
V
V
DD
DDO
Qx
2
2
Q0:Q5
t PW
t
V
DDO
Qy
2
tsk(o)
odc =
PERIOD
t PW
x 100%
t PERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
Clock
Outputs
80%
20%
20%
tR
tF
OUTPUT RISE/FALL TIME
81006AK
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REV. A JANUARY 4, 2006
ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
APPLICATION INFORMATION
VCXO CRYSTAL SELECTION
range and accuracy of a VCXO. Below are the key variables
and an example of using the crystal parameters to calculate
the tuning range of the VCXO.
Choosing a crystal with the correct characteristics is one of
the most critical steps in using a Voltage Controlled Crystal
Oscillator (VCXO). The crystal parameters affect the tuning
VC
➤
Oscillator
Control Voltage
➤
CV
➤C
V
VCXO (Internal)
XTAL
C S1
C S2
➤
C L1
➤
C L2
Optional
FIGURE 1: VCXO OSCILLATOR CIRCUIT
CL1, CL2 Load tuning capacitance used for fine tuning or
centering nominal frequency
VC Control voltage used to tune frequency
C V Varactor capacitance, varies due to the change in
control voltage
CS1, CS2 Stray Capacitance caused by pads, vias, and other
board parasitics
TABLE 5. EXAMPLE CRYSTAL PARAMETERS
Symbol
Parameter
fN
Nominal Frequency
Test Conditions
Minimum
Typical
Maximum
19.44
Units
MHz
fT
Frequency Tolerance
±20
ppm
fS
Frequency Stability
±20
ppm
70
°C
Operating Temperature Range
0
CL
Load Capacitance
12
pF
CO
Shunt Capacitance
4
pF
C0, C1
Pullability Ratio
ESR
Equivalent Series Resistance
220
20
Drive Level
1
Aging @ 25°C
±3 per year
mW
ppm
Fundamental
Mode of Operation
81006AK
240
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REV. A JANUARY 4, 2006
ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
TABLE 6. VARACTOR PARAMETERS
Symbol
Parameter
CV_LOW
Low Varactor Capacitance
Test Conditions
VC = 0V
Minimum
15.4
pF
CV_HIGH
High Varactor Capacitance
VC = 3.3V
29. 6
pF
FORMULAS
C Low =
(C
(C
L1
L1
+ C S 1 + CV _ Low ) ⋅ (C L 2 + C S 2 + CV _ Low )
C High =
+ C S 1 + CV _ Low ) + (C L 2 + C S 2 + CV _ Low )
(C
(C
L1
Typical
Maximum
Units
+ C S1 + CV _ High ) ⋅ (C L 2 + C S 2 + CV _ High )
L1 + C S 1 + CV _ High ) + (C L 2 + C S 2 + CV _ High )
• CLow is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance.
CLow determines the high frequency component on the TPR.
• CHigh is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance.
CHigh determines the low frequency component on the TPR.
⎛
⎞
⎜
⎟
1
1
⎜
⎟ ⋅ 10 6
−
Total Pull Range (TPR ) =
⎜
⎟
C Low ⎞
C
⎛
⎞
⎛
C
0
High
⎟ 2 ⋅ C 0 C 1 ⋅ ⎜1 +
⎜ 2 ⋅ C 1 ⋅ ⎜1 +
⎟⎟
C
0
0
C
⎝
⎠
⎝
⎠⎠
⎝
Absolute Pull Range (APR) = Total Pull Range – (Frequency Tolerance + Frequency Stability + Aging)
EXAMPLE CALCULATIONS
the inaccuracy due to aging is ±15ppm. Third, though many
boards will not require load tuning capacitors (CL1, CL2), it is
recommended for long-term consistent performance of the
system that two tuning capacitor pads be placed into every
design. Typical values for the load tuning capacitors will range
from 0 to 4pF.
Using the tables and figures above, we can now calculate the
TPR and APR of the VCXO using the example crystal
parameters. For the numerical example below there were some
assumptions made. First, the stray capacitance (CS1, CS2), which
is all the excess capacitance due to board parasitic, is 4pF.
Second, the expected lifetime of the project is 5 years; hence
CLow =
(0 + 4 pf + 15.4 pf ) ⋅ (0 + 4 pf + 15.4 pf ) = 9.7 pf
(0 + 4 pf + 15.4 pf ) + (0 + 4 pf + 15.4 pf )
CHigh =
(0 + 4 pf + 29.6 pf ) ⋅ (0 + 4 pf + 29.6 pf ) = 16.8 pf
(0 + 4 pf + 29.6 pf ) + (0 + 4 pf + 29.6 pf )
⎛
⎞
⎜
⎟
1
1
⎟ ⋅ 106 ⋅ = 226.5 ppm
−
TPR = ⎜
⎞⎟ 2 ⋅ 220 ⋅ ⎛⎜1 + 16.8 pF
⎞⎟ ⎟
⎜⎜ 2 ⋅ 220 ⋅ ⎛⎜1 + 9.7 pF
4 pF ⎠
4 pF ⎠ ⎟⎠
⎝
⎝
⎝
TPR = ±113.25ppm
APR = 113.25ppm – (20ppm + 20ppm + 15ppm) = ±58.25ppm
with better pullability (C0/C1 ratio) can be used. Also, with the
equations above, one can vary the frequency tolerance,
temperature stability, and aging or shunt capacitance to achieve
the required pullability.
The example above will ensure a total pull range of
±113.25 ppm with an APR of ±58.25ppm. Many times, board
designers may select their own crystal based on their
application. If the application requires a tighter APR, a crystal
81006AK
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REV. A JANUARY 4, 2006
ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
INPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used. The VC pin can not be
floated.
SCHEMATIC EXAMPLE
drivers, series termination example is shown in the schematic. Additional termination approaches are shown in the
LVCMOS Termination Application Note.
Figure 2 shows an example of ICS81006 application schematic. The decoupling capacitors should be located as close
as possible to the power pin. For the LVCMOS 20Ω output
Pull-up VDD
example
R4
1K
VDD
R1
Zo = 50
U1
1
2
3
4
5
XTAL
XTAL_IN
XTAL_OUT
VDD
VC
DIV_SEL_Q5
GND
Q2
VDDO
Q3
GND
15
14
13
12
11
OE1
GND
Q5
VDDO
Q4
C2
SPARE
81006
Pull-down
example
6
7
8
9
10
VC
VC = 0V to VDD
30
OE0
GND
Q0
VDDO
Q1
C1
SPARE
20
19
18
17
16
Quartz crystal should be
placed as close to the
device as possible.
VDDO
R3
1K
R2
Zo = 50
VDD
30
R5
(U1-3)
(U1-9)
VDD
C7
10uf
1K
(U1-13)
(U1-17)
VDDO
C6
0.1uF
C5
0.1uF
C4
0.1uF
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
C3
0.1uF
FIGURE 2. ICS81006 SCHEMATIC EXAMPLE
81006AK
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REV. A JANUARY 4, 2006
ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD VFQFN
θJA by Velocity (Meters Per Second)
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
141.7°C/W
38.5°C/W
1
126.0°C/W
35.0°C/W
2.5
116.9°C/W
33.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS81006 is: 983
81006AK
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REV. A JANUARY 4, 2006
ICS81006
Integrated
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PACKAGE OUTLINE - K SUFFIX
FOR
VCXO-TO-6 LVCMOS OUTPUTS
20 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
A
0.80
A1
0
1. 0
0.05
0.25 Reference
A3
b
MAXIMUM
20
N
0.18
0.30
e
0.50 BASIC
ND
5
NE
5
D
4.0
D2
0.75
2.80
4.0
E
E2
0.75
2.80
L
0.35
0.75
Reference Document: JEDEC Publication 95, MO-220
81006AK
www.icst.com/products/hiperclocks.html
13
REV. A JANUARY 4, 2006
ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS81006AK
81006A
20 lead VFQFN
tube
0°C to 70°C
ICS81006AKT
81006A
20 lead VFQFN
2500 tape & reel
0°C to 70°C
ICS81006AKLF
TBD
20 lead "Lead-Free" VFQFN
tube
0°C to 70°C
ICS81006AKLFT
TBD
20 lead "Lead-Free" VFQFN
2500 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
81006AK
www.icst.com/products/hiperclocks.html
14
REV. A JANUARY 4, 2006