PRELIMINARY Integrated Circuit Systems, Inc. ICS840008-01 FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS840008-01 is an 8 output LVCMOS/LVTTL Synthesizer designed to generate 125MHz for HiPerClockS™ Gigabit Ethernet applications and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. The ICS840008-01 uses ICS’ 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical random rms phase jitter, easily meeting Gigabit Ethernet jitter requirements. The ICS840008-01 is packaged in a small 24-pin SSOP package. • Eight LVCMOS/LVTTL outputs, 15Ω typical output impedance ICS • Output frequency range: 125MHz - 160MHz • Crystal oscillator interface, 25MHz - 32MHz crystal • VCO range: 500MHz - 640MHz • RMS phase jitter (1.875MHz - 20MHz): 0.52ps (typical) • Output skew: 150ps (maximum) (design target) • Voltages supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request PIN ASSIGNMENT BLOCK DIAGRAM nPLL_SEL Pulldown 25MHz 1 XTAL_IN OSC XTAL_OUT Phase Detector VCO 500MHz 640MHz ÷4 (fixed) 0 8 8 Q0:Q7 VDDO nc XTAL_OUT XTAL_IN VDDA OE MR nPLL_SEL VDD nc GND nc 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q0 Q1 GND Q2 Q3 VDDO Q4 Q5 GND Q6 Q7 VDDO ICS840008-01 ÷20 (fixed) 24-Lead SSOP, 150MIL 3.9mm x 8.65mm x 1.5mm package body R Package Top View MR Pulldown OE Pullup The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 840008AR-01 www.icst.com/products/hiperclocks.html 1 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840008-01 FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name 1, 13, 19 VDDO Power Type 2, 10, 12 3, 4 5 nc XTAL_OUT, XTAL_IN VDDA Unused 6 OE Input 7 MR Input 8 nPLL_SEL Input 9 VDD Power Description Output supply pins. No connect. Crystal interface. XTAL_OUT is the output, XTAL_IN is the input. Analog supply pin. Input Power Pullup Output enable. LVCMOS/LVTTL interface levels Active HIGH Master Reset. When logic HIGH, the internal dividers are Pulldown reset causing the true outputs to go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and XTAL as the input to the dividers. Pulldown When HIGH, selects XTAL. When LOW, selects PLL. LVCMOS/LVTTL interface levels. Core supply pin. 11, 16, 22 GND Power Power supply ground. 14, 15, 17, Q7, Q6, Q5, Single-ended outputs.15Ω impedance. 18, 20, 21, Q4, Q3, Q2, Ouput LVCMOS/LVTTL interface levels. 23, 24 Q1, Q0 NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance RPULLUP Input Pullup Resistor RPULLDOWN Input Pulldown Resistor ROUT 840001AR-01 Output Impedance Test Conditions Minimum Typical Maximum Units 4 pF VDDO = 3.63V TBD pF VDDO = 2.625V TBD pF VDDO = 1.89V TBD pF 51 KΩ 51 KΩ VDDO = 3.63V or 2.625V 15 Ω VDDO = 1.89V TBD Ω www.icst.com/products/hiperclocks.html 2 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840008-01 FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 73.1°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±10%, VDDO = 3.3V±10% OR 2.5V±5% OR 1.8V±5%, TA = 0°C TO 70°C Symbol VDD Parameter Core Supply Voltage VDDA Analog Supply Voltage VDDO Test Conditions Minimum 2.97 Output Supply Voltage Typical 3.3 Maximum 3.63 Units V 2.97 3.3 3.63 V 2.97 3.3 3.63 V 2.375 2.5 2.625 V 1.71 1.8 1.89 V IDD Power Supply Current 65 mA IDDA IDDO Analog Supply Current Output Supply Current 5 4 mA mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, VDDO = 2.5V±5% OR 1.8V±5%, TA = 0°C TO 70°C Symbol VDD Parameter Core Supply Voltage VDDA Analog Supply Voltage VDDO Output Supply Voltage IDD Power Supply Current 60 mA IDDA IDDO Analog Supply Current Output Supply Current 5 4 mA mA 840008AR-01 Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 Units V 2.375 2.5 2.625 V 2.375 2.5 2.625 V 1.71 1.8 1.89 V www.icst.com/products/hiperclocks.html 3 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840008-01 FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = 0°C TO 70°C Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Test Conditions Minimum Maximum Units OE, MR, PLL_SEL VDD = 3.3V ±10% 2 VDD + 0.3 V VDD = 2.5V ± 5% 1.7 VDD + 0.3 V OE, MR, PLL_SEL VDD = 3.3V ±10% -0.3 1.3 V VDD = 2.5V ± 5% -0.3 0.7 V MR, nPLL_SEL VDD = 3.3V ±10% 150 µA VDD = 2.5V ± 5% 150 µA Input High Current OE MR, nPLL_SEL IIL Input Low Current OE Typical VDD = 3.3V ±10% 5 µA VDD = 2.5V ± 5% 5 µA VDD = 3.3V ±10% -5 µA VDD = 2.5V ± 5% -5 µA VDD = 3.3V ±10% -150 µA VDD = 2.5V ± 5% -150 µA VDDO = 3.3V ± 10% 2.6 V VOH Output High Voltage; NOTE 1 VDDO = 2.5V ± 5% 1.8 V VDDO = 1.8V ± 5% 1.5 VOL Output Low Voltage: NOTE 1 VDDO = 3.3V±10% or 2.5V±5% 0.5 V VDDO = 1.8V ± 5% 0.4 V V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Fundamental Frequency 25 Units MHz 32 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF NOTE: Characterized using an 18pF parallel resonant crystal. 840001AR-01 www.icst.com/products/hiperclocks.html 4 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840008-01 FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±10%, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency tsk(o) tL Output Skew; NOTE 1, 3 RMS Phase Jitter (Random); NOTE 2 PLL Lock Time tR / tF Output Rise/Fall Time tjit(Ø) Test Conditions Minimum Typical 125 Integration Range: 1.875MHz - 20MHz 20% to 80% Maximum Units 160 MHz TBD ps 0.52 ps TBD ms 550 ps odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. % TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±10%, VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency tsk(o) tL Output Skew; NOTE 1, 3 RMS Phase Jitter (Random); NOTE 2 PLL Lock Time tR / tF Output Rise/Fall Time tjit(Ø) Test Conditions Minimum Typical 125 Integration Range: 1.875MHz - 20MHz 20% to 80% Maximum Units 160 MHz TBD ps 0.53 ps TBD ms 600 ps odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. % TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = 3.3V±10%, VDDO = 1.8V±5%, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency tsk(o) tL Output Skew; NOTE 1, 3 RMS Phase Jitter (Random); NOTE 2 PLL Lock Time tR / tF Output Rise/Fall Time tjit(Ø) Test Conditions Minimum Typical 125 Integration Range: 1.875MHz - 20MHz 20% to 80% www.icst.com/products/hiperclocks.html 5 Units 160 MHz TBD ps 0.49 ps TBD ms 630 ps odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 840008AR-01 Maximum % REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840008-01 FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 5D. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency tsk(o) tL Output Skew; NOTE 1, 3 RMS Phase Jitter (Random); NOTE 2 PLL Lock Time tR / tF Output Rise/Fall Time tjit(Ø) Test Conditions Minimum Typical 125 Integration Range: 1.875MHz - 20MHz 20% to 80% Maximum Units 160 MHz TBD ps 0.53 ps TBD ms 600 ps odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. % TABLE 5E. AC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, VDDO = 1.8V±5%, TA = 0°C TO 70°C Symbol Parameter fOUT Output Frequency tsk(o) tL Output Skew; NOTE 1, 3 RMS Phase Jitter (Random); NOTE 2 PLL Lock Time tR / tF Output Rise/Fall Time tjit(Ø) Test Conditions Minimum Typical 125 Integration Range: 1.875MHz - 20MHz 20% to 80% www.icst.com/products/hiperclocks.html 6 Units 160 MHz TBD ps 0.49 ps TBD ms 630 ps odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot which will follow the AC Characteristics Tables. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 840001AR-01 Maximum % REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840008-01 FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 125MHZ (3.3V) ➤ 0 -10 -20 -30 Gigabit Ethernet Filter -40 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.52ps (typical) -60 -70 -80 -90 Raw Phase Noise Data -100 -110 ➤ NOISE POWER dBc Hz -50 -120 -130 -140 -150 ➤ -160 -170 -180 -190 100 1k Phase Noise Result by adding Gigabit Ethernet Filter to raw data 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 840008AR-01 www.icst.com/products/hiperclocks.html 7 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840008-01 FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 1.65V±10% 2.05V±13% 1.25V±5% SCOPE VDD, VDDA, VDDO LVCMOS VDD, VDDA, Qx SCOPE VDDO Qx LVCMOS GND GND -1.65V±10% -1.25V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 1.25V±5% 2.4V±12% 0.9V±5% SCOPE VDD, VDDA, VDDO LVCMOS SCOPE VDD, VDDA, VDDO Qx Qx LVCMOS GND GND -1.25V±5% -0.9V±5% 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 1.6V±5% 0.9V±5% Noise Power Phase Noise Plot SCOPE VDD, VDDA, VDDO LVCMOS Qx Phase Noise Mask GND f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot -0.9V±5% 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 840001AR-01 RMS PHASE JITTER www.icst.com/products/hiperclocks.html 8 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840008-01 FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER V DDO Qx 80% 2 Clock Outputs V DDO Qy 2 t sk(o) OUTPUT SKEW 80% 20% 20% tR tF OUTPUT RISE/FALL TIME V DDO 2 Q0:Q7 Pulse Width t odc = PERIOD t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 840008AR-01 www.icst.com/products/hiperclocks.html 9 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840008-01 FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840008-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VDDA. 3.3V VDD .01μF 10Ω V DDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS840008-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332 ICS840008-01 Figure 2. CRYSTAL INPUt INTERFACE 840001AR-01 www.icst.com/products/hiperclocks.html 10 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840008-01 FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD SSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 73.1°C/W 65.9°C/W 60.5°C/W TRANSISTOR COUNT The transistor count for ICS840008-01 is: 3378 840008AR-01 www.icst.com/products/hiperclocks.html 11 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - R SUFFIX FOR ICS840008-01 FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER 24 LEAD SSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 24 A 1.35 1.75 A1 0.10 0.25 b 0.20 0.30 c 0.18 0.25 A2 1.50 D 8.55 8.75 E 5.80 6.20 E1 3.80 e 4.00 0.635 BASIC L 0.40 α 0° ZD 1.27 8° 0.84 REF Reference Document: JEDEC Publication 95, MO-137 840001AR-01 www.icst.com/products/hiperclocks.html 12 REV. A APRIL 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS840008-01 FEMTOCLOCKS™CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS840008AR-01 ICS840008AR01 24 Lead SSOP tube 0°C to 70°C ICS840008AR-01T ICS840008AR01 24 Lead SSOP 2500 tape & reel 0°C to 70°C The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840008AR-01 www.icst.com/products/hiperclocks.html 13 REV. A APRIL 7, 2005