SN54HCT138, SN74HCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS171C – MARCH 1984 – REVISED MAY 1997 D SN54HCT138 . . . J OR W PACKAGE SN74HCT138 . . . D, N, OR PW PACKAGE (TOP VIEW) A B C G2A G2B G1 Y7 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 SN54HCT138 . . . FK PACKAGE (TOP VIEW) description The ’HCT138 are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. B A NC VCC Y0 D Inputs Are TTL-Voltage Compatible Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs C G2A NC G2B G1 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 Y1 Y2 NC Y3 Y4 Y7 GND NC Y6 Y5 D D NC – No internal connection The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low (G) and one active-high (G) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The SN54HCT138 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HCT138 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HCT138, SN74HCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS171C – MARCH 1984 – REVISED MAY 1997 FUNCTION TABLE INPUTS ENABLE OUTPUTS SELECT G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 X H X X X X H H H H H H H Y7 H X X H X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L logic symbols (alternatives)† A B C G1 G2A G2B 1 2 3 6 4 5 BIN/OCT 0 1 1 2 2 4 3 4 & EN 5 6 7 15 14 13 12 11 10 9 7 Y0 A Y1 Y2 Y3 B C G1 Y6 G2A Y7 G2B POST OFFICE BOX 655303 0 2 3 6 4 5 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, PW, and W packages. 2 DMUX 0 G 2 0 7 1 2 3 Y4 Y5 1 • DALLAS, TEXAS 75265 & 4 5 6 7 15 14 13 12 11 10 9 7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 SN54HCT138, SN74HCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS171C – MARCH 1984 – REVISED MAY 1997 logic diagram (positive logic) 15 A B C 1 14 Y1 2 13 3 12 11 10 G1 Y0 6 Y2 Y3 Y4 Y5 9 Y6 G2A 4 7 G2B Y7 5 Pin numbers shown are for the D, J, N, PW, and W packages. absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54HCT138, SN74HCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS171C – MARCH 1984 – REVISED MAY 1997 recommended operating conditions SN54HCT138 SN74HCT138 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0 0.8 0 0.8 V Input voltage 0 0 Output voltage 0 0 VCC VCC V VO tt VCC VCC 0 500 0 500 ns TA Operating free-air temperature –55 125 –40 85 °C High-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 2 Input transition (rise and fall) time 2 V V V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VI = VIH or VIL IOH = –20 µA IOH = –4 mA 45V 4.5 VOL VI = VIH or VIL IOL = 20 µA IOL = 4 mA 45V 4.5 II ICC VI = VCC or 0 VI = VCC or 0, ∆ICC† MIN MIN MAX SN74HCT138 MIN 4.4 4.499 4.4 4.4 4.3 3.7 3.84 5.5 V 4.5 V to 5.5 V MAX UNIT V 0.001 0.1 0.1 0.1 0.17 0.26 0.4 0.33 ±0.1 ±100 ±1000 ±1000 nA 8 160 80 µA 1.4 2.4 3 2.9 mA 3 10 10 10 pF 5.5 V Ci SN54HCT138 3.98 5.5 V IO = 0 One input at 0.5 V or 2.4 V, Other inputs at 0 or VCC TA = 25°C TYP MAX V † This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) A B, A, B or C Any Y tpd d Enable tt Any Y Y VCC MIN TA = 25°C TYP MAX SN54HCT138 MIN MAX SN74HCT138 MIN MAX 4.5 V 23 36 54 45 5.5 V 17 32 49 34 4.5 V 22 33 50 42 5.5 V 18 30 45 38 4.5 V 12 15 22 19 5.5 V 11 14 20 17 UNIT ns ns operating characteristics, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 85 UNIT pF SN54HCT138, SN74HCT138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS171C – MARCH 1984 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION From Output Under Test 3V Test Point Input 1.3 V 1.3 V 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 1.3 V 10% tPHL 90% 90% tr Input 1.3 V 0.3 V 2.7 V 2.7 V tr tPHL 3V 1.3 V 0.3 V 0 V Out-of-Phase Output 90% tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOH 1.3 V 10% V OL tf tPLH 1.3 V 10% tf 1.3 V 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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