PTH04070W www.ti.com SLTS227 – SEPTEMBER 2004 3-A, 3.3/5-V INPUT ADJUSTABLE SWITCHING REGULATOR • • • FEATURES • • • • • • • • • Up to 3-A Output Current at 85°C 3.3-V / 5-V Input Voltage Wide-Output Voltage Adjust (0.9 V to 3.6 V) 160 W/in3 Power Density Efficiencies Up To 94% On/Off Inhibit Undervoltage Lockout (UVLO) Output Overcurrent Protection (Nonlatching, Auto-Reset) Overtemperature Protection Ambient Temp. Range: –40°C to 85°C Surface Mount Package Safety Agency Approvals: UL/CUL 60950, EN60950 VDE (Pending) APPLICATIONS • Telecommunications, Instumentation, and General-Purpose Circuits DESCRIPTION The PTH04070W is a highly integrated, low-cost switching regulator module that delivers up to 3 A of output current. Occupying less PCB area than a standard TO-220 linear regulator IC, the PTH04070W provides output current at a much higher efficiency and with much less power dissipation, thereby eliminating the need for a heat sink. Their small size (0.5 × 0.4 in), high efficiency, and low cost makes these modules attractive for a variety of applications. The input voltage range of the PTH04070W is from 3 V to 5.5 V, allowing operation from either a 3.3-V or 5-V input bus. Using state-of-the-art switched-mode power-conversion technology, the PTH04070W can step down to voltages as low as 0.9 V from a 5-V input bus, with typically less than 1 W of power dissipation. The output voltage can be adjusted to any voltage over the range, 0.9 V to 3.6 V, using a single external resistor. Operating features include an undervoltage lockout (UVLO), on/off inhibit, output overcurrent protection, and overtemperature protection. Target applications include telecommunications, test and measurement applications, and high-end consumer products. The modules are available in both through-hole and surface-mount package options, including tape and reel. STANDARD APPLICATION Inhibit 5 4 RSET 0.05 W#, 1% (Required) VI VO PTH04070W (Top View) 1 GND 3 2 C1* 47 F Ceramic (Required) C2* 47 F Ceramic (Required) C3* 47 F Electroytic (Recommended) GND #See The Specification Table for Value *See The Capacitor Application Information Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated PTH04070W www.ti.com SLTS227 – SEPTEMBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PTH04070 (Basic Model) Output Voltage 0.9 V - 3.6 V (1) Part Number Description Package Designator PTH04070WAH Horizontal T/H EVD PTH04070WAS (1) Horizontal SMD EVE Add a T suffix for tape and reel option on SMD packages. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TA Tstg (1) Operating free-air temperature Over Vin range Solder reflow temperature Surface temperature of module body or pins Storage temperature PTH04070 UNIT -40 to 85 °C 235 °C -40 to 125 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS VI Input voltage TA Operating free-air temperature MIN MAX 3 5.5 V –40 85 °C PACKAGE SPECIFICATIONS PTH04070x (Suffix AH & AS) Weight Flammability Mechanical shock Mechanical vibration (1) 2 Qualification limit. 1.5 grams Meets UL 94 V-O Per Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted 500 Gs Mil-STD-883D, Method 2007.2, 20-2000 Hz 20 Gs (1) (1) UNIT PTH04070W www.ti.com SLTS227 – SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS at 25°C free-air temperature, VI = 5 V, VO = 3.3 V, IO = IO(Max), C1 = 47 µF, C2 = 47 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IO Output current TA = 85°C, natural convection airflow 0 3 A VI Input voltage range Over IO range 3 5.5 V VO(tol) Set-point voltage tolerance TA = 25°C Temperature variation -40 ≤ TA≤ +85°C Line regulation Over VI range ±1 mV Load regulation Over IO range ±5 mV Total output voltage variation Includes set-point, line, load, -40 ≤ TA≤ +85°C VO(adj) Output voltage adjust range ±2% (1) ±0.5% VO 3% (1) VI ≥ 4.5 V 0.9 3.6 VI < 4.5 V 0.9 VI – 1.1 (2) V TA = 25°C, IO = 2 A η RSET = 475 Ω, VO = 3.3 V (2) 92% RSET = 2.32 kΩ, VO = 2.5 V V (2) 90% RSET = 4.87 kΩ, VO = 2 V 88% RSET = 6.65 kΩ, VO = 1.8 V 87% RSET = 11.5 kΩ, VO = 1.5 V 85% RSET = 26.1 kΩ, VO = 1.2 V 82% RSET = 84.5 kΩ, VO = 1 V 80% Efficiency IO(trip) Output voltage ripple 20 MHz bandwith Overcurrent threshold Reset, followed by autorecovery 10 mVPP 7 A C3 = 47 µF, 1 A/µs load step from 50% to 100% IOmax Transient response UVLO Undervoltage lockout Recovery time 70 µs VO over/undershoot 100 mV VI = increasing VI = decreasing Input high voltage (VIH) Inhibit control (pin 5) Input low voltage (VIL) 2.95 2.7 VI – 0.5 Input low current (IIL) Input standby current Pins 5 and 2 connected FS Switching frequency Over VI and IO ranges External input capacitance Ceramic type (C1) 47 (4) Ceramic type (C2) 47 (5) External output capacitance Nonceramic type (C3) Equivalent series resistance (nonceramic) MTBF (1) (2) (3) (4) (5) (6) (7) Calculated reliability Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign Open –0.2 II(stby) V (3) 0.6 V –10 µA 1 mA 700 kHz µF 200 47 4 3 2.8 (5) 560 (6) µF (7) mΩ 48 106 Hrs The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a tolerance of 1% with with 100 ppm/°C or better temperature stability. The minimum input voltage is 3 V or (VO + 1.1) V, whichever is greater. A 5-V input bus is recommended for output voltages higher than 2 V. This control pin has an internal pullup to the input voltage VI. If it is left open circuit, the module operates when input power is applied. A small low-leakage (<100 nA) MOS field effect transistor (MOSFET) is recommended for control. See the application information for further guidance. An external 47-µF ceramic capacitor is required across the input (VI and GND) for proper operation. Locate the capacitor close to the module. An external 47-µF ceramic capacitor is required across the output (VO and GND) for proper operation. Locate the capacitor close to the module. Adding another 47 µF of electrolytic capacitance close to the load improves the response of the regulator to load transients. This is the calculated maximum capacitance. The minimum ESR limitation often results in a lower value. See the capacitor application information for further guidance. This is the typical ESR for all the electrolytic (nonceramic) capacitance. Use 7 mΩ as the minimum when calculating the total equivalent series resistance (ESR) using the max-ESR values specified by the capacitor manufacturer. 3 PTH04070W www.ti.com SLTS227 – SEPTEMBER 2004 PIN ASSIGNMENT TERMINAL FUNCTIONS TERMINAL NAME NO. VI 1 GND 2 VO 3 VO Adjust Inhibit 4 4 5 I/O I DESCRIPTION The positive input voltage power node to the module, which is referenced to common GND. This is the common ground connection for the VI and VO power connections. It is also the 0 VDC reference for the Inhibit and VO Adjust control inputs. O The regulated positive power output with respect to the GND node. I A 1% resistor must be connected between this pin and GND (pin 1) to set the output voltage of the module higher than 0.9 V. If left open-circuit, the output voltage defaults to this value. The temperature stability of the resistor should be 100 ppm/°C (or better). The set-point range is from 0.9 V to 3.6 V. The electrical specification table gives the standard resistor value for a number of common output voltages. Refer to the application information for further guidance. I The Inhibit pin is an open-collector/drain-negative logic input that is referenced to GND. Applying a low-level ground signal to this input disables the module's output. When the Inhibit control is active, the input current drawn by the regulator is significantly reduced. If the Inhibit pin is left open-circuit, the module will produce an output voltage whenever a valid input source is applied. PTH04070W www.ti.com SLTS227 – SEPTEMBER 2004 TYPICAL CHARACTERISTICS (5-V INPUT) (1) (2) EFFICIENCY vs OUTPUT CURRENT OUTPUT RIPPLE vs OUTPUT CURRENT 20 100 VO = 3.3 V V = 2.5 V O V O − Output Voltage Ripple − mV PP VO = 2 V Efficiency − % 90 80 VO = 1.8 V VO = 1.5 V VO = 1.2 V VO = 1 V 70 60 50 16 12 8 4 0 0 0.5 1 1.5 2 2.5 0 3 0.5 IO − Output Current − A 1.5 2 2.5 Figure 1. Figure 2. POWER DISSIPATION vs OUTPUT CURRENT TEMPERATURE DERATING vs OUTPUT CURRENT 1.5 3 90 80 1.2 Temperature Derating − C PD − Power Dissipation − W 1 IO − Output Current − A 0.9 0.6 0.3 Airflow: Nat Conv 70 60 50 40 30 0 0 (1) (2) 0.5 1 1.5 2 2.5 3 20 0 0.5 1 1.5 2 IO − Output Current − A IO − Output Current − A Figure 3. Figure 4. 2.5 3 The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 1, Figure 2, and Figure 3. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to modules soldered directly to a 100 mm x 100 mm double-sided PCB with 1 oz. copper. Applies to Figure 4. 5 PTH04070W www.ti.com SLTS227 – SEPTEMBER 2004 TYPICAL CHARACTERISTICS (3.3-V INPUT) (3) (4) EFFICIENCY vs OUTPUT CURRENT OUTPUT RIPPLE vs OUTPUT CURRENT 20 100 VI = 1.8 V VI = 1.5 V 90 Efficiency − % V O − Output Voltage Ripple − mV PP VI = 2 V 80 VI = 1.2 V VI = 1 V 70 60 50 0 0.5 1 1.5 2 2.5 12 8 4 0 3 0 0.5 1 1.5 2 2.5 IO − Output Current − A IO − Output Current − A Figure 5. Figure 6. POWER DISSIPATION vs OUTPUT CURRENT TEMPERATURE DERATING vs OUTPUT CURRENT 1.5 3 90 80 1.2 Temperature Derating − C PD − Power Dissipation − W 16 0.9 0.6 0.3 Airflow: Nat Conv 70 60 50 40 30 0 0 0.5 1 1.5 2 IO − Output Current − A Figure 7. (3) (4) 6 2.5 3 20 0 0.5 1 1.5 2 2.5 IO − Output Current − A 3 Figure 8. The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 5, Figure 6, and Figure 7. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to modules soldered directly to a 100 mm x 100 mm double-sided PCB with 1 oz. copper. Applies to Figure 8. PTH04070W www.ti.com SLTS227 – SEPTEMBER 2004 APPLICATION INFORMATION Adjusting the Output Voltage of the PTH04070W Wide-Output Adjust Power Modules The VO Adjust control (pin 4) sets the output voltage of the PTH04070W product. The adjustment range is from 0.9 V to 3.6 V. The adjustment method requires the addition of a single external resistor, Rset, that must be connected directly between the VO Adjust and GND pin 2. Table 1 gives the standard external resistor for a number of common bus voltages, along with the actual voltage the resistance produces. For other output voltages, the value of the required resistor can either be calculated using the following formula, or simply selected from the range of values given in Table 2. Figure 9 shows the placement of the required resistor. R set 10 k 0.891 V 3.24 k V out 0.9 V Table 1. Standard Values of Rset for Common Output Voltages Vout (Required) (1) Rset (Standard Value) Vout (Actual) 3.3 V (1) 475 Ω 3.298 V 2.5 V (1) 2.32 kΩ 2.502 V 2V 4.87 kΩ 1.999 V 1.8 V 6.65 kΩ 1.801 V 1.5 V 11.5 kΩ 1.504 V 1.2 V 26.1 kΩ 1.204 V 1V 84.5 kΩ 1.001 V 0.9 V Open 0.9 V The minimum input voltage is 3 V or (VO + 1.1) V, whichever is greater. VI 1 PTH04070W VO VIN Inhibit 5 C1 47-µF Ceramic Inhibit VO 3 VO Adj GND 2 4 RSET 0.05 W 1% GND C2 47-µF Ceramic GND (1) A 0.05-W rated resistor may be used. The tolerance should be 1%, with a temperature stability of 100 ppm/°C (or better). Place the resistor as close to the regulator as possible. Connect the resistor directly between pins 4 and 2 using dedicated PCB traces. (2) Never connect capacitors from VO Adjust to either GND or VO. Any capacitance added to the VO Adjust pin will affect the stability of the regulator. Figure 9. VO Adjust Resistor Placement 7 PTH04070W www.ti.com SLTS227 – SEPTEMBER 2004 Table 2. Calculated Set-Point Resistor Values 8 Va Req'd Rset Va Req'd Rset Va Req'd Rset 0.900 Open 1.475 12.3 kΩ 2.55 2.16 kΩ 0.925 353 kΩ 1.50 11.6 kΩ 2.60 2.00 kΩ 0.950 175 kΩ 1.55 10.5 kΩ 2.65 1.85 kΩ 0.975 116 kΩ 1.60 9.49 kΩ 2.70 1.71 kΩ 1.000 85.9 kΩ 1.65 8.64 kΩ 2.75 1.58 kΩ 1.025 68.0 kΩ 1.70 7.90 kΩ 2.80 1.45 kΩ 1.050 56.2 kΩ 1.75 7.24 kΩ 2.85 1.33 kΩ 1.075 47.7 kΩ 1.80 6.66 kΩ 2.90 1.22 kΩ 1.100 41.3 kΩ 1.85 6.14 kΩ 2.95 1.11 kΩ 1.125 36.4 kΩ 1.90 5.67 kΩ 3.00 1.00 kΩ 1.150 32.4 kΩ 1.95 5.25 kΩ 3.05 904 Ω 1.175 29.2 kΩ 2.00 4.86 kΩ 3.10 810 Ω 1.200 26.5 kΩ 2.05 4.51 kΩ 3.15 720 Ω 1.225 24.2 kΩ 2.10 4.19 kΩ 3.20 634 Ω 1.250 22.2 kΩ 2.15 3.89 kΩ 3.25 551 Ω 1.275 20.5 kΩ 2.20 3.61 kΩ 3.30 473 Ω 1.300 19.0 kΩ 2.25 3.36 kΩ 3.35 397 Ω 1.325 17.7 kΩ 2.30 3.12 kΩ 3.40 324 Ω 1.350 16.6 kΩ 2.35 2.90 kΩ 3.45 254 Ω 1.375 15.5 kΩ 2.40 2.70 kΩ 3.50 187 Ω 1.400 14.6 kΩ 2.45 2.51 kΩ 3.55 122 Ω 1.425 13.7 kΩ 2.50 2.33 kΩ 3.60 60 Ω 1.450 13.0 kΩ PTH04070W www.ti.com SLTS227 – SEPTEMBER 2004 CAPACITOR RECOMMENDATIONS for the PTH04070W WIDE-OUTPUT ADJUST POWER MODULES Input Capacitor The minimum recommended input capacitor(s) is 47-µF of ceramic capacitance, in either an X5R or X7R temperature tolerance. The ceramic capacitors should be located within 0.5 in. (1,27 cm) of the regulator's input pins. Electrolytic capacitors can also be used at the input, but only in addition to the required ceramic capacitance. The minimum ripple current rating for nonceramic capacitors should be at least 200 mA rms. The ripple current rating of electrolytic capacitors is a major consideration when they are used at the input. When specifying regular tantalum capacitors for use at the input, a minimum voltage rating of 2 × (maximum dc voltage + ac ripple) is highly recommended. This is standard practice to ensure reliability. Polymer-tantalum capacitors are not affected by this requirement. For improved ripple reduction on the input bus, additional ceramic capacitors can be used to complement the minimum requirement. Output Capacitors For most applications only one (1) 47-µF ceramic capacitor is required. The ceramic capacitor should be located within 0.5 in. (1,27 cm) of the output pin. Adding a second 47-µF nonceramic capacitor allows the module to meet its transient response specification. For applications with load transients (sudden changes in load current), the regulator response benefits from additional external output capacitance. A high-quality computer-grade electrolytic capacitor should be adequate. Electrolytic capacitors should be located close to the load circuit. These capacitors provide decoupling over the frequency range, 2 kHz to 150 kHz. Aluminum electrolytic capacitors are suitable for ambient temperatures above 0°C. For operation below 0°C, tantalum or Os-Con type capacitors are recommended. When using one or more nonceramic capacitors, the calculated equivalent ESR should be no lower than 4 mΩ (7 mΩ using the manufacturer's maximum ESR for a single capacitor). A list of preferred low-ESR type capacitors are identified in Table 3, the recommended capacitor table. Ceramic Capacitors Above 150 kHz the performance of aluminum electrolytic capacitors becomes less effective. To further improve the reflected input ripple current, or the output transient response, multilayer ceramic capacitors must be added. Ceramic capacitors have very low ESR and their resonant frequency is higher than the bandwidth of the regulator. When placed at the output their combined ESR is not critical as long as the total value of ceramic capacitance does not exceed 200 µF. Also, to prevent the formation of local resonances, do not place more than three identical ceramic capacitors with values of 10 µF or greater in parallel. Tantalum Capacitors Additional tantalum type capacitors can be used at both the input and output, and are recommended for applications where the ambient operating temperature can be less than 0°C. The AVX TPS, Sprague 593D/594/595 and Kemet T495/T510/T520 capacitors series are suggested over many other tantalum types due to their rated surge, power dissipation, and ripple current capability. As a caution, many general-purpose tantalum capacitors have considerably higher ESR, reduced power dissipation, and lower ripple current capability. These capacitors are also less reliable as they have lower power dissipation and surge current ratings. Tantalum capacitors that do not have a stated ESR or surge current rating are not recommended for power applications. When specifying Os-Con and polymer tantalum capacitors for the output, the minimum ESR limit is encountered well before the maximum capacitance value is reached. Capacitor Table The capacitor table, Table 3, identifies the characteristics of capacitors from a number of vendors with acceptable ESR and ripple current (rms) ratings. The recommended number of capacitors required at both the input and output buses is identified for each capacitor type. This is not an extensive capacitor list. Capacitors from other vendors are available with comparable specifications. Those listed are for guidance. The rms rating and ESR (at 100 kHz) are critical parameters necessary to insure both optimum regulator performance and long capacitor life. 9 PTH04070W www.ti.com SLTS227 – SEPTEMBER 2004 Designing for Load Transients The transient response of the dc/dc converter has been characterized using a load transient with a di/dt of 1 A/µs. The typical voltage deviation for this load transient is given in the data sheet specification table using the optional value of output capacitance. As the di/dt of a transient is increased, the response of a converter's regulation circuit ultimately depends on its output capacitor decoupling network. This is an inherent limitation with any dc/dc converter once the speed of the transient exceeds its bandwidth capability. If the target application specifies a higher di/dt or lower voltage deviation, the requirement can only be met with additional output capacitor decoupling. In these cases, special attention must be paid to the type, value, and ESR of the capacitors selected. If the transient performance requirements exceed those specified in the data sheet, the selection of output capacitors becomes more important. Review the minimum ESR in the characteristic data sheet for details on the capacitance maximum. Table 3. Recommended Input/Output Capacitors CAPACITOR CHARACTERISTICS QUANTITY WORKING VOLTAGE VALUE µF EQUIVALENT SERIES RESISTANCE (ESR) 85°C MAXIMUM RIPPLE CURRENT (Irms) Panasonic WA (SMT) FC (SMT) 10 V 25 V 120 47 0.035 Ω 0.400 Ω 2800 mA 230 mA 8×6.9 8×6.2 1 1 ≤ 4 (1) 1 (1) Panasonic SL SP-cap(SMT) 6.3 V 6.3 V 47 56 0.018 Ω 0.009 Ω 2500 mA 3000 mA 7.3×4.3 7.3× 4.3 1 1 ≤3 ≤2 EEFCD0J470R EEFSL0J560R United Chemi-con PXA (SMT) FS LXZ MVZ (SMT) 10 10 16 16 V V V V 47 100 100 100 0.031 Ω 0.040 Ω 0.250 Ω 0.440 Ω 2250 mA 2100 mA 290 mA 230mA 6.3×5.7 6.3×9.8 6.3×11.5 6.3×5.7 1 1 1 1 1 ≤5 1 1 PXA10VC470MF60TP 10FS100M LXZ16VB101M6X11LL MVZ16VC101MF60TP Nichicon UWG (SMT) F559(Tantalum) PM 16 V 10 V 10 V 100 100 100 0.400 Ω 0.055 Ω 0.550 Ω 230mA 2000mA 210 mA 8×6.2 7.7 × 4.3 6×11 1 1 1 1 ≤5 1 UWG1C101MCR1GS F551A107MN UPM1A101MEH Sanyo Os-con\ POS-Cap SVP (SMT) SP 10V 6.3 V 10 V 68 47 56 0.025 Ω 0.074 Ω 0.045 Ω 2400 mA 1110 mA 1710 mA 7.3×4.3 5×6 6.3×5.0 1 1 1 ≤5 ≤5 ≤5 10TPE68M 6SVP47M 10SP56M AVX Tantalum TPS (SMD) 10 V 10 V 47 47 0.100 Ω 0.060 Ω 1100 mA > 412 mA 7.3L × 4.3W × 4.1H 1 1 ≤5 ≤5 TPSD476M010R0100 TPSB476M010R0500 Kemet T520 (SMD) AO-CAP 10 V 6.3 V 68 47 0.060 Ω 0.028 Ω >1200 mA >1100 mA 7.3L × 5.7W × 4.0H 1 1 ≤5 ≤3 T520V686M010ASE060 A700V476M006AT Vishay/Sprague 594D/595D (SMD) 10 V 10 V 68 68 0.100 Ω 0.240 Ω >1000 mA 680 mA 7.3L × 6.0W × 4.1H 1 1 ≤5 ≤5 594D686X0010C2T 595D686X0010C2T 94SL 16 V 47 0.070 Ω 1550 mA 8×5 1 ≤5 94SL476X0016EBP TDK Ceramic X5R Murata Ceramic X5R Kemet 6.3 V 6.3 V 6.3 V 22 22 22 0.002 Ω 0.002 Ω 0.002 Ω >1400 mA >1000 mA >1000 mA 1210 case 3225 mm ≥ 2 (3) ≥ 2 (3) ≥ 2 (3) ≤3 ≤3 ≤3 C3225X5R0J226KT/MT GRM32ER61J223M C1210C226K9PAC TDK Ceramic X5R Murata Ceramic X5R Kemet 6.3 V 6.3 V 6.3 V 47 47 47 0.002 Ω 0.002 Ω 0.002 Ω >1400 mA >1000 mA >1000 mA 1210 case 3225 mm ≥1 ≥1 ≥1 ≤3 ≤3 ≤3 C3225X5R0J476KT/MT GRM32ER60J476M/6.3 C1210C476K9PAC CAPACITOR VENDOR/ COMPONENT SERIES (1) (2) (3) 10 PHYSICAL SIZE (mm) INPUT BUS (1) OUTPUT BUS VENDOR NUMBER EEFWA1A121P (2) EEVFC1E470P (2) A ceramic capacitor is required on both the input and the output. An electrolytic capacitor can be added to the output for improved transient response. An optional through-hole capacitor available. A total capacitance of 44 µF is an acceptable replacement for a single 47-µF capacitor. PTH04070W www.ti.com SLTS227 – SEPTEMBER 2004 Power-Up Characteristics When configured per the standard application, the PTH04070 power module produces a regulated output voltage following the application of a valid input source voltage. During power up, internal soft-start circuitry slows the rate that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input source. The soft-start circuitry introduces a short time delay (typically 10 ms) into the power-up characteristic. This is from the point that a valid input source is recognized. Figure 10 shows the power-up waveforms for a PTH04070W, operating from a 3-V input and with the output voltage adjusted to 1.8 V. The waveforms were measured with a 2-A resistive load. VI (1 V/div) VO (1 V/div) II (1 A/div) t − 10 ms/div Figure 10. Power-Up Waveforms Current Limit Protection The PTH04070 modules protect against load faults with a continuous current limit characteristic. Under a load fault condition, the output current cannot exceed the current limit value. Attempting to draw current that exceeds the current limit value causes the output voltage to be progressively reduced. Current is continuously supplied to the fault until it is removed. Upon removal of the fault, the output voltage will promptly recover. Thermal Shutdown Thermal shutdown protects the module internal circuitry against excessively high temperatures. A rise in temperature may be the result of a drop in airflow, a high ambient temperature, or a sustained current limit condition. If the junction temperature of the internal components exceeds 150°C, the module shuts down. This reduces the output voltage to zero. The module will start up automatically, by initiating a soft-start power up when the sensed temperature decreases 10°C below the thermal shutdown trip point. Output On/Off Inhibit For applications requiring output voltage on/off control, the PTH04070 power module incorporates an output on/off Inhibit control (pin 5). The inhibit feature can be used wherever there is a requirement for the output voltage from the regulator to be turned off. The power module functions normally when the Inhibit pin is left open-circuit, providing a regulated output whenever a valid source voltage is connected to Vin with respect to GND. Figure 11 shows the typical application of the inhibit function. Note the discrete transistor (Q1). The Inhibit control has its own internal pullup to VI potential. An open-collector or open-drain device is recommended to control this input. 11 PTH04070W www.ti.com SLTS227 – SEPTEMBER 2004 Turning Q1 on applies a low voltage to the Inhibit control pin and disables the output of the module. If Q1 is then turned off, the module will execute a soft-start power-up sequence. A regulated output voltage is produced within 20 msec. Figure 12 shows the typical rise in the output voltage, following the turn off of Q1. The turn off of Q1 corresponds to the fall in the waveform, Q1 Vgs. The waveforms were measured with a 2-A resistive load. VI = 5 V 1 PTH04070W VIN VO 3 VO = 1.8 V Inhibit GND VO Adj 5 4 2 C1 47-µF RSET 6.65 k 0.05 W 1% Ceramic Inhibit Q1 BSS138 C2 47-µF Ceramic GND GND Figure 11. On/Off Inhibit Control Circuit VO (1 V/div) II (1 A/div) Q1, Vgs (10 V/div) t − 5 ms/div Figure 12. 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