TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 LOW PIN COUNT, LOW VIN (2.5 V TO 5.5 V) SYNCHRONOUS BUCK DC-TO-DC CONTROLLER WITH ENABLE FEATURES • • • • • • • • • • • • • CONTENTS 2.25-V to 5.5-V Input Output Voltage from 0.6 V to 90% of VIN High-Side Drive for N-Channel FET Supports Pre-Biased Outputs Adaptive Anti-Cross Conduction Gate Drive 1%, 0.6-V Reference Two Fixed Switching Frequency Versions, TPS40040 (300 kHz) and TPS40041 (600 kHz) Three Selectable Short Circuit Protection Levels of 105 mV, 180 mV and 310 mV Hiccup Restart from Faults Voltage Mode Control Active Low Enable Thermal Shutdown Protection at 145°C 8-Pin, 3-mm x 3-mm SON with Ground Connection to Thermal Pad Device Ratings 2 Electrical Characteristics 3 Device Information 8 Application Information 10 Design Examples 19 Additional References 32 DESCRIPTION The TPS40040 and TPS40041 dc-to-dc controllers are designed to operate from a 2.25-V to 5.5-V input source. To reduce the number of external components, several operating parameters are fixed internally; namely, frequency, soft start time, and short circuit protection (SCP) levels. For example, the operating frequencies of TPS40040/1 are 300 kHz/600 kHz, respectively. APPLICATIONS • • • • Point of Load Telecommunications DC to DC Modules Set Top Boxes SIMPLIFIED APPLICATION DIAGRAM VIN TPS40040/1 1 EN HDRV 8 2 FB SW 7 3 COMP 4 VDD VOUT BOOT 6 GND LDRV 5 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. Predictive Gate Drive is a registered trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 DESCRIPTION (CONT.) One of three short circuit threshold levels may be selected by the addition of an external resistor from the COMP pin to circuit ground. During power on, and before the internal soft start commands the output voltage to rise, the TPS40040/1 enters a calibration cycle, measures the current out of the COMP pin, and selects an internal SCP threshold voltage. At the end of the 1.6-ms calibration time, the output voltage is allowed to rise for a 4-ms soft start. During operation, the selected SCP threshold voltage is compared to the upper MOSFET’s voltage drop during its ON time to determine whether there is an overload condition. The packaging of the TPS40040/1 is unique in that the PowerPAD™ is used as an electrical ground connection as well as a thermal connection. ORDERING INFORMATION OPERATING FREQUENCY PACKAGE TAPE AND REEL QTY. PART NUMBER 300 kHz Plastic 8-pin SON (DRB) 250 TPS40040DRBT 300 kHz Plastic 8-pin SON (DRB) 2500 TPS40040DRBR 600 kHz Plastic 8-pin SON (DRB) 250 TPS40041DRBT 600 kHz Plastic 8-pin SON (DRB) 2500 TPS40041DRBR DEVICE RATINGS ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted, all voltages are with respect to GND.) PARAMETER VALUE VDD UNIT 6.5 SW -3 to 10.5 SW transient (< 50 ns) -5 BOOT SW+6.5 HDRV SW to SW+6.5 EN, FB, LDRV V -0.3 to 6.5 COMP -0.3 to 3 Operating junction temperature -40 to 150 Storage junction temperature -55 to 150 °C RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PARAMETER VIN Input voltage TJ Junction temperature MIN TYP MAX UNIT 2.25 5.5 V -40 125 °C ELECTROSTATIC DISCHARGE (ESD) PROTECTION PARAMETER MIN TYP MAX UNIT Human body model 2500 V CDM 1500 V PACKAGE DISSIPATION RATINGS (1) (1) 2 THERMAL IMPEDANCE JUNCTION-TO-AMBIENT TA = 25°C POWER RATING TA = 85°C POWER RATING 48°C/W 2W 0.8W For more information on the DRB package and the test method, refer to TI technical brief, literature number SZZA017. TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 ELECTRICAL CHARACTERISTICS TJ = -40 °C to 85°C VDD = 5 V, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input Supply VDD Input voltage range 2.25 5.5 V IDDsd Shutdown EN = VDD IDDq Quiescent FB = 0.8 V 100 180 µA 1.0 2.0 IDDs Switching current No load at HDRV/LDRV 2.0 UVLOON Minimum turn-on voltage UVLOHYS Hysteresis mA 1.95 2.05 2.15 V 80 130 200 mV Oscillator/ Ramp Generator fPWM TPS40040 PWM frequency 2.25 V < VDD < 5.5 V 250 300 350 kHz fPWM TPS40040 PWM frequency VDD = 5.0 V, 0°C < TJ < 70°C 270 300 330 kHz fPWM TPS40041 PWM frequency 2.25 V < VDD < 5.5 V 500 600 700 kHz fPWM TPS40041 PWM frequency VDD = 5.0 V, 0°C < TJ < 70°C 540 600 660 kHz VRAMP Ramp amplitude PP VPEAK– VVALLEY 0.75 0.87 1.0 V VVALLEY Ramp valley voltage 0.37 V PWM MAXDUTY Maximum duty cycle, TPS40040 VFB = 0 V, 2.25 V < VDD < 5.5 V 90 95 Maximum duty cycle, TPS40041 VFB = 0 V, 2.25 V < VDD < 5.5 V 88 95 MINDUTY Minimum duty cycle MIN pulse width (1) Minimum controllable pulse width % 0 Minimum width control range before jumping to zero. 90 150 600.0 606.5 ns Error Amplifier VDD = 5.0 V, 0°C < TJ < 70°C 593.5 VFB FB input voltage IFB FB input bias current VOH High level output voltage IOH = 0.5 mA, VFB = 0 V, VDD = 5.5 V VOL Low level output voltage IOL = 0.5 mA, VFB = VDD IOH Output source current VCOMP = 0.7 V, VFB = GND 1 6 IOL Output sink current VCOMP = 0.7 V, VFB = VDD 2 8 GBW (1) Gain bandwidth 5 10 MHz AOL Open loop gain 55 85 dB 2.25 V < VDD < 5.5 V, -40°C < TJ < 125°C 590 610 50 2.0 150 2.5 80 mV nA V 150 mV mA Short Circuit Protection TH1 Low short circuit threshold voltage Resistor COMP to GND = 2.4 kΩ, TJ = 25°C 80 105 130 VTH2 Medium short circuit threshold voltage Default: No resistor COMP to GND, TJ = 25°C 145 180 215 VTH3 High short circuit threshold voltage Resistor COMP to GND = 12 kΩ, TJ = 25°C 250 310 370 VTH(tc) (1) Threshold temperature coefficient 3100 Minimum HDRV pulse time in over current 200 tSWOCblank (1) SW leading edge blanking pulse in over current detection 100 tHICCUP Hiccup time between restarts tON(oc) (1) (1) mV ppm ns 40 ms Ensured by design. Not production tested. 3 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 ELECTRICAL CHARACTERISTICS (continued) TJ = -40 °C to 85°C VDD = 5 V, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Soft Start/Enable tCAL (2) Calibration time before softstart begins tSS (2) Soft start time FB rise time from 0 V to 600 mV tREG Time to voltage regulation Sum of tCAL plus tSS VEN Enable threshold EN voltage w.r.t. VDD VENHYS Enable hysteresis 1.0 1.6 2.5 3.0 4.0 6.0 4.0 5.6 8.5 -0.8 -1.2 -1.6 50 ms V mV Bootstrap RBOOT3V3 RBOOT5V Bootstrap switch resistances VBOOT to VDD, VDD = 3.3 V 50 VBOOT to VDD, VDD = 5 V 30 Ω Output Driver RHDHI3V3 HDRV pull-up resistance VBOOT - VSW = 3.3 V, ISRCE = 100 mA 3.0 RHDLO3V3 HDRV pull-down resistance VBOOT - VSW = 3.3 V, ISINK = 100 mA 1.5 3 RLDHI3V3 LDRV pull-up resistance VDD = 3.3 V, ISOURCE = 100 mA 3.0 5.5 RLDLO3V3 LDRV pull-down resistance VDD = 3.3 V, ISINK = 100 mA 1.0 2.0 tRISE (3) LDRV, HDRV rise time CLOAD = 1 nF 15 35 10 25 tFALL (3) LDRV, HDRV fall time CLOAD = 1 nF TDEAD HL Adaptive timing HDRV to LDRV No load 15 30 TDEAD LH Adaptive timing LDRV to HDRV No load 5 15 Leakage current EN = VDD 5.5 Ω ns SW Node ILEAK µA -2 Thermal Shutdown tSD (3) Shutdown temperature Hysteresis (2) (3) 4 tCAL and tSS track with temperature and input voltage Ensured by design. Not production tested. 145 15 °C TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 TYPICAL CHARACTERISTICS Quiescent Current (Non-Switching) Shutdown Current 1.100 110 1.000 105 VDD = 5.5 V 100 IDDsd − µA 0.900 IDDq − mA VDD = 2.25 V 0.800 0.700 95 90 85 0.600 80 0.500 VDD = 2.25 V 0.400 −40 −20 VDD = 5.5 V 75 70 0 20 40 60 80 Temperature − C 100 120 −40 −20 0 20 40 60 80 Temperature − C Figure 1. Figure 2. UVLO Threshold EN Threshold 2.200 −0.8 Turn ON Turn OFF Enable Threshold Relative to VDD − V UVLO Threshold − V 2.150 2.100 2.050 2.000 1.950 1.900 1.850 1.800 VDD = 5 V −0.9 −1.0 −1.1 −1.2 −1.3 −1.4 −1.5 −1.6 −40 −20 0 20 40 60 80 Temperature − C 100 120 −40 −20 0 20 40 60 80 Temperature − C 100 120 Figure 3. Figure 4. Oscillator Frequency (TPS40040) Oscillator Frequency (TPS40041) 350 700 VDD =2.25 V VDD =3.9 V VDD = 2.25V VDD = 5 V 325 300 275 VDD = 5.5V 600 550 250 −40 VDD = 3.9V 650 Frequency − KHz Frequency − KHz 100 120 −20 0 20 40 60 80 Temperature − C Figure 5. 100 120 500 −40 −20 0 20 40 60 80 Temperature − C 100 120 Figure 6. 5 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 TYPICAL CHARACTERISTICS (continued) Soft Start Time FB Voltage 4.50 610 VDD = 2.25 V VDD = 3.9 V VDD = 5.5 V 608 VDD = 5 V 4.45 606 604 VFB − mV TSS − ms 4.40 4.35 602 600 598 4.30 596 594 4.25 592 590 4.20 −40 −20 0 20 40 60 80 Temperature − C −40 100 120 −20 0 Figure 7. 20 40 60 80 Temperature − C 100 120 Figure 8. PWM Gain (TPS40040) PWM Gain (TPS40041) 6.1 6.0 VDD = 5 V VDD = 5 V 6.0 5.9 5.9 Gain Gain 5.8 5.8 5.7 5.7 5.6 5.6 5.5 5.5 −40 −20 0 20 40 60 80 Temperature − C −40 100 120 −20 0 Figure 9. 100 120 Figure 10. ILIM Threshold Bootstrap Switch Resistance 450 400 20 40 60 80 Temperature − C 80 RC = 2.5 kΩ RC =nil VDD = 3.3 V RC = 12.5 kΩ VDD = 5 V 70 Switch Resistance − Ω ILIM Threshold − mV 350 300 250 200 150 50 40 20 −20 0 20 40 60 80 Temperature − C Figure 11. 6 50 30 100 −40 60 100 120 −40 −20 0 20 40 60 80 Temperature − C Figure 12. 100 120 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 TYPICAL CHARACTERISTICS (continued) Minimum Controllable Pulse Width (TPS40040) Minimum Controllable Pulse Width (TPS40041) 100 130 VDD = 2.25 V 95 VDD = 5.5 V 125 Pulse Width − ns Pulse Width − ns 90 120 115 110 85 80 75 105 70 100 65 VDD = 2.25 V 95 −40 −20 0 20 40 60 80 Temperature − C 60 −40 100 120 −20 0 Figure 13. 20 40 60 80 Temperature − C 100 120 Figure 14. Maximum Duty Cycle SW Node Leakage Current 100 0.00 VDD = 2.25 V VDD = 5.5 V −0.50 VDD = 5.5 V −0.10 98 −0.15 ISW − µA Duty Cycle − % VDD = 5.5 V 96 −0.20 −0.25 −0.30 94 −0.35 −0.40 92 −0.45 90 −40 −20 0 20 40 60 80 Temperature − C Figure 15. 100 120 −0.50 −40 −20 0 20 40 60 80 Temperature − C 100 120 Figure 16. 7 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 DEVICE INFORMATION TERMINAL CONFIGURATION The package is an 8-pin SON (DRB) package. Note: The thermal pad is an electrical ground connection. TPS40040/1 1 EN HDRV 8 2 FB SW 7 3 COMP BOOT 6 4 VDD LDRV 5 GND Figure 17. DRB Package Terminal Configuration (Top View) Table 1. TERMINAL FUNCTIONS TERMINAL NAME BOOT COMP NO. 6 3 I/O DESCRIPTION I Input (bootstrapped) supply to the high-side gate driver for PWM enabling the gate of the high side FET to be driven above the input supply rail. Connect a ceramic capacitor from this pin to SW. This capacitor is charged from the VDD pin voltage through an internal switch. The switch is turned ON during the off time of the converter. To slow down the turn on of the external MOSFET, a small resistor (1 Ω to 3 Ω) may be placed in series with the bootstrap capacitor. See Applications Section to calculate the appropriate value. O Output of the error amplifier and connection node for loop feedback components. The voltage at this pin determines the duty cycle for the PWM. Optionally, a resistor from this pin to ground is used to determine the voltage threshold used for short circuit protection. (See Application Section) • Low threshold R = 2.4 kΩ, +/-10% • Mid threshold R = not installed • High threshold R = 12 kΩ, +/-10% EN 1 I Active low enable input allows ON/OFF operation of the controller. If power is applied to the TPS40040/1 while the EN pin is allowed to float high, the TPS40040/1 remains disabled (both external switches are held OFF). Only when the EN pin is pulled to 1.2 V below VDD is the TPS40040/1 allowed to start. An internal 100-kΩ resistor is connected between VDD and EN to provide pull up. Connect this pin to GND to bypass the enable function. FB 2 I Inverting input of the error amplifier. In closed loop operation, the voltage at this pin is at the internal reference level of 600 mV. A series resistor divider from the converter output to ground, with the center connection tied to this pin, determines the value of the regulated output voltage. This pin is also a connection node for loop feedback components. HDRV 8 O This is the gate drive output for the high side N-channel MOSFET switch for PWM. It is referenced to SW and is bootstrapped for enhancement of the high-side switch. LDRV 5 O Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET. VDD 4 I Power input to the device. This pin should be locally bypassed to GND with a low ESR ceramic capacitor of 1 µF or greater. O Connection to the switched node of the converter and the power return for the upper gate driver. There should be a high current return path from the source of the upper MOSFET to this pin. It is also used by the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET conduction. SW GND 8 7 Thermal Pad Ground connection to the device. This is also the thermal pad used to conduct heat from the device. This connection serves a twofold purpose. The first is to provide an electrical ground connection for the device. The second is to provide a low thermal impedance path from the device die to the PCB. This pad should be tied externally to a ground plane. See Application Section for PC board layout information. TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 Block Diagram VDD VDD 4 VDD/2 UVLO SW SDN 100K 2V EN EN 1 100ns DELAY FAULT LOGIC ILIM SET CURRENT LIMIT COMP Vdd−1.2v VDD SDN CLOCK 0.6 V VREF Soft Start FB 2 COMP 3 LDRV PWM COMP + + − PWM PWM LOGIC RAMP VDD OSCILLATOR 0.6V VREF Reference HI ILIM SET ILIM voltages 105 mV 180 mV 310 mV BOOT 8 HDRV 7 SW 5 LDRV CLOCK ADAPTIVE GATE DRIVE Calibration Circuit 6 VDD LO Thermal Shutdown Pre−bias PAD GND Figure 18. Functional Block Diagram 9 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 APPLICATION INFORMATION Functional Description The TPS40040 (300 kHz) and TPS40041 (600 kHz) are fixed-frequency voltage-mode synchronous buck controllers. In operation, the synchronous rectifier (SR) is allowed to conduct current in both directions, allowing a converter to operate in continuous mode, even under no load conditions, simplifying feedback loop compensation requirements. During startup, internal circuitry modulates the switching of the synchronous rectifier to prevent discharging of the output if a pre-biased condition exists. Voltage Reference The 600-mV bandgap reference voltage cell is internally connected to the non-inverting input of the error amplifier. The voltage reference is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final regulation voltage. Voltage Error Amplifier The error amplifier has a bandwidth of greater than 5 MHz, and open loop gain of at least 55 dB. The output voltage swing is limited to just above and below the oscillator ramp levels to improve transient response. Loop Compensation Voltage mode buck type converters are typically compensated using Type III networks. Please refer to the Design Example for detailed methodology in designing feedback loops for voltage mode converters. Oscillator The oscillator frequency is internally fixed. The TPS40040/1 operating frequencies are 300 kHz/600 kHz, respectively. UVLO When the input voltage is below the UVLO threshold, the TPS40040/1 turns off the internal oscillator and holds all gate drive outputs in the low (OFF) state. When the input rises above the UVLO threshold, and the EN pin is below the turn ON threshold, the start-up sequence is allowed to begin. 10 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 APPLICATION INFORMATION (continued) Enable and Start-Up Sequence The EN pin of the TPS40040/1s internally pulled to VDD. When power is applied to VDD, the EN pin is allowed to float high, and the TPS40040/1 remains OFF. Only when the EN pin is externally pulled below the threshold voltage of VDD - 1.2 V is the TPS40040/1 allowed to start. When enabled, the TPS40040/1 enters a calibration cycle where the short circuit current threshold is determined. The TPS40040/1 monitors the current out of the COMP pin and selects a threshold based on the sensed value of the current. See Selecting the Short Circuit Current Limit Threshold section for for details. When this calibration time is completed, the soft-start cycle is allowed to begin. See Figure 19 below. ENB COMP VOUT 1.5 ms Configure ILIM Threshold 4 ms Soft Start Figure 19. Startup DESIGN HINT: If the enable function is not used, the EN pin should be connected to ground (GND). DESIGN HINT: When designing the feedback loop compensation, ensure the capacitors used are not so large that they distort the COMP pin calibration waveform. Soft Start At the end of a calibration cycle, the TPS40040/1 slowly increases the voltage to the non-inverting input of the error amplifier. In this way, the output voltage slowly ramps up until the voltage on the non-inverting input to the error amplifier reaches the internal reference voltage. At that time, the voltage at the non-inverting input to the error amplifier remains at the reference voltage. During the soft-start interval, pulse-by-pulse current limiting is active. If seven consecutive current limit pulses are detected, overcurrent is declared and a timeout period equivalent to seven calibration/soft-start cycles goes into effect. See Output Short Circuit Protection section for details. 11 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 APPLICATION INFORMATION (continued) Pre-Bias Startup The TPS40040/1 supports pre-biased output voltage applications. In cases where the output voltage is held up by external means while the TPS40040/1 is off, full synchronous rectification is disabled during the initial phase of soft starting the output voltage. When the first PWM pulses are detected during soft start, the controller slowly initiates synshronous rectification by starting the synchronous rectifier with a narrow on time. It then increments that on time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This approach prevents the sinking of current from a pre-biased output, and ensures the output voltage startup and ramp to regulation is smooth and controlled. NOTE: If the output is pre-biased, PWM pulses start when the internal soft-start voltage rises above the error amplifier input (FB pin). Figure 20 below depicts the waveform of the HDRV and LDRV output signals at the beginning PWM pulses. When HDRV turns off, diode rectification is enabled. Before the next PWM cycle starts, LDRV is turned on for a short pulse. With every clock cycle, the leading edge of LDRV is modulated, increasing the on time of the synchronous rectifier. Eventually, the leading edge of LDRV coincides with the falling edge of HDRV to achieve full synchronous rectification. During normal operation of the converter, the TPS40040/1 operates in full two quadrant source/sink mode. Figure 21 shows the startup waveform of a 1.2-V output converter under three different pre-biased output conditions. The lowest trace is when there is no pre-bias on the output. The center and top most traces indicate converter startup with 0.5-V and 1.0-V pre-bias conditions. VIN = 5 V VOUT = 1.2 V (200 mV/div) PREBIAS = 1 V VHDRV PREBIAS = 0.5 V PREBIAS = 0 V VLDRV t − Time − 2 µs/div Figure 20. MOSFET Drivers at Beginning of Soft Start t − Time − 500 µs/div Figure 21. Startup Waveforms The recommended output voltage pre-bias range is less than or equal to 90% of the final regulation voltage. A pre-biased output voltage of 90% to 100% of final regulation could lead to the sinking of current from the pre-bias source. If the pre-biased voltage is greater than the designed converter output regulation voltage, then upon the completion of the soft-start interval, the TPS40040/1 draws current from the output to bring the output voltage into regulation. 12 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 APPLICATION INFORMATION (continued) Output Short Circuit Protection To minimize circuit losses, the TPS40040/1 uses the RDS(on) of the upper MOSFET switch as the current sensing element. The current limit comparator, initially blanked during the first portion of each switching cycle, senses the voltage across the high-side MOSFET when it is fully ON. This voltage is compared to an internally selected short circuit current (SCC) limit threshold voltage. If the comparator senses a voltage drop across the high-side MOSFET greater than the SCC limit threshold, it outputs an OC pulse. This terminates the current PWM pulse preventing further current ramp-up, and sets the fault counter to count up one count on the next clock cycle. Similarly, if no OC pulse is detected, the fault counter decrements by one count. If seven OC pulses are summed, a fault condition is declared and the upper switch of the PWM output of the chip is immediately disabled (turned OFF) and remains that way until the fault time-out period has elapsed. Both HDRV and LDRV drivers are kept OFF during the fault time-out. The fault time-out period is determined by cycling through seven internal soft-start time periods. At the end of the fault time-out period, startup is attempted again. The main purpose is for hard fault protection of the power switches. The internal SCC voltage has a positive temperature coefficient designed to improve the short circuit threshold tolerance variation with temperature. However, given the tolerance of the voltage thresholds and the RDS(on) range for a MOSFET, it is possible to apply a load that thermally damages the external MOSFETs. Selecting the Short Circuit Current Limit Threshold The TPS40040/1 uses one of three user selectable voltage thresholds. During the calibration interval at power on or enable (Figure 19), the TPS40040/1 monitors the current out of the COMP pin and selects a threshold based on the sensed value. If the current is zero; that is, no resistor is connected between COMP and GND, then the threshold voltage level is 180 mV. If a 2.4-kΩ resistor is connected between COMP and GND, then the threshold voltage level is 105 mV. If a 12-kΩ resistor is connected between COMP and GND, then the threshold voltage is 310 mV. Once calibration is complete, the selected SCP threshold level is latched into place and remains constant. In addition, the sensing circuits on COMP pin during calibration are disconnected from the COMP pin, and soft start is allowed to begin. Synchronous Rectification and Gate Drive In a buck converter, when the upper switch MOSFET turns off, current is flowing in the inductor to the load. This current cannot be stopped immediately without using infinite voltage. To give this current a path to flow and maintain voltage levels at a safe level, a rectifier or catch device is used. This device can be either a diode, or it can be a controlled active device. The TPS40040/1 provides a signal to drive an N-channel MOSFET as a synchronous rectifier (SR). This control signal is carefully coordinated with the drive signal for the main switch so that there is minimum dead time from the time that the SR turns OFF and the upper switch MOSFET turns ON, and minimum delay from when the upper switch MOSFET turns OFF and the SR turns ON. NOTE: The longer the time spent in diode conduction during the rectifier conduction period, the lower the converter efficiency. The drivers for the external HDRV and LDRV MOSFETs are capable of driving a gate to source voltage of approximately 5 V. At VDD = 5 V, the drivers are capable of driving MOSFETs appropriate for a 15-A converter. The LDRV driver switches between VDD and ground, while HDRV driver is referenced to SW and switches between BOOT and SW. The drivers have non-overlapping timing that is governed by an adaptive delay circuit that minimizes body diode conduction in the synchronous rectifier. 13 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 APPLICATION INFORMATION (continued) Gate Drive Resistors The TPS40040/41’s adaptive gate delay circuitry monitors the HDRV-to-SW and LDRV-to-GND voltages to determine the state of the external MOSFET switches. Any voltage drop across an external series gate drive resistor is sensed as reduced gate voltage during turn-off and may interfere with the MOSFET timing. DESIGN HINT: A resistor should never be placed in series with the synchronous rectifiers gate and the gate trace should be kept as short as practical in the layout. Total Gate Charge The internal voltage sensing of the external MOSFET gate voltages used by the TPS40040/1 to control the dead-times between turn-off and turn-on can be sensitive to large MOSFET gate charges, especially when different gate charges are used for the high-side and low-side MOSFETs. Increased gate charge increases MOSFET switching times and decreases the dead-time between the MOSFETs switching. DESIGN HINT: MOSFETs with no more than 40 nC of total gate charge should be selected. The upper switch MOSFET’s gate charge should be no less than 60% of the synchronous rectifier’s gate charge to minimize the turn-on/turn-off delay mismatch between the high-side and low-side MOSFET. Synchronous Rectifier dV/dt Turn-On As the upper switch MOSFET turns on, the switch node voltage rises from close to ground to VIN in a very short period of time (typically 10 ns to 30 ns) resulting in very high voltage spikes on the switch node. The construction of a MOSFET creates parasitic capacitances between its terminals, particularly the gate-to-drain and gate-to-source, creating a capacitive divider between the drain and source of the MOSFET with the gate at its mid-point. If the gate-to-drain charge (QGD) is larger than the gate-to-source charge (QGS), the capacitive divider places proportionally more charge on the gate of the MOSFET as the switch node voltage rises than is shunted to GND. In extreme cases, this can cause the synchronous rectifier gate voltage to rise above the turn on threshold voltage of the MOSFET and causes cross-conduction. This is called dV/dt turn-on. It increases power dissipation in both the high-side and the low-side MOSFET, reducing efficiency. 14 DESIGN HINT: Select a synchronous rectifier MOSFET with a QGD to QGS ratio of less than one and provide a wide, low resistance, low inductance loop in the synchronous rectifier gate drive circuit. (See Layout Consideration) DESIGN HINT: A resistor in series with the boost capacitor slows the turn on of the high-side MOSFET, and reduces the dV/dt of the switch node. See Boost Capacitor Series Resistor section. TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 APPLICATION INFORMATION (continued) Bootstrap for N-Channel MOSFET Drive The PWM duty cycle is limited to a maximum of 95%, allowing the bootstrap capacitor to charge during every cycle. During each PWM OFF period, the voltage on VDD charges the bootstrap capacitor. When the PWM switch is next commanded to turn ON, the voltage used to drive the MOSFET is derived from the voltage on this capacitor. Since this is a charge transfer circuit, the value of the bootstrap capacitor must be sized such that the energy stored in the capacitor on a per cycle basis is greater then the gate charge requirement of the MOSFET being used. See the Design Example section for details. Bootstrap Capacitor Series Resistor Since resistors should not be placed in series with the high-side gate, it may be necessary to place a small 1-Ω to 3-Ω resistor in series with the bootstrap capacitor to control the turn-on of the main switching MOSFET and reduce the dV/dt rate of rise of the switch node voltage. A resistor placed between the BOOT pin and the bootstrap capacitor increases the series resistance during the turn-on of the high-side MOSFET, and has no effect during the high-side MOSFET’s turn-off period. This prevents the TPS40040/1 from sensing the upper switch MOSFET’s turn-off too early and reducing the upper switch MOSFET turn-off to the SR MOSFET turn-on delay timing too far. DESIGN HINT: To reduce EMI, place a small 1-Ω to 3-Ω resistor in series with the boost capacitor to control the turn-on of the main switching FET. External Schottky Diode for Low Input Voltage The TPS40040/1 uses an internal P-channel MOSFET switch between VDD and BOOT to charge the bootstrap capacitor during synchronous rectifier conduction time. At low input voltages, a MOSFET can not be turned on hard enough to rapidly replenish the charge required to turn on an (high gate charge) external high-side MOSFET. For this situation, an external Schottky diode between the VDD and BOOT pins may be added. While the diode carries very small average current (QG x FSW) it may be required to carry several hundred mA of peak surge current. The diode should be rated for at least 500 mA of surge current. For higher input voltage applications, if a resistor is used in series with the boost capacitor, connect the diode to the junction of the resistor and capacitor to remove the added resistance from the capacitor’s charge path. DESIGN HINT: For low input voltages, and a high gate charge upper switch MOSFET, a small Schottky diode should be placed from VDD to BOOT. Do not use a resistor in series with the boost capacitor. VDD Bypass and Filtering To prevent switching noise from being injected into the TPS40040/1 control circuitry, a ceramic capacitor (1 µF minimum) must be placed as close to the VDD pin and GND pad as possible. 15 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 APPLICATION INFORMATION (continued) VDD Filter Resistor To further limit the noise on VDD, a small 1-Ω to 2-Ω resistor may be placed between the input voltage and the VDD pin to create a small filter to VDD. The resistor should connect near the drain of the upper switch MOSFET to prevent trace IR drops from increasing the sensed voltage drop. The resistor itself should be placed close to Pin 4. The current through the resistor includes the device's no-load switching current of 2 mA plus gate switching current. The voltage drop induced across this resistor reduces the VDD-to-SW voltage sensed by the over current protection circuitry within the device. This results with the apparent voltage drop across the upper switch MOSFET being increased, thereby decreasing the current at which protection will occur. To minimize this effect, the resistor value should be selected to yield less than a 25-mV drop. Thermal Shutdown If the junction temperature of the device reaches the thermal shutdown level, the PWM and the oscillator are turned off and HDRV and LDRV are driven off. When the junction cools to the required level, the PWM soft starts as during a normal power-up cycle. Package Power Dissipation The power dissipation in a controller is largely dependent on the MOSFET driver currents and the input voltage. The driver current is proportional to the total gate charge, QG, of the external MOSFETs, and the operating frequency of the converter. Driver power, neglecting external gate resistance, is calculated from: P D(driver) Q G VDRIVE F SW Wdriver (1) And the total power dissipation, assuming the same MOSFET is selected for both the high side and synchronous rectifier is: 2 PD PT I Q V DD W V DRIVE (2) or P T 2 G Q F SW I Q V DD W (3) where IQ is the quiescent operating current (neglecting drivers). The max power capability of the PowerPad™ package is dependent on the layout as well as air flow. The thermal impedance from junction-to-air assuming 2-oz copper trace and thermal pad with solder and no air flow is detailed in Reference [5]. 16 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 APPLICATION INFORMATION (continued) PCB Layout Guidelines A synchronous BUCK power stage has two primary current loops, the input current loop that carries high ac discontinuous current and an output current loop that carries high dc continuous current. The output current loop carries low ac inductor ripple current. VIN VDD Filter (Optional) Main Gate TPS40041 EN HDRV FB SW Drive Enable Input Current Loop VOUT Enable Bypass (Optional) COMP BOOT BOOST Resistor (Optional) VDD LDRV Output Current Loop (Power Pad) Current Limit Set Resistor GND VDD Bypass Signal Ground SR Gate Drive Power Ground Locate Parts Over Power Ground Locate Parts Over Signal Ground Island Figure 22. Synchronous BUCK Power Stage Power Component Routing As shown in Figure 22, the input current loop contains the input capacitors, the switching MOSFET, the inductor, the output capacitors, and the ground path back to the input capacitors. To keep this loop as small as possible, it is good practice to place some ceramic capacitance directly between the drain of the main switching MOSFET and the source of the synchronous rectifier (SR) through a power ground plane directly under the MOSFETs. The output current loop includes the filter inductor, the output capacitors, and the ground return between the output capacitors and the source of the synchronous rectifier MOSFET. As with the input current loop, the ground return between the output capacitor ground and the source of the SR source should be routed under the inductor and MOSFETs to minimize the power loop area. 17 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 APPLICATION INFORMATION (continued) Device to Power Stage Interface The TPS40040/1 uses a very fast break-before-make anti-cross conduction circuit to minimize power loss. Adding external impedance in series with the gates of the switching MOSFETs adversely affects the converter’s operation and must be avoided. The loop impedance (HDRV-to-gate plus source-to-SW and LDRV-to-SR gate plus SR source-to-GND) should be kept to less than 20 nH to avoid possible cross-conduction. The HDRV and LDRV connections should widen to 20 mils as soon as possible out from the device pin. The return for the main switching MOSFET gate drive is the SW pin of the TPS40040/1. The SW pin should be routed to the source of the main switching FET with at least a 20-mils wide trace as close to the HDRV trace as possible to minimize loop impedance. The return for the SR MOSFET gate drive is the TPS40040/1 GND pad. The GND pad should be connected directly to the source of the SR with at least a 20-mil wide trace directly under the LDRV trace. Use a minimum of 2 parallel vias to connect the GND pad to the source of the SR if multiple layers are used. A small, less than 3-Ω resistor may be added in series with the BOOT pin to slow the turn-on of the upper switch MOSFET, thereby reducing the rising edge slew-rate of the switch node. In turn, this reduces EMI, increases upper MOSFET OFF to SR ON dead time, and minimizes induced dV/dt turn-on of the SR when the upper switch MOSFET turns on. It is recommended customers make provisions on their boards for this resistor and not use resistors in series with MOSFET gate leads. VDD Filtering A ceramic capacitor, 1 µF minimum, must be placed as close to the VDD pin and GND pad as possible with a 15-mil wide (or greater) trace. If used, a small series connected resistor (1 Ω to 2 Ω) may be placed less than 100 mils from the TPS40040/1 between the supply input voltage and the VDD pin to further reduce switching noise on the VDD pin. NOTE: The voltage drop across this resistor affects the level at which the over-current circuit operates by filtering the sensed VDD voltage. Device Connections If a current limit resistor is used (COMP to GND), it must be placed within 100 mils of the COMP pin to limit noise injection into the PWM comparator. Compensation components (feedback divider, and associated error amplifier components) should be placed over a signal ground island connected to the power ground at the GND pad through a 10-mil wide trace. If multiple layers are used, connect to GND through a single via on an internal layer opposite the connection to the source of the synchronous rectifier. PowerPAD™ Layout The PowerPAD™ package provides low thermal impedance for heat removal from the device. The PowerPAD™ derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend on the size of the PowerPAD™ package. See PCB Layout Guidelines for further information. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter plus 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD™ Thermally Enhanced Package[2] for more information on the PowerPAD™ package. 18 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 DESIGN EXAMPLES Example 1. A 5-V to 1.8-V DC-to-DC Converter Using a TPS40041 The following example illustrates the design process and component selection for a 5-V to 1.8-V point-of-load synchronous buck converter. The design goal parameters are given in the table below. A list of symbol definitions is found at the end of this section. Design Goal Parameters SYMBOL PARAMETER TEST CONDITION MIN TYP MAX VIN Input voltage VINripple Input ripple IOUT = 6 A 4.5 VOUT Output voltage IOUT = 0 A, VIN = 5 V Line regulation VIN = 4.5 A to 5.5 V 0.5% 0.5% Load regulation IOUT = 0 A to 6 A VRIPPLE Output ripple IOUT = 6 A VTRANS Transient deviation IOUT = 1 A to 5 A, IOUT = 5 A to 1 A IOUT Output current VIN = 4.5 V to 5.5 V FSW Switching frequency 1.764 1.8 UNIT 5.5 V 75 mV 1.836 36 mV 50 0 6 600 Size V A kHz 1 In2 For this example, the schematic shown in Figure 23 is used. The TPS40041, with FSW = 600 kHz, is selected to reduce inductor and capacitor sizes. EN EN Figure 23. TPS40041 Sample Schematic 19 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 Inductor Selection The inductor is typically sized for 30% peak-to-peak ripple current (IRIPPLE) Given this target ripple current, the required inductor size is calculated by: V IN(max) V OUT V L OUT 1 0.3 I OUT V IN(max) F SW (4) Solving with VIN(max) = 5.5 V, an inductor value of 1.12 µH is obtained. A standard value of 1.0 µH is selected, resulting in 2-A peak-peak ripple. The RMS current through the inductor is approximated by the equation: I L(rms) I L(avg) 1 I RIPPLE I OUT 1 I RIPPLE 12 12 (5) Using Equation 5, the maximum RMS current in the inductor is about 6.15 A Output Capacitor Selection (C8 & C9) The selection of the output capacitor is typically driven by the output load transient response requirement. Equation 6 and Equation 7 estimate the output capacitance required for a given output voltage transient deviation. 2 C OUT(min) I TRAN(max) L VIN(min) VOUT VTRAN when V IN(min) 2 VOUT (6) 2 C OUT(min) I TRAN(max) L VOUT VTRAN when V IN(min) 2 V OUT (7) For this example, Equation 6 is used in calculating the minimum output capacitance. Based on a 4-A load transient with a maximum 50-mV deviation, a minimum of 178-µF output of capacitance is required. The output ripple is divided into two components. The first is the ripple voltage generated by inductor ripple current flowing through the output capacitor's capacitance, and the second is the voltage generated by the ripple current flowing in the output capacitor's ESR. The maximum allowable ESR is then determined by the maximum ripple voltage and is approximated by: ESR MAX VRIPPLE(total) VRIPPLE(cap) I RIPPLE V RIPPLE(total) I RIPPLE C OUTF SW I RIPPLE (8) Based on 178 µF of capacitance, 2-A ripple current, 600-kHz switching frequency and a design goal of 36-mV ripple voltage, we calculate a capacitive ripple component of 18.7 mV and a maximum ESR of 8.6 mΩ. Two 1206, 100-µF, 6.3-V, X5R ceramic capacitors are selected to provide significantly less than 8.6 mΩ of ESR. 20 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 Peak Current Rating of Inductor With output capacitance known, it is now possible to calculate the charging current during start-up and determine the minimum saturation current rating for the inductor. The start-up charging current is approximated by: V COUT I CHARGE OUT T SS (9) Using the TPS40041’s fixed 4.5-ms soft-start time, COUT = 200 µF and VOUT = 1.8 V, ICHARGE is found to be 80 mA. The peak current rating of the inductor is now found by: L L(peak) I OUT(max) 1 I RIPPLE I CHARGE 2 (10) The inductor requirements are summarized in the table below. Inductor Requirements PARAMETER SYMBOL VALUE L 1.0 µH IL(rms) 6.15 A IL(peak) 7.08 Inductance RMS current (thermal rating) Peak current (saturation rating) UNITS A PG0083.102, 1.0 µH is selected for its small size, low DCR and high current handling capability. Input Capacitor Selection (C1 & C2) The input voltage ripple is divided between capacitance and ESR. For this design, VRIPPLE(CAP) = 50 mV and VRIPPLE(ESR) = 25 mV. The minimum capacitance and maximum ESR are estimated by: I LOAD VOUT C IN(min) VRIPPLE(cap) VIN F SW (11) ESR MAX VRIPPLE(ESR) I LOAD 1 I RIPPLE 2 (12) For this design, CIN > 120 µF and ESR < 3.5 mΩ. The RMS current in the input capacitors is estimated by: VVOUT VOUTV I OUT I RMS(cin) I IN(rms) I IN(avg) I OUT 1 I RIPPLE 12 IN IN (13) With VIN = VIN(max), the input capacitors must support a ripple current of 1.56 ARMS. Two 1206, 100-µF, X5R ceramic capacitors with about 5-mΩ ESR and a 2-A RMS current rating are selected. It is important to check the dc bias voltage derating curves to ensure the capacitors provide sufficient capacitance at the working voltage. 21 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 MOSFET Switch Selection (Q1 & Q2) The switching losses for the upper switch MOSFET are estimated by: I LOAD VOUT C IN(min) VRIPPLE(cap) VIN F SW (14) For this design, switching losses are higher at low input voltage due to the lower gate drive current. Designing for 1 W of total losses in both MOSFETS and 20% of the total MOSFET losses in switching losses, we can estimate our maximum gate-to-drain charge for the design at: PG1SW V Vt Q GS2_Q1 Q GD_Q1 DD 1 VIN I OUT R DRIVE F SW (15) For a low-gate threshold MOSFET, and the TPS40041’s 5 Ω and 3 Ω drive resistances, we estimate a maximum QGS2+QGD of 10.8 nC. The conduction losses in the upper switch MOSFET are estimated by the RMS current through the MOSFET times its RDS(on): 2 V P CON_Q1 D I OUT 1 I RIPPLE R DS(on) OUT I L(rms) RDS(on_Q1) 12 V IN (16) Estimating about 30% of total MOSFET losses to be high-side conduction losses, the maximum RDS(on) of the high-side MOSFET can be estimated by: P CON_Q1 R DS(on_Q1) V 2 I L(rms) OUT VIN (17) For this design, with IL_RMS = 6 ARMS and 4.5 V to 1.8 V, RDS(on_Q1) is < 19.5 mΩ for the upper switch MOSFET. Estimating 50% of total MOSFET losses are in the SR as conduction losses, repeat equation 14. Then calculate the maximum RDS(on) of the SR by the equation: PCON_Q2 R DS(on_Q2) V 2 I L(rms) 1 OUT V IN (18) For this design IL_RMS = 6 A at 5.5 V to 1.8 V RDS(on_Q2) < 19.6 mΩ. The table below summarizes the MOSFET requirements. MOSFET Requirements PARAMETER High-side FET RDS(on) High-side FET turn-on charge Low-side FET RDS(on) SYMBOL UNITS 19.5 QGS2_Q1 +QGD_Q1 10.8 nC RDS(on_Q2) 19.6 mΩ IRF7910 has an RDSON(max) of 15 mΩ at 4.5-V gate drive,QGD of 6.2 nC, and QGS2 of 2 nC. 22 VALUE RDS(on_Q1) mΩ TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 Bootstrap Capacitor (C7) To ensure proper charging of the upper switch MOSFET gate, limit the ripple voltage on the bootstrap capacitor to < 5% of the minimum gate drive voltage of 3.0 V. 20 Q GS_Q1 C BOOST V IN(min) (19) Based on the IRF7910 MOSFET with a maximum total gate charge of 26 nC, calculate a minimum of 116 nF of capacitance. The next higher standard value of 220 nF is selected. VDD Bypass Capacitor (C6) Select a 1.0-µF ceramic bypass capacitor for VDD. VDD Filter Resistor (R7) An optional resistor in series with VDD helps filter switching noise from the device. Driving the two IRF7910 MOSFETs, with a typical total QG of 17 nC each, we calculate a maximum IDD current of 22 mA. The result of equation 19, leads to selecting a 1-Ω resistor, and limits the voltage drop across this resistor to less than 25 mV. VRVDD(max) 25 mV R VDD I DD 2 mA Q G_Q1 Q G_Q2F SW (20) Short Circuit Protection (R2) The TPS40040/1 use the forward drop across the upper switch MOSFET during the ON time to measure the inductor current. The voltage drop across the high-side MOSFET is given by: 20 Q GS_Q1 C BOOST V IN(min) (21) When VIN = 4.5 V to 5.5 V, IL_PEAK = 7.2A. Using the IRF7910 MOSFET, we calculate the peak voltage drop to be 108 mV. The TPS40041’s internal 3100-ppm temperature coefficient helps compensate for the MOSFET’s RDS(on) temperature coefficient. For this design, select the short circuit protection voltage threshold of 180 mV by selecting R2 = OPEN. 23 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 Feedback Loop Design To design feedback circuit, a small signal average modeling technique is employed. Further information on this technique may be found in the references. Modeling the Power Stage The peak-to-peak ramp voltage given in the Electrical Specification table allows the modulator gain to be calculated as: V IN A MOD VRAMP(pp) (22) For this design, a modulator gain of 7.3 (17.3 dB) is calculated. The LC filter applies a double pole at the resonance frequency: 1 F RES 2 L C (23) For this design, the resonance frequency is about 11.3 kHz. Below this frequency, the power stage has the dc gain of 17.3 dB and above this frequency the power stage gain drops off at -40 dB per decade. The ESR zero is approximated by: 1 F ESR 2 COUT RESR (24) For COUT = 2 x 100 µF and RESR = 2.5 mΩ FESR = 318 kHz. This is greater than 1/5th the switching frequency and outside the scope of the error amplifier design. The gain of the power stage would change to -20 dB per decade above FESR. The straight line approximation the power stage gain is approximated in Figure 24. FRES AMOD −40dB/dec 0dB −20dB/dec FESR Frequency (Log Scale) Figure 24. Power Stage Frequency Response Straight Line Approximation Feedback Divider (R4, R5 & R8) Select R8 be between 10 kΩ and 100 kΩ. For this design, select 20 kΩ. Next, R5 is selected to produce the desired output voltage when VFB = 0.600 V using the following formula. V FB R8 R5 in paralell with R4 V OUT V FB (25) VFB = 0.600 V and R8 = 20 kΩ for VOUT = 1.8 V, R5 = 10 kΩ. If the calculated value is not a standard resistor, select a slightly higher resistor value and add R4 in parallel to reduce the parallel combination of R4 and R5 to produce desired output voltage. 24 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 Error Amplifier Pole-Zero Selection Place two zeros at 80% and 125% of the resonance frequency to keep the actual resonance frequency between the two zeros over the L and C tolerance. For FRES = 11.3 kHz, FZ1 = 9.0 kHz and FZ2 = 14 kHz. Selecting the cross-over frequency (FCO) of the control loop between 3 times the LC filter resonance and 1/5th the switching frequency. For most applications 1/10th the switching frequency provides a good balance between ease of design and fast transient response. If FESR < FCO; FP1 = ½ FCO and FP2 = 2x FCO. If FESR > 2x FCO; FP1 = FCO and FP2 = 4x FCO. For this design with FSW = 600 kHz, FRES = 11.3 kHz and FESR = 318 kHz. FCO = 60 kHz and since FESR > 2x FCO, FP1 = FCO and FP2 = 4x FCO. Since FCO < FESR the power stage gain at the desired cross-over can be approximated by: F CO A PS(fcc) AMOD 40 LOG F RES (11.7/20) APS(FCO) = -11.7 dB, so the error amplifier gain between the two poles should be 10 (26) = 3.84. If the error amplifier gain is greater than 0 dB at FSW, the converter can achieve a stable bi-modal operation with duty cycles alternating between two stable values, and the output regulated with a output ripple component at ½ FSW. To prevent this effect, check FP2 by the equation: F SW F P2(max) AMID(band) (27) Since FP2 > FP2(max), it is possible for this control loop to obtain bi-modal operation. To prevent this bi-modal operation, reduce FCO and re-calculate APC(FCO), FP1, and FP2(max). Now, FCO = 50 kHz, AMID-BAND = 2.67, FP1 = 50 kHz and FP2 = 200 kHz. The table below summarizes the error amplifier compensation network design criteria. Error Amplifier Compensation Network PARAMETER First zero frequency SYMBOL VALUE UNITS FZ1 9 Second zero frequency FZ2 14 First pole frequency FP1 50 Second pole frequency FP2 200 AMID-BAND 2.67 Mid-band gain kHz V/V 25 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 Feedback Components (R3, R6, C3, C4, C5) Approximate C5 with the formula: 1 C5 2 R8 F Z2 (28) C5 = 560 pF (closest standard capacitor value to calculated 568 pF) and approximate R6 with the formula: 1 R6 2 C5 F P1 (29) R6 = 4.75 kΩ (closest standard resistor value to calculated 4.74 kΩ) Calculate R3 by the formulae: A MID(band) (R6 R8) R3 R6 R8 (30) With AMID_BAND = 3.84, R6 = 4.75 kΩ and R8 = 20 kΩ, R3 = 14.7 kΩ (closest standard resistor value to calculated 14.7 kΩ) Calculate C3 and C4 by the equations: 1 C4 2 R3 F Z1 (31) C3 1 2 R3 F P2 (32) For R3 = 14.7 kΩ, C3 = 47 pF (closest standard value to 45 pF) C4 = 1200 pF (closest standard value to 1.2 nF) Error Amplifier straight line approximation transfer function looks like Figure 25. F P1 FP2 A mid−Band 0dB FZ1 FZ2 FSW Frequency (Log Scale) Figure 25. Error Amplifier Frequency Response Straight Line Approximation 26 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 100% η − Efficiency − % 90% 80% 4.5 5 5.5 70% 60% 50% 0 1 2 4 3 6 5 7 IOUT − Load Current − A Figure 26. Typical Efficency for 5-V to 1.8-V at 6-A Converter Using TPS40041 1.818 VOUT − Output Voltage − V 1.816 1.814 4.5 1.812 5 5.5 1.810 1.808 1.806 1.804 1.802 1.800 0 1 2 3 4 5 6 7 IOUT − Load Current − A Figure 27. Typical Line/Load Regulation for 5-V to 1.8-V at 6-A Converter Using TPS40041 27 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 List of Materials REF QTY C1 1 Capacitor, ceramic, 6.3 V, X5R, 20%, 100 µF, 1210 TDK C325X5R0J107M C2 1 Capacitor, ceramic, 6.3 V, X5R, 20%, 100 µF, 1210 TDK C3225X5R0J107M C3 1 Capacitor, ceramic, 50 V, X7R, 20%, 270pF, 0402 TDK C1005C01H271M C4 1 Capacitor, ceramic, 50 V, X7R, 20%, 1500 pF, 0402 TDK C1005X7R1H152M C5 1 Capacitor, ceramic, 50 V, X7R, 20%, 560 pF, 0402 TDK C1005X7R1H561M C6 1 Capacitor, ceramic, 6.3 V, X5R, 20%, 1.0 µF, 0402 TDK C1005X7R0J105M C7 1 Capacitor, ceramic, 6.3 V, X5R, 20%, 0.22 µF, 0402 TDK C1005X7R0J224M C8 1 Capacitor, ceramic, 6.3 V, X5R, 20%, 100 µF, 1210 TDK C3225X5R0J107M C9 1 Capacitor, ceramic, 6.3 V, X5R, 20%, 100 µF, 1210 TDK C3225X5R0J107M L1 1 Inductor, SMT, 1.0 µH, 12 A, 6.6 mΩ, ED1514, 0.268 x 0.268 Pulse PG0083.102 Q2 1 MOSFET, dual N-channel, 20 V, 6.6 A, 29 mΩ, 1.0 µH, SO8 IR IRF7311 R2 1 Resistor, chip, 1/16 W, %, IRF7910, 0402 Std Std R3 1 Resistor, chip, 1/16 W, 1%, OPEN, 0402 Std Std R4 1 Resistor, chip, 1/16 W, 1%, 11.8 kΩ, 0402 Std Std R5 1 Resistor, chip, 1/16 W, 1%, OPEN, 0402 Std Std R6 1 Resistor, chip, k 1/1 W, 1%, 10.0 kΩ, 0402 Std Std R7 1 Resistor, chip, k, 1/16 W, 1%, 5.62 kΩ, 0402 Std Std R8 1 Resistor, chip, k 1/16 W, 1%, 20 kΩ, 0402 Std Std 1 Device, Low Voltage DC to DC Synchronous Buck Controller, TPS40041DRB, SON-8P TPS40041DRB TI Std Std 2N7002W-7 Diodes Inc U1 DESCRIPTION MFR PART NUMBER Active High Enable Circuit R1 Q1 28 1 Resistor, chip, 100 kΩ, 1/16 W, 1%, 100 kΩ, 0402 1 Mosfet, N-channel, VDS 60 V, RDS 2 Ω, ID 115 mA, 2N7002W, SOT-323 (SC-70) TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 Definition of Symbols SYMBOL DESCRIPTION VIN(max) Maximum operating input voltage VIN(min) Minimum operating input voltage VINRIPPLE Peak-to-peak ac ripple voltage on VIN VOUT Target output voltage VOUTRIPPLE Peak-to-peak ac ripple voltage on VOUT IOUT(max) Maximum operating load current IRIPPLE Peak-to-peak ripple current through the output filter inductor IL_PEAK Peak ripple current through the output filter inductor IL_RMS Root mean squared current through the output filter inductor IRMS_CIN Root mean squared current in input capacitor FSW Switching frequency FCO Desired control loop cross-over frequency AMOD Low frequency gain of the pulse width modulator VCONTROL PWM control voltage (error amplifier output voltage - VCOMP) FRES L-C filter resonant frequency FESR Output capacitors’ ESR zero frequency FP1 First pole frequency in error amplifier compensation FP2 Second pole frequency in error amplifier compensation FZ1 First zero frequency in error amplifier compensation FZ2 Second pole frequency in error amplifier compensation QG1_Q1 Total gate charge of upper switch MOSFET QG2_Q2 Total gate charge of synchronous rectifier MOSFET RDS(on_Q1) “ON” drain-to-source resistance of upper switch MOSFET RDS(on_Q2) “ON” drain-to-source resistance of synchronous rectifier MOSEFT PCON_Q1 Conduction losses in upper switch MOSFET PSW_Q1 Switching losses in upper switch MOSFET PCON_Q2 Conduction losses in synchronous rectifier MOSFET QGD_Q1 Gate-to-drain charge of upper switch MOSFET QGS2_Q1 Post threshold gate-to-source charge of the upper switch MOSFET. (Estimate from QG vs. VGS if not provided in MOSFET data sheet) VFB Internal reference voltage as measured on FB pin. VRAMP_slope Slope of internal PWM ramp APS(Fco) VCOMP to VOUT gain at desired loop cross-over frequency. (dB) AMID-BAND VOUT to VCOMP gain at desired loop cross-over frequency (V/V) 29 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 Example 2. A 2.5-V to 1.2-V DC-to-DC Converter Using a TPS40041 This example illustrates a 2.5-V to 1.2-V at 3-A synchronous buck application using the TPS40041. A diode has been added to increase the bootstrap capacitor charging current at low input voltage. The highest current limit threshold has been selected due to the increased RDS(on) at low input voltages. Figure 28. Schematic for 2.5-V to 1.2-V at 3-A Converter Using the TPS40041 1.210 100% 1.208 80% 2.25 2.5 VOUT − Output Voltage − V η − Efficiency − % 90% 2.75 70% 60% 2.5 2.75 2.0 2.5 3.0 1.206 1.204 1.202 1.200 50% 1.198 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 IOUT − Load Current − A Figure 29. Typical Efficency for 2.5-V to 1.2-V at 3-A Converter Using TPS40041 30 2.25 0.0 0.5 1.0 1.5 3.5 IOUT − Load Current − A Figure 30. Typical Line/Load Regulation for 2.5-V to 1.2-V at 3-A Converter Using TPS40041 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 Example 3. A 3.3-V to 1.2-V DC-to-DC Converter Using a TPS40040 This example illustrates a 3.3-V to 1.2-V at 10-A synchronous BUCK application using the TPS40040 switching at 300 kHz. Separate SO-8 MOSFETs have been chosen to support the higher currents in this application and a resistor has been added in series with the BOOT pin to slow the rising edge of the switch node and reduce EMI on the input of the converter. Figure 31. Schematic for 3.3-V to 1.2-V at 10-A Converter Using the TPS40040 100 1.217 3.3 1.212 3 80 3.3 VOUT − Output Voltage − V η − Efficiency − % 90 3.6 70 60 3 3.6 1.207 1.202 1.197 1.192 1.187 1.182 0 50 0 2 4 6 8 IOUT − Load Current − A 10 12 Figure 32. Typical Efficiency for 3.3-V to 1.2-V at 10-A Converter Using TPS40040 2 4 6 8 10 IOUT − Load Current − A 12 Figure 33. Typicaly Line and Load Regulation for 3.3-V to 1.2-V at 10-A Converter Using TPS40040 31 TPS40040, TPS40041 www.ti.com SLUS700B – MARCH 2006 – REVISED MARCH 2006 ADDITIONAL REFERENCES Related Parts The following parts have characteristics similar to the TPS40040/1 and may be of interest. Related Parts DEVICE TPS40007/9 DESCRIPTION Low Voltage Synchronous Buck Controller with Predictive Gate Drive® TPS40021 Full Featured Low Voltage Synchronous Buck Controller with Predictive GateTM Drive TPS40190 Cost Optimized Mid Voltage Synchronous Buck Controller References These references may be found on the web at www.power.ti.com under Technical Documents. Many design tools and links to additional references, including design software, may also be found at www.power.ti.com 1. Under The Hood Of Low Voltage DC/DC Converters, SEM1500 Topic 5, 2002 Seminar Series 2. Understanding Buck Power Stages in Switchmode Power Supplies, SLVA057, March 1999 3. Design and Application Guide for High Speed MOSFET Gate Drive Circuits, SEM 1400, 2001 Seminar Series 4. Designing Stable Control Loops, SEM 1400, 2001 Seminar Series 5. Additional PowerPADTM information may be found in Applications Briefs SLMA002 and SLMA004 6. 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