MICREL SY100E446JC

4-BIT PARALLEL-TO-SERIAL
CONVERTER
Micrel, Inc.
SY100E446
DESCRIPTION
FEATURES
■ On-chip clock ÷4 and ÷8
■ Extended 100E VEE range of –4.2V to –5.5V
■
■
■
■
■
■
■
■
SY10E446
SY100E446
SY10E446
The SY10/100E446 are integrated 4-bit parallel-toserial data converters. These devices are designed to
operate for NRZ data rates of up to a minimum of 1.3Gb/
s. The chips generate a divide-by-4 and a divide-by-8
clock for both 4-bit conversion and a two-chip 8-bit
conversion function. The conversion sequence was
chosen to convert the parallel data into a serial stream
from bit D0 to D3. A serial input is provided to cascade
two E446 devices for 8-bit conversion applications.
The SYNC input will asynchronously reset the internal
clock circuitry. This pin allows the user to reset the internal
clock conversion unit and, thus, select the start of the
conversion process.
The MODE input is used to select the conversion mode
of the device. With the MODE input LOW (or open) the
device will function as a 4-bit converter. When the mode
input is driven HIGH, the internal load clock will change
on every eighth clock cycle, thus allowing for an 8-bit
conversion scheme using two E446s. When cascaded in
an 8-bit conversion scheme, the devices will not operate
at the 1.3Gb/s data rate of a single device. Refer to the
applications section of this data sheet for more information
on cascading the E446.
For lower data rate applications, a V BB reference
voltage is supplied for single-ended inputs. When
operating at clock rates above 500MHz, differential input
signals are recommended. For single-ended inputs, the
VBB pin is tied to the inverting differential input and
bypassed via a 0.01µF capacitor. The VBB provides the
switching reference for the input differential amplifier. The
VBB can also be used to AC couple an input signal.
1.6Gb/s typical data rate capability
Differential clock and serial inputs
VBB output for single-ended use
Asynchronous data synchronization
Mode select to expand to 8 bits
Internal 75KΩ input pulldown resistors
Fully compatible with Motorola MC10E/100E446
Available in 28-pin PLCC package
PIN NAMES
Pin
Function
SIN, SIN
Differential Serial Data Input
D0 – D3
Parallel Data Input
SOUT, SOUT
Differential Serial Data Output
CLK, CLK
Differential Clock Input
CL/4, CL/4
Differential 4 Clock Output
CL/8, CL/8
Differential 8 Clock Output
MODE
Conversion Mode, 4-bit/8-bit
SYNC
Conversion Synchronizing Input
VCCO
VCC to Output
M9999-032206
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Rev.: F
Amendment: /0
Issue Date: March 2006
SY10E446
SY100E446
Micrel, Inc.
Ordering Information(1)
NC
MODE
NC
D2
D3
D0
D1
PACKAGE/ORDERING INFORMATION
25 24 23 22 21 20 19
CLK
CLK
26
18
NC
27
17
VBB
VEE
SIN
28
16
NC
VCC
15
SOUT
14
13
4
12
NC
7
8
9
10 11
VCCO
6
VCCO
CL/8
5
CL/8
3
SOUT
VCCO
2
VCCO
CL/4
CL/4
SIN
SYNC
TOP VIEW
PLCC
J28-1
1
28-Pin PLCC (J28-1)
Part Number
Package
Type
Operating
Range
Package
Marking
Lead
Finish
SY10E446JC
J28-1
Commercial
SY10E446JC
Sn-Pb
SY10E446JCTR(2)
J28-1
Commercial
SY10E446JC
Sn-Pb
SY100E446JC
J28-1
Commercial
SY100E446JC
Sn-Pb
SY100E446JCTR(2)
J28-1
Commercial
SY100E446JC
Sn-Pb
SY10E446JZ(3)
J28-1
Commercial
SY10E446JZ with
Pb-Free bar-line indicator
Matte-Sn
Pb-Free
SY10E446JZTR(2, 3)
J28-1
Commercial
SY10E446JZ with
Pb-Free bar-line indicator
Matte-Sn
Pb-Free
SY100E446JZ(3)
J28-1
Commercial
SY100E446JZ with
Pb-Free bar-line indicator
Matte-Sn
Pb-Free
SY100E446JZTR(2, 3)
J28-1
Commercial
SY100E446JZ with
Pb-Free bar-line indicator
Matte-Sn
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
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SY10E446
SY100E446
Micrel, Inc.
BLOCK DIAGRAM
SIN
SIN
D3
0
D
Q
1
CLK
0
D
D2
Q
1
CLK
0
D
D1
Q
1
CLK
0
SOUT
D
D0
Q
SOUT
1
CLK
CL/8
MODE
0
1
CL/8
CLK
CLK
DELAY
÷4
÷8
R
R
CL/4
CL/4
SYNC
VBB
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SY10E446
SY100E446
Micrel, Inc.
TRUTH TABLE
Mode
Conversion
L
4-Bit
H
8-Bit
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
Symbol
Parameter
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Condition
—
—
150
—
—
150
—
—
150
µA
—
Output HIGH Voltage
(SOUT Only) 10E –1020
(SOUT Only) 100E –1025
V
1
—
—
–790 –980
–830 –1025
—
—
–760 –910
–830 –1025
—
—
–670
–830
Output Reference Voltage
10E
100E
V
—
–1.38
–1.38
—
—
–1.27 –1.35
–1.26 –1.38
—
—
–1.25 –1.31
–1.26 –1.38
—
—
–1.19
–1.26
mA
—
—
—
110
110
110
127
132
152
Input HIGH Current
VOH
IEE
TA = +85°C
Min.
IIH
VBB
TA = +25°C
Power Supply Current
10E
100E
132
132
—
—
110
110
132
132
—
—
Note:
1. The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard 10E
and 100E VOH levels.
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
Symbol
TA = +25°C
Parameter
Min.
Typ.
fMAX
Max. Conversion Frequency
1.3
1.6
tPD
Propagation Delay to Output
CLK to SOUT
1000
CLK to CL/4
500
CLK to CL/8
800
SYNC to CL/4, CL/8
500
1400
800
1100
800
Set-up Time
SIN
Dn
Mode
–200
–200
0
–400
–400
–250
—
—
—
Hold Time
SIN
Dn
Mode
750
800
500
550
600
300
tRR
Reset Recovery Time
500
tPW
Minimum Pulse Width
CLK, MR
tr
tf
Rise/Fall Time
SOUT
Other
tS
tH
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Max. Min.
TA = +85°C
Typ.
Max.
Min.
Typ.
Max.
Unit
Condition
1.6
—
1.3
1.6
—
Gb/s
NRZ
—
ps
—
1400
800
1100
800
1700
1100
1400
1100
1000
500
800
500
1400
800
1100
800
1700
1100
1400
1100
ps
—
–200
–200
0
–400
–400
–250
—
—
—
–200
–200
0
–400
–400
–250
—
—
—
ps
—
—
—
—
750
800
500
550
600
300
—
—
—
750
800
500
550
600
300
—
—
—
200
—
500
200
—
500
200
—
ps
—
400
—
—
400
—
—
400
—
—
ps
—
ps
20–80%
100
200
225
425
350
650
100
200
225
425
350
650
100
200
225
425
350
650
—
1.3
1700 1000
1100 500
1400 800
1100 500
4
SY10E446
SY100E446
Micrel, Inc.
TIMING DIAGRAMS
CLK
RESET
D0
D0–1
D1
D1–1
D2
D2–1
D3
D3–1
SOUT
CL/4
CL/8
Timing Diagram A. 4:1 Parallel-to-Serial Conversion
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SY10E446
SY100E446
Micrel, Inc.
TIMING DIAGRAMS (CONTINUED)
CLK
RESET
D0
D0–1
D1
D1–1
D2
D2–1
D3
D3–1
D4(D0B)
D4–1
D5(D1B)
D5–1
D6(D2B)
D6–1
D7(D3B)
D7–1
SOUT
Timing Diagram B. 8:1 Parallel-to-Serial Conversion
M9999-032206
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SY10E446
SY100E446
Micrel, Inc.
APPLICATIONS INFORMATION
The SY10E/100E446 are integrated 4:1 parallel-to-serial
converters. The chips are designed to work with the E445
device to provide both transmission and receiving of a highspeed serial data path. The E446 can convert 4 bits of
data into a 1.3Gb/s NRZ data stream. The device features
a SYNC input which allows the user to reset the internal
clock circuitry and restart the conversion sequence (see
Timing Diagram A). Note that SOUT is triggered by negative
clock edges.
The E446 features a differential serial input and internal
divide-by-eight circuitry to facilitate the cascading of two
devices to build an 8:1 multiplexer. Figure 1 illustrates the
architecture for an 8:1 multiplexer using two E446s (see
Timing Diagram B). Notice the serial outputs (SOUT) of the
lower order converter feed the serial inputs of the higher
order device. This feed through of the serial inputs bounds
the upper end of the frequency of operation. The clock-toserial output propagation delay, plus the set-up time of the
serial input pins, must fit into a single clock period for the
cascade architecture to function properly. Using the worst
case values for these two parameters from the data sheet,
tPD CLK to SOUT = 1600ps and ts for SIN = –200ps, yields
a minimum period of 1400ps or a clock frequency of
700MHz.
The clock frequency is somewhat lower than that of a
single converter. In order to increase this frequency, it is
recommended that the clock edge feeding the E446A be
delayed with respect to the E446B, as shown in Figure 2.
Perhaps the easiest way to delay the second clock relative
to the first is to take advantage of the differential clock
inputs of the E446. By connecting the clock for E446A to
the complimentary clock input pin, the device will clock a
half a clock period after E446B (Figure 2). Utilizing this
simple technique will raise the potential conversion frequency
up to the maximum 1.3GHz of a stand-alone E446.
CLK
CLK
E446B
E446A
SOUT
SIN
SOUT
SOUT
SIN
SOUT
D3 D2 D1 D0
D3 D2 D1 D0
D7 D6 D5 D4
D3 D2 D1 D0
PARALLEL DATA
1400ps
CLK
tPD
CLK to SOUT
1600ps
Figure 1. Cascaded 8:1 Converter Architecture
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200ps
SERIAL
DATA
SY10E446
SY100E446
Micrel, Inc.
APPLICATIONS INFORMATION
CLK
CLK
E446B
E446A
SOUT
SIN
SOUT
SOUT
SIN
SOUT
D3 D2 D1 D0
D3 D2 D1 D0
D7 D6 D5 D4
D3 D2 D1 D0
PARALLEL DATA
1.3GHz
770ps
CLKB
CLKA
tPD
CLK to SOUT
Figure 2. Extended Frequency 8:1 Converter Architecture
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SERIAL
DATA
SY10E446
SY100E446
Micrel, Inc.
28-PIN PLCC (J28-1)
Rev. 03
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
USA
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
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