SEMICONDUCTOR TECHNICAL DATA The MC10E/100E136 is a 6-bit synchronous, presettable, cascadable universal counter. The device generates a look-ahead-carry output and accepts a look-ahead-carry input. These two features allow for the cacading of multiple E136’s for wider bit width counters that operate at very nearly the same frequency as the stand alone counter. • • • • • • 550 MHz Count Frequency 6-BIT UNIVERSAL UP/DOWN COUNTER Fully Synchronous Up and Down Counting Internal 75 kΩ Input Pulldown Resistors Look-Ahead-Carry Input and Output Asynchronous Master Reset Extended 100E VEE Range of –4.2 V to –5.46 V The CLOUT output will pulse LOW for one clock cycle one count before the E136 reaches terminal count. The COUT output will pulse LOW for one clock cycle when the counter reaches terminal count. For more information on utilizing the look-ahead-carry features of the device please refer to the applications section of this data sheet. The differential COUT output facilitates the E136’s use in programmable divider and self-stopping counter applications. FN SUFFIX PLASTIC PACKAGE CASE 776-02 Unlike the H136 and other similar universal counter designs the E136 carry out and look-ahead-carry out signals are registered on chip. This design alleviates the glitch problem seen on many counters where the carry out signals are merely gated. Because of this architecture there are some minor functional differences between the E136 and H136 counters. The user, regardless of familiarity with the H136, should read this data sheet carefully. Note specifically (see logic diagram) the operation of the carry out outputs and the look-ahead-carry in input when utilizing the master reset. When left open all of the input pins will be pulled LOW via an input pulldown resistor. The master reset is an asynchronous signal which when asserted will force the Q outputs LOW. The Q outputs need not be terminated for the E136 to function properly, in fact if these outputs will not be used in a system it is recommended to save power and minimize noise that they be left open. This practice will minimize switching noise which can reduce the maximum count frequency of the device or significantly reduce margins against other noise in the system. PIN NAMES Pin Function D0 – D5 Q0 – Q5 S1, S2 MR CLK COUT, COUT CLOUT CIN CLIN Preset Data Inputs Data Inputs Mode Control Pins Master Reset Clock Input Carry-Out Output (Active LOW) Look-Ahead-Carry Out (Active LOW) Carry-In Input (Active LOW) Look-Ahead-Carry In Input (Active LOW) FUNCTION TABLE (Expanded truth table on page 2–4) S1 S2 CIN MR CLK Function L L L H H H X L H H L L H X X L H L H X X L L L L L L H Z Z Z Z Z Z X Preset Parallel Data Increment (Count Up) Hold Count Decrement (Count Down) Hold Count Hold Count Reset (Qn = LOW) D3 D4 D5 VCCO Q5 Q4 VCCO 25 24 23 22 21 20 19 D2 26 18 Q3 S2 27 17 Q2 S1 28 16 VCC 15 VCCO Pinout: 28-lead PLCC (Top View) VEE 1 CLK 2 14 COUT CIN 3 13 COUT CLIN 4 12 CLOUT 5 6 2–1 8 9 10 11 D1 MR D0 VCCO Q0 Q1 VCCO * All VCC and VCCO pins are tied together on the die. 5/95 Motorola, Inc. 1996 7 REV 2 MOTOROLA MR CLK CLIN CIN S1 S2 2–2 D0 D Q RQ Q0 D1 D Q RQ Q1 D2 – D4 Bits 2 – 4 Q2 – Q4 D5 D Q RQ Q5 QM0 QM1 S D Q D Q SQ Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay. S D Q QM0 CLOUT COUT COUT MC10E136 MC100E136 E136 Universal Up/Down Counter Logic Diagram ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E136 MC100E136 DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) 0°C Characteristic 25°C 85°C Symbol Min Typ Max Min Typ Max Min Typ Max Unit Input HIGH Current IIH — — 150 — — 150 — — 150 µA Power Supply Current 10E 100E IEE — — 125 125 150 150 — — 125 125 150 150 — — 125 140 150 170 AC CHARACTERISTICS mA (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) 0°C Characteristic 25°C 85°C Symbol Min Typ Max Min Typ Max Min Typ Max Unit Maximum Count Frequency fCOUNT 550 650 — 550 650 — 550 650 — MHz Propagation Delay to Output CLK to Q MR to Q CLK to COUT CLK to CLOUT tPLH tPHL 850 850 800 825 1150 1150 1150 1150 1450 1450 1300 1400 850 850 800 825 1150 1150 1150 1150 1450 1450 1300 1400 850 850 800 825 1150 1150 1150 1150 1450 1450 1300 1400 1000 800 150 800 650 400 0 400 — — — — 1000 800 150 800 650 400 0 400 — — — — 1000 800 150 800 650 400 0 400 — — — — 150 150 300 150 –200 –250 0 –250 — — — — 150 150 300 150 –200 –250 0 –250 — — — — 150 150 300 150 –200 –250 0 –250 — — — — 1000 700 — 1000 700 — 1000 700 — 700 400 — 700 400 — 700 400 — 275 300 — — 600 700 275 300 — — 600 700 275 300 — — 600 700 Setup Time S1, S2 D CLIN CIN ts Hold Time S1, S2 D CLIN CIN th Reset Recovery Time tRR Minimum Pulse Width CLK, MR tPW Rise/Fall Times COUT Other ECLinPS and ECLinPS Lite DL140 — Rev 4 Condition tr tf Condition ps ps ps ps ps ps 2–3 20% - 80% MOTOROLA MC10E136 MC100E136 EXPANDED TRUTH TABLE Function S1 S2 MR CIN CLIN CLK D5 D4 D3 D2 D1 D0 Q5 Q4 Q3 Q2 Q1 Q0 COUT CLOUT Preset L L L X X Z L L L L H H L L L L H H H H Down H H H H L L L L L L L L L L L L L L L L Z Z Z Z X X X X X X X X X X X X X X X X X X X X X X X X L L L H L L L H L L L H L L L H H L L H L H L H H H L H H L H H Preset L L L X X Z H H H H L L H H H H L L H H Up L L L L L L H H H H H H L L L L L L L L L L L L L L L L L L Z Z Z Z Z Z X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X H H H L L L H H H L L L H H H L L L H H H L L L L H H L L H H L H L H L H H L H H H H L H H H H Hold H H H H L L X X X X Z Z X X X X X X X X X X X X L L L L L L L L H H L L H H H H Down Hold Down Hold H H H H H H H H L L L L L L L L L L L L L L L L L H L H H H L L L L L L L H H L Z Z Z Z Z Z Z Z X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L H H L L L L L L H H L H H H L L L H H H H H H H H L L L L L L L L H L H H H H H H H L L L L L L L L L L X L L H L H H L L X L L L L L H L Z Z Z Z Z Z Z Z Z X H X X X X X X X X H X X X X X X X X H X X X X X X X X H X X X X X X X X L X X X X X X X X L X X X X X X X L H H H H H H H H L H H H H H H H H L H H H H H H H H L H H H H H H H H L L L H H H H H H L L H L L H H H H L H H H H L H H L H H H L H H H H H Up L L L L H H H H L L L L L L L L L L L L Z Z Z Z X X X X X X X X X X X X X X X X X X X X X X X X L L L L L L L L L L L L L L L L L L H H L H L H H H H H H H H H Reset X X H X X X X X X X X X L L L L L L H H Hold Hold Preset Up Hold Up Hold Hold Z = Low to High Transition MOTOROLA 2–4 ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E136 MC100E136 APPLICATIONS INFORMATION result of the terminal count signal of the lower order counters having to ripple through the entire counter chain. As a result past counters of this type were not widely used in large bit counter applications. Overview The MC10E/100E136 is a 6-bit synchronous, presettable, cascadable universal counter. Using the S1 and S2 control pins the user can select between preset, count up, count down and hold count. The master reset pin will reset the internal counter, and set the COUT, CLOUT, and CLIN flip-flops. Unlike previous 136 type counters the carry out outputs will go to a high state during the preset operation. In addition since the carry out outputs are registered they will not go low if terminal count is loaded into the register. The look-ahead-carry out output functions similarly. An alternative counter architecture similar to the E016 binary counter was implemented to alleviate the need to ripple propagate the terminal count signal. Unfortunately these types of counters require external gating for cascading designs of more than two devices. In addition to requiring additional components, these external gates limit the cascaded count frequency to a value less than the free running count frequency of a single counter. Although there is a performance impact with this type of architecture it is minor compared to the impact of the ripple propagate designs. As a result the E016 type counters have been used extensively in applications requiring very high speed, wide bit width synchronous counters. Note from the schematic the use of the master information from the least significant bits for control of the two carry out functions. This architecture not only reduces the carry out delay, but is essential to incorporate the registered carry out functions. In addition to being faster, because these functions are registered the resulting carry out signals are stable and glitch free. Motorola has incorporated several improvements to past universal counter designs in the E136 universal counter. These enhancements make the E136 the unparalleled leader in its class. With the addition of look-ahead-carry features on the terminal count signal, very large counter chains can be designed which function at very nearly the same clock frequency as a single free running device. More importantly these counter chains require no external gating. Figure 1 below illustrates the interconnect scheme for using the look-ahead-carry features of the E136 counter. Cascading Multiple E136 Devices Many applications require counters significantly larger than the 6 bits available with the E136. For these applications several E136 devices can be cascaded to increase the bit width of the counter to meet the needs of the application. In the past cascading several 136 type universal counters necessarily impacted the maximum count frequency of the resulting counter chain. This performance impact was the Q0 –> Q5 CLOCK Q0 –> Q5 CLK Q0 –> Q5 Q0 –> Q5 CLK CLK CLK LSB MSB “LO” CIN COUT “LO” CLIN CLOUT “LO” CIN COUT CIN COUT CIN COUT CLIN CLOUT CLIN CLOUT CLIN CLOUT D0 –> D5 111101 D0 –> D5 111110 D0 –> D5 111111 000000 D0 –> D5 000001 CLK CLOUT COUT Figure 1. 24-bit Cascaded E136 Counter ECLinPS and ECLinPS Lite DL140 — Rev 4 2–5 MOTOROLA MC10E136 MC100E136 CIN During the clock pulse in which the higher order counter is counting by one the CLIN is clocking in the high signal presented by the CLOUT of the LSC. The CIN’s in the higher order counter will ripple propagate through the chain to update the count status for the next occurrence of terminal count on the LSC. This ripple propagation will not affect the count frequency as it has 26–1 or 63 clock pulses to ripple through without affecting the count operation of the chain. ACTIVE LOW CLIN D Q CLK The only limiting factor which could reduce the count frequency of the chain as compared to a free running single device will be the setup time of the CLIN input. This limit will consist of the CLK to CLOUT delay of the E136 plus the CLIN setup time plus any path length differences between the CLOUT output and the clock. Figure 2. Look-Ahead-Carry Input Structure Note from the waveforms that the look-ahead-carry output (CLOUT) pulses low one clock pulse before the counter reaches terminal count. Also note that both CLOUT and the carry out pin (COUT) of the device pulse low for only one clock period. The input structure for look-ahead-carry in (CLIN) and carry in (CIN) is pictured in Figure 2. The CLIN input is registered and then ORed with the CIN input. From the truth table one can see that both the CIN and the CLIN inputs must be in a LOW state for the E136 to be enabled to count (either count up or count down). The CLIN inputs are driven by the CLOUT output of the lowest order E136 and therefore are only asserted for a single clock period. Since the CLIN input is registered it must be asserted one clock period prior to the CIN input. If the counter previous to a given counter is at terminal count its COUT output and thus the CIN input of the given counter will be in the “LOW” state. This signals the given counter that it will need to count one upon the next terminal count of the least significant counter (LSC). The CLOUT output of the LSC will pulse low one clock period before it reaches terminal count. This CLOUT signal will be clocked into the CLIN input of the higher order counters on the following positive clock transition. Since both CIN and CLIN are in the LOW state the next clock pulse will cause the least significant counter to roll over and all higher order counters, if signaled by their CIN inputs, to count by one. Programmable Divider Using external feedback of the COUT pin, the E136 can be configured as a programmable divider. Figure 3 illustrates the configuration for a 6-bit count down programmable divider. If for some reason a count up divider is preferred the COUT signal is simply fed back to S2 rather than S1. Examination of the truth table for the E136 shows that when both S1 and S2 are LOW the counter will parallel load on the next positive transition of the clock. If the S2 input is low and the S1 input is high the counter will be in the count down mode and will count towards an all zero state upon successive clock pulses. Knowing this and the operation of the COUT output it becomes a trivial matter to build programmable dividers. For a programmable divider one wants to load a predesignated number into the counter and count to terminal count. Upon terminal count the counter should automatically reload the divide number. With the architecture shown in Figure 3 when the counter reaches terminal count the COUT output and thus the S1 input will go LOW, this combined with the low on S2 will cause the counter to load the inputs present on D0-D5. Upon loading the divide value into the counter COUT will go HIGH as the counter is no longer at terminal count thereby placing the counter back into the count mode. Q0 –> Q5 Table 1. Preset Inputs Versus Divide Ratio S0 CLOCK CLK “LO” Divide S1 COUT COUT D0 –> D5 Figure 3. 6-bit Programmable Divider MOTOROLA 2–6 Preset Data Inputs Ratio D5 D4 D3 D2 D1 D0 2 3 4 5 • • 36 37 38 • • 62 63 64 L L L L • • H H H • • H H H L L L L • • L L L • • H H H L L L L • • L L L • • H H H L L L H • • L H H • • H H H L H H L • • H L L • • L H H H L H L • • H L H • • H L H ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E136 MC100E136 LOAD 100100 100011 100010 000011 000010 000001 000000 LOAD ••• CLOCK ••• S1 ••• COUT DIVIDE BY 37 Figure 4. Programmable Divider Waveforms superiority of the E016 diminishes, and in fact for very wide dividers the E136 will provide the capability of a faster count frequency. This potential is a result of the cascading features mentioned previously in this document. Figure 5 shows the architecture of a 24-bit programmable divider implemented using E136 counters. Note the need for one external gate to control the loading of the entire counter chain. An ideal device for the external gating of this architecture would be the 4-input OR function in the 8-lead SOIC ECLinPS Lite family. However the final decision as to what device to use for the external gating requires a balancing of performance needs, cost and available board space. Note that because of the need for external gating the maximum count frequency of a given sized programmable divider will be less than that of a single cascaded counter. The exercise of building a programmable divider then becomes simply determining what value to load into the counter to accomplish the desired division. Since the load operation requires a clock pulse, to divide by N, N–1 must be loaded into the counter. A single E136 device is capable of divide ratios of 2 to 64 inclusive, Table 1 outlines the load values for the various divide ratios. Figure 4 presents the waveforms resulting from a divide by 37 operation. Note that the availability of the COUT complimentary output COUT allows the user to choose the polarity of the divide by output. For single device programmable counters the E016 counter is probably a better choice than the E136. The E016 has an internal feedback to control the reloading of the counter, this not only simplifies board design but also will result in a faster maximum count frequency. For programmable dividers of larger than 8 bits the Q0 –> Q5 CLOCK CLK Q0 –> Q5 CLK S1 Q0 –> Q5 Q0 –> Q5 CLK S1 S1 CLK LSB S1 MSB “LO” CIN COUT “LO” CLIN CLOUT D0 –> D5 “LO” CIN COUT CIN COUT CIN COUT CLIN CLOUT CLIN CLOUT CLIN CLOUT D0 –> D5 D0 –> D5 D0 –> D5 Figure 5. 24-bit Programmable Divider Architecture ECLinPS and ECLinPS Lite DL140 — Rev 4 2–7 MOTOROLA MC10E136 MC100E136 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) B Y BRK -N- T L –M M U 0.007 (0.180) X G1 M S N T L –M S S N S D Z -L- -M- D W 28 V 1 C A 0.007 (0.180) M R 0.007 (0.180) M T L –M S T L –M S N S N S H S N S 0.007 (0.180) M T L –M N S S 0.004 (0.100) G J -T- K SEATING PLANE F VIEW S G1 T L –M S N 0.007 (0.180) M T L –M S N S VIEW S S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MOTOROLA T L –M K1 E S S VIEW D-D Z 0.010 (0.250) 0.010 (0.250) 2–8 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 — 0.025 — 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 — 0.020 2° 10° 0.410 0.430 0.040 — MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 — 0.64 — 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 — 0.50 2° 10° 10.42 10.92 1.02 — ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E136 MC100E136 Motorola reserves the right to make changes without further notice to any products herein. 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