UC1524A UC2524A UC3524A Advanced Regulating Pulse Width Modulators FEATURES • • • DESCRIPTION The UC1524A family of regulating PWM ICs has been designed to retain the same highly versatile architecture of the industry standard UC1524 (SG1524) while offering substantial improvements to many of its limitations. The UC1524A Precision Reference Internally is pin compatible with “non-A” models and in most existing applications can be Trimmed to ±1% directly interchanged with no effect on power supply performance. Using the High-Performance Current Limit UC1524A, however, frees the designer from many concerns which typically had Function required additional circuitry to solve. Fully Interchangeable with Standard UC1524 Family • Under-Voltage Lockout with Hysteretic Turn-on • Start-Up Supply Current Less Than 4mA • Output Current to 200mA • 60V Output Capability • Wide Common-Mode Input Range for both Error and Current Limit Amplifiers • PWM Latch Insures Single Pulse per Period • Double Pulse Suppression Logic • 200ns Shutdown through PWM Latch • Guaranteed Frequency Accuracy • Thermal Shutdown Protection The UC1524A includes a precise 5V reference trimmed to ±1% accuracy, eliminating the need for potentiometer adjustments; an error amplifier with an input range which includes 5V, eliminating the need for a reference divider; a current sense amplifier useful in either the ground or power supply output lines; and a pair of 60V, 200mA uncommitted transistor switches which greatly enhance output versatility. An additional feature of the UC1524A is an under-voltage lockout circuit which disables all the internal circuitry, except the reference, until the input voltage has risen to 8V. This holds standby current low until turn-on, greatly simplifying the design of low power, off-line supplies. The turn-on circuit has approximately 600mV of hysteresis for jitter-free activation. Other product enhancements included in the UC1524A’s design include a PWM latch which insures freedom from multiple pulsing within a period, even in noisy environments, logic to eliminate double pulsing on a single output, a 200ns external shutdown capability, and automatic thermal protection from excessive chip temperature. The oscillator circuit of the UC1524A is usable beyond 500kHz and is now easier to synchronize with an external clock pulse. The UC1524A is packaged in a hermetic 16-pin DIP and is rated for operation from -55°C to +125°C. The UC2524A and 3524A are available in either ceramic or plastic packages and are rated for operation from -40°C to +85°C and 0°C to 70°C, respectively. Surface mount devices are also available. BLOCK DIAGRAM VIN OSC 3 RT 6 CT 7 T OSC 9 N.I. INPUT 1 200mV 4 CL (–) SENSE 5 VIN + CL (+) SENSE + – COMP S VREF 12 CA 11 EA 13 CB 14 EB 10 SHUTDOWN 8 GND FLIP FLOP R PWM S LATCH – E/A + 2 16 CLOCK VIN INV. INPUT POWER TO INTERNAL CIRCUITRY U.V. SENSE RAMP COMP +5V REFERENCE REGULATOR 15 + C/L – 1k 6V 10k 5.5V UDG-99178 SLUS181A - NOVEMBER 1999 UC1524A UC2524A UC3524A ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAMS Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Collector Supply Voltage (VC) . . . . . . . . . . . . . . . . . . . . . . . 60V Output Current (each Output). . . . . . . . . . . . . . . . . . . . . 200mA Maximum Forced Voltage (Pin 9, 10) . . . . . . . . . . . . . -3 to +5V Maximum Forced Current (Pin 9, 10) . . . . . . . . . . . . . . . ±10mA Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . . 50mA Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . 5mA Power Dissipation at TA = +25°C. . . . . . . . . . . . . . . . . 1000mW Power Dissipation at TC = +25°C . . . . . . . . . . . . . . . . 2000mW Operating Temperature Range . . . . . . . . . . . . -55°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature, (Soldering, 10 seconds) . . . . . . . . . +300°C Note: Consult packaging section of Databook for thermal limitations and considerations of package. PLCC-20, LCC-20 (TOP VIEW) Q or L Package PACKAGE PIN FUNCTION FUNCTION PIN N/C Inv. Input Non-Inv. Input OSC/SYNC C.L. (+) sense N/C C.L. (-) sense RT CT Ground N/C Compensation Shutdown Emitter A Collector A N/C Collector B Emitter B +VIN +5V VREF DIL-16, SOIC-16 (TOP VIEW) J or N Package, DW Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the UC1524A, -40° to +85°C for the UC2524A, and 0°C to + 70°C for the UC3524A; VIN = VC = 20V, TA = TJ. UC1524A / UC2524A PARAMETER TEST CONDITIONS MIN UC3524A TYP MAX MIN 40 8 7.5 8.5 6.5 UNITS TYP MAX 40 V 7.5 8.5 V Turn-on Characteristics Input Voltage Operating Range after Turn-on Turn-on Threshold 8 6.5 Turn-on Current VIN = 6V Operating Current VIN = 8 to 40V Turn-on Hysteresis* 2.5 4 2.5 4 mA 5 10 5 10 mA 0.5 0.5 V Reference Section Output Voltage TJ = 25°C 4.95 Over Operating Range 4.9 5.00 5.05 4.90 5.1 4.85 5.00 5.10 V 5.15 V Line Regulation VIN = 10 to 40V 10 20 10 30 mV Load Regulation IL = 0 to 20 mA 20 25 20 35 mV Temperature Stability* Over Operating Range* 20 25 20 35 mV Short Circuit Current VREF = 0, 25°C ≤ TJ ≤ 125°C 80 100 80 100 mA Output Noise Voltage* 10Hz ≤ f ≤ 10kHz, TJ =25°C 40 Long Term Stability* TJ =125°C, 1000 Hrs. 20 * These parameters are ensured by design but not 100% tested in production. 2 µVrms 40 50 20 50 mV UC1524A UC2524A UC3524A ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the UC1524A, -40° to +85°C for the UC2524A, and 0°C to + 70°C for the UC3524A; VIN = VC = 20V, TA = TJ. UC1524A / UC2524A PARAMETER TEST CONDITIONS MIN TYP MAX UC3524A MIN TYP 45 39 43 45.9 38.2 UNITS MAX Oscillator Section (Unless otherwise specified, RT = 2700Ω, CT = 0.01 mfd) Initial Accuracy TJ = 25°C 41 Over Operating Range 43 40.2 Temperature Stability* Over Operating Temperature Range Minimum Frequency RT = 150kΩ, CT = 0.1mfd Maximum Frequency RT = 2.0kΩ, CT = 470pF 1 2 1 140 500 Output Amplitude* 3 47 kHz 47.9 kHz 2 % 120 Hz 500 3.5 3 kHz 3.5 V Output Pulse Width* 0.29 0.5 1.0 0.3 0.5 1.0 µs Ramp Peak 3.3 3.5 3.7 3.3 3.5 3.7 V 0.8 0.9 0.7 0.8 0.9 Ramp Valley TJ = 25°C 0.7 Ramp Valley T.C. -1.0 -1.0 V mV/°C Error Amplifier Section (Unless otherwise specified, VCM = 2.5V) Input Offset Voltage Input Bias Current Input Offset Current Common Mode Rejection Ratio VCM = 1.5 to 5.5V Power Supply Rejection Ratio VIN = 10 to 40V Output Swing (Note 1) Open Loop Voltage Gain 0.5 5 1 .05 Gain-Bandwidth* TJ = 25°C, AV = 0dB DC Transconductance*§ TJ = 25°C, 30kΩ ≤ RL ≤ 1MΩ 10 mV 5 1 10 µA 1 0.5 1 µA 70 80 70 80 dB 70 80 70 80 dB 5.0 ∆VO= 1 to 4V, RL ≥ 10MΩ 2 72 0.5 80 5.0 64 0.5 V 80 dB 1 3 1 3 MHz 1.7 2.3 1.7 2.3 mS P.W.M. Comparator (RT = 2kΩ, CT = 0.01mfd) Minimum Duty Cycle VCOMP = 0.5V Maximum Duty Cycle VCOMP = 3.8V 0 45 0 45 % % Current Limit Amplifier (Unless otherwise specified, Pin 5 = 0V) Input Offset Voltage TJ = 25°C, E/A Set for Maximum Output 190 Over Operating Temperature Range 180 Input Bias Current 200 -1 Common Mode Rejection Ratio V(pin 5) = -0.3V to + 5.5V 210 180 220 170 -10 200 -1 220 mV 230 mV -10 µA 50 60 50 60 dB Power Supply Rejection Ratio VIN = 10 to 40V 50 60 50 60 dB Output Swing (Note 1) Minimum Total Range 5.0 Open-Loop Voltage Gain ∆VO = 1 to 4V, RL ≥ 10MΩ 70 Delay Time* Pin 4 to Pin 9, ∆VIN = 300mV 0.5 80 5.0 70 300 0.5 V 80 dB 300 ns Output Section (Each Output) Collector Emitter Voltage IC = 100µA Collector Leakage Current VCE = 50V 60 80 .1 60 20 80 .1 * These parameters are ensured by design but not 100% tested in production. § DC transconductance (gM) relates to DC open-loop voltage gain according to the following equation: AV = gMRL where RL is the resistance from pin 9 to the common mode voltage. The minimum gM specification is used to calculate minimum AV when the error amplifier output is loaded. Note 1: Min Limit applies to output high level, max limit applies to output low level. 3 V 20 µA UC1524A UC2524A UC3524A ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the UC1524A, -40° to +85°C for the UC2524A, and 0°C to + 70°C for the UC3524A; VIN = VC = 20V. TA = TJ. PARAMETER TEST CONDITIONS UC1524A / UC2524A MIN TYP MAX Output Section ( cont.) (Each Output) Saturation Voltage IC = 20mA IC = 200mA 17 Emitter Output Voltage IE = 50mA Rise Time* TJ = 25°C, R = 2kΩ Fall Time* TJ = 25°C, R = 2kΩ Comparator Delay* TJ = 25°C, Pin 9 to output Shutdown Delay* TJ = 25°C, Pin 10 to output 0.6 Shutdown Threshold TJ = 25°C, RC = 2kΩ S/D Threshold Over Temp. Over Operating Temperature Range 0.4 Thermal Shutdown* * These parameters are ensured by design but not 100% tested in production. OPEN-LOOP CIRCUIT 4 .2 1 18 120 25 300 200 .7 165 MIN .4 2.2 17 400 200 1.0 1.2 0.6 0.4 UC3524A UNITS TYP MAX .2 1 18 120 25 300 200 .7 165 .4 2.2 400 200 1.0 1.0 V V V ns ns ns ns V V °C UC1524A UC2524A UC3524A Supply Current vs Voltage Error Amplifier Voltage Gain and Phase vs Frequency Pulse Width Modulator Transfer Function Oscillator Frequency vs Timing Components Output Dead Time vs Timing Capacitor Value Output Saturation Voltage 5 UC1524A UC2524A UC3524A Shutdown Delay From PWM Comparator - Pin 9 Current Limit Amplifier Delay Turn-Off Delay From Shutdown - Pin 10 6 PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8764502EA ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC UC1524AJ ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC UC1524AJ/80503 ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC UC1524AJ883B ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC UC1524AL ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC UC1524AL883B ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC UC2524ADW ACTIVE SOIC DW 16 40 None CU NIPDAU Level-2-220C-1 YEAR UC2524ADWTR ACTIVE SOIC DW 16 2000 None CU NIPDAU Level-2-220C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) UC2524AJ ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC UC2524AN ACTIVE PDIP N 16 25 None CU SNPB Level-NA-NA-NA UC2524ANG4 ACTIVE PDIP N 16 CU NIPDAU Level-NA-NA-NA 1000 Green (RoHS & no Sb/Br) UC3524ADW ACTIVE SOIC DW 16 40 None CU NIPDAU Level-2-220C-1 YEAR UC3524ADWTR ACTIVE SOIC DW 16 2000 None CU NIPDAU Level-2-220C-1 YEAR UC3524AJ ACTIVE CDIP J 16 1 None A42 SNPB Level-NC-NC-NC UC3524AN ACTIVE PDIP N 16 25 None CU SNPB Level-NA-NA-NA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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