SEMICONDUCTOR TECHNICAL DATA The MC1650 and the MC1651 are very high speed comparators utilizing differential amplifier inputs to sense analog signals above or below a reference level. An output latch provides a unique sample-hold feature. The MC1650 provides high impedance Darlington inputs, while the MC1651 is a lower impedance option, with higher input slew rate and higher speed capability. The clock inputs (Ca and Cb) operate from MECL III or MECL 10,000 digital levels. When Ca is at a logic high level, Q0 will be at a logic high level provided that V1 V2 (V1 is more positive than V2). Q0 is the logic complement of Q0. When the clock input goes to a low logic level, the outputs are latched in their present state. Assessment of the performance differences between the MC1650 and the MC1651 may be based upon the relative behaviors shown in Figures 4 and 7. u L SUFFIX CERAMIC PACKAGE CASE 620–10 LOGIC DIAGRAM V1A 6 + V2A 5 – D Q 2 Q0 Q 3 Q0 PIN ASSIGNMENT CA 4 V1B 12 + – V2B 11 D 14 Q1 Q Q CB 13 15 Q1 VCC = +5.0 V = PIN 7, 10 VEE = –5.2 V = PIN 8 GND = PIN 1, 16 • • • • • • • PD = 330 mW typ/pkg (No Load) tpd = 3.5 ns typ (MC1650) = 3.0 ns typ (MC1651) Input Slew Rate = 350 V/µs (MC1650) = 500 V/µs (MC1651) Differential Input Voltage: 5.0 V (–30°C to +85°C) Common Mode Range: –3.0 V to +2.5 V (–30°C to +85°C) (MC1651) –2.5 V to +3.0 V (–30°C to +85°C) (MC1650) Resolution: 20 mV (–30°C to +85°C) Drives 50 Ω lines p Number at end of terminal denotes pin number for L package (Case 620). TRUTH TABLE C H H L V1 , V2 u V2 V1 t V2 V1 X X Q0n + 1 Q0n + 1 H L L H Q0n Q0n 3/93 Motorola, Inc. 1996 4–334 REV 5 GND 1 16 GND Q0 2 15 Q1 Q0 3 14 Q1 CA 4 13 CB V2A 5 12 V1B V1A 6 11 V2B VCC 7 10 VCC VEE 8 9 NC MC1650 MC1651 ELECTRICAL CHARACTERISTICS Test Limits –30°C Characteristic Symbol Min +25°C Max Min +85°C Max Min Unit Max Power Supply Drain Current Positive Negative ICC IE 25* 55* mAdc Input Current MC1650 MC1651 Iin 10 40 µAdc Input Leakage Current MC1650 MC1651 IR 7.0 10.0 µAdc Output Voltage Logic 1 VOH –1.045 –0.875 –0.960 –0.810 –0.890 –0.700 Vdc Output Voltage Logic 0 VOL –1.890 –1.650 –1.850 –1.620 –1.830 –1.575 Vdc Threshold Voltage (Note 2.) Logic 1 VOHA –1.065 Clock Input Current IinH 350 –0.980 Threshold Voltage (Note 2.) Logic 0 VOLA –1.630 –1.600 1. All data is for 1/2 MC1650 or MC1651, except data marked (*) which refers to the entire package. 2. These tests are done in order indicated. See Figure 5. 3. Maximum Power Supply Voltages (beyond which device life may be impaired): |VEE| + |VCC| ≥ 12 Vdc. 4. All Temperature VA3 VA4 VA5 VA6 MC1650 +3.0 +2.98 –2.5 –2.48 MC1651 +2.5 +2.48 –3.0 –2.98 MECL Data DL122 — Rev 6 4–335 –0.910 Vdc –1.555 Vdc MOTOROLA MC1650 MC1651 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) @ Test Temperature VIHmax VILmin VIHAmin VILAmax VA1 VA2 –30°C –0.875 –1.890 –1.180 –1.515 +0.02 +0.02 +25°C –0.810 –1.850 –1.095 –1.485 +0.02 +0.02 +85°C –0.700 –1.830 –1.025 –1.440 +0.02 +0.02 VA3 VA4 VA5 VA6 S Note See N 4 4. VCC3. VEE3. +5.0 –5.2 +5.0 –5.2 +5.0 –5.2 TEST VOLTAGE APPLIED TO PINS LISTED BELOW Characteristic Symbol VIHmax ICC IE 4,13 MC1650 MC1651 Iin Input Leakage MC1650 Current MC1651 IR Power Supply Drain Current Input Current Pos Neg VILmin VIHAmin VILAmax VA1 4,13 6,12 6,12 4 13 12 4 13 12 13 6,12 Clock Input Current IinH 4 Output Voltage Logic 1 VOH 4,13 VA2 VA3 VA4 VA5 VA6 1,5,11,16 1,5,11,16 6 1,5,11,16 6 1,5,11,16 1,5,11,16 6,12 5,11 6,12 5,11 5,11 6,12 6,12 5,11 6,12 5,11 5,11 Output Voltage Logic 0 VOL 4,13 6,12 6,12 5,11 5,11 6,12 6,12 5,11 5,11 6,12 6,12 5,11 6,12 Threshold Voltage Note 2. Logic 1 VOHA 13 4 4 Logic 0 VOLA 13 4 1,5,11,16 1,6,12,16 1,16 1,16 1,5,11,16 1,6,12,16 1,16 1,16 1,5,16 6 6 4 1,5,16 6 6 4 4 1,5,11,16 1,6,12,16 1,16 1,16 1,5,11,16 1,6,12,16 1,16 1,16 6 6 4 Threshold Voltage Note 2. 5,11 6 4 (VCC) Gnd 6 1. All data is for 1/2 MC1650 or MC1651, except data marked (*) which refers to the entire package. 2. These tests are done in order indicated. See Figure 5. 3. Maximum Power Supply Voltages (beyond which device life may be impaired): |VEE| + |VCC| ≥ 12 Vdc. 4. All Temperature VA3 VA4 VA5 VA6 MC1650 +3.0 +2.98 –2.5 –2.48 MC1651 +2.5 +2.48 –3.0 –2.98 Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. MOTOROLA 4–336 MECL Data DL122 — Rev 6 MC1650 MC1651 CIRCUIT SCHEMATIC 1/2 of Device Shown MC1650 Inputs (Both Devices) VCC 7, 10 A B C Gnd 1 Gnd 16 A B V1 6 C 2Q 3Q V2 5 D E MC1651 Inputs A B C D V1 6 E RP V2 5 8 VEE D 4 Clock E SWITCHING TEST VOLTAGE VALUES (Volts) @Test Temperature –30°C VR1 +2.0 +25°C +2.0 +85°C +2.0 VR2 VR3 S N See Note 4 VX +1.04 VXX +2.0 VCC1 +7.0 VEE1 –3.2 +1.11 +2.0 +7.0 –3.2 +1.19 +2.0 +7.0 –3.2 –30°C Characteristic Ch i i Symbol S b l Switching Times Propagation Delay (50% to 50%) V-Input Clock2 Clock Enable3 Clock Aperture3 Min Max +25°C Min Max +85°C Min Max Unit U i ns tpd 2.0 5.0 2.0 5.0 2.0 5.7 2.0 4.7 2.0 4.7 2.0 5.2 tsetup tap — — 2.5 — — — ns — — 1.5 — — — ns t+ t– 1.0 3.5 1.0 3.5 1.0 3.8 ns 1.0 3.0 1.0 3.0 1.0 3.3 ns Rise Time (10% to 90%) Fall Time (10% to 90%) Conditions (See Figures 1–3) VR1 to V2, VX to Clock, P1 to V1, or, VR2 to V2, VX to Clock, P2 to V1, or, VR3 to V2, VX to Clock, P3 to V1. VR1 to V2, P1 to V1 and P4 to Clock, or, VR1 to V1, P1 to V2 and P4 to Clock. VR1 to V2, P1 to V1, P4 to Clock Clock P1 to V1. VR to V2, VX to Clock, NOTES: 1. Maximum Power Supply Voltages (beyond which device life may be impaired: VCC + VEE 12 Vdc. 2. Unused clock inputs may be tied to ground. 3. See Figure 3. q 4. All Temperatures VR2 VR3 MC1650 +4.9 –0.4 MC1651 +4.4 –0.9 MECL Data DL122 — Rev 6 4–337 MOTOROLA MC1650 MC1651 FIGURE 1 — SWITCHING TIME TEST CIRCUIT @ 25°C VCC = + 7.0 Vdc Vin to Channel A 0.1 µF 0.1 µF VR1, VR2, VR3 10 Coax 16 7 1 VCC Gnd + – P1 P2 P3 Vout to Channel B VXX = + 2.0 Vdc D Q C Q D Q C Q VX + – P4 VEE 0.1 µF VEE = –3.2 Vdc Note: All power supply and logic levels are shown shifted 2.0 volts positive. 50 ohm termination to ground located in each scope channel input. All input and output cables to the scope are equal lengths of 50 ohm coaxial cable. FIGURE 2 — SWITCHING AND PROPAGATION WAVEFORMS @ 25°C The pulse levels shown are used to check ac parameters over the full common-mode range. CLOCK TO OUTPUT V — INPUT TO OUTPUT 50% Vin tpd 50% Q VIH VR 50% VIL tpd P1 VIH + 2.1 V VR + 2.0 V 50% Vin 40 ns 30 ns 30 ns 40 ns 30 ns 90% 30 ns 10% t+ P4 t– +1.11 V 50% +0.31 V C Test pulses: t +, t – = 1.5 ± 0.2 ns (10% to 90%) f = 5.0 MHz 50% Duty Cycle VIL + 1.9 V tpd tpd 50% Q P4: t +, t – = 1.5 ± 0.2 ns. TEST PULSE LEVELS P1 MOTOROLA P2 P3 MC1650 MC1651 MC1650 MC1651 MC1650 MC1651 VIH +2.1 V +2.1 V +5.0 V +4.5 V –0.3 V –0.8 V VR +2.0 V +2.0 V +4.9 V +4.4 V –0.4 V –0.9 V VIL +1.9 V +1.9 V +4.8 V +4.3 V –0.5 V –1.0 V 4–338 MECL Data DL122 — Rev 6 MC1650 MC1651 FIGURE 3 — CLOCK ENABLE AND APERTURE TIME TEST CIRCUIT AND WAVEFORMS @ 25°C Vin to Channel A VCC = +7.0 Vdc 0.1 µF 0.1 µF 10 Vin VR Vout to Channel B VXX = +2.0 Vdc 7 1 16 VCC Gnd + – + – D Q C Q D Q C Q 50 VEE 8 VEE = –3.2 Vdc 0.1 µF 50 ohm termination to ground located in each scope channel input. All input and output cables to the scope are equal lengths of 50 ohms coaxial cable. ANALOG SIGNAL POSITIVE AND NEGATIVE SLEW CASE Vin Negative VR + 100 mV = +2.1 V VR = 2.0 V Vin Positive Clock Enable Time C VR – 100 mV = +1.9 V VIH = +1.11 V 50% Clock Aperature Time tpd 50% Q Positive VIL = +0.31 V “1” V V Q Negative “0” “1” 50% “0” tpd Clock enable time = minimum time between analog and clock signal such that output switches, and tpd (analog to Q) is not degraded by more than 200 ps. Clock aperture time = time difference between clock enable time and time that output does not switch and V is less than 150 mV. Note: All power supply and logic levels are shown shifted 2.0 volts positive. MECL Data DL122 — Rev 6 4–339 MOTOROLA MC1650 MC1651 FIGURE 4 — PROPAGATION DELAY (tpd) versus INPUT PULSE AMPLITUDE AND CONSTANT OVERDRIVE TEST CIRCUIT Vin Vref + – D Q Q 1/2 Device VIH C 50 50 –2.0 V Q 50 Vref = Gnd POSITIVE PULSE DIAGRAM Positive Overdrive NEGATIVE PULSE DIAGRAM Negative Overdrive Vref Vin Vin Vref PA PB tpd tpd Q 50% Q Input Switching time is constant at 1.5 ns (10% to 90%). PROPAGATION DELAY versus PULSE AMPLITUDE PROPAGATION DELAY INCREASE (ns) 5.0 4.0 Overdrive Constant @ 100 mV Positive Going Pulse Negative Going Pulse MC1650 3.0 MC1651 2.0 1.0 tpd referenced to PA, PB = 20 mV 0 0.01 0.02 0.05 0.1 0.2 0.5 1.0 PULSE AMPLITUDE PA, PB (VOLTS) 2.5 10 PROPAGATION DELAY INCREASE (ns) PROPAGATION DELAY versus OVERDRIVE 2.0 MC1650 1.0 MC1651 tpd is referenced to 2.5 V overdrive. 0 0.01 MOTOROLA PA, PB, Constant @ 100 mV Positive Overdrive (PA) Negative Overdrive (PB) tpd is measured from Vref on the input to 50% on the output. 0.02 0.04 0.07 0.1 0.2 0.3 0.5 0.7 1.0 OVERDRIVE (VOLTS) 4–340 2.5 10 MECL Data DL122 — Rev 6 MC1650 MC1651 FIGURE 5 — LOGIC THRESHOLD TESTS (WAVEFORM SEQUENCE DIAGRAM) +0.02 V Vin –0.02 V VIHA C VILA “1” Q “0” “1” Q “0” Sequential Test Number (See Test Table) 1 2 3 4 FIGURE 6 — TRANSFER CHARACTERISTICS (Q versus Vin) TEST CONFIGURATION + Differential Input Vin + – D – Q Q 1/2 Device VIH C Vref –2.5 Vdc Q 50 p Vref p +2.5 Vdc –2.0 Vdc TYPICAL TRANSFER CURVES Q. OUTPUT VOLTAGE (VOLTS) 0 Resolution Logic “1” –1.0 Logic “0” –2.0 –20 MECL Data DL122 — Rev 6 –15 –10 –5.0 5.0 10 Vref Vin, DIFFERENTIAL INPUT VOLTAGE (mV) 4–341 15 20 MOTOROLA MC1650 MC1651 FIGURE 7 — OUTPUT VOLTAGE SWING versus FREQUENCY (A) TEST CIRCUIT V1 + – V2 D Q Q 1/2 Device 50 VIH C 50 –2.0 Vdc Q (B) TYPICAL OUTPUT LOGIC SWING versus FREQUENCY MC1651 PEAK-TO-PEAK OUTPUT (VOLTS) 0.85 0.65 0.45 0.25 50 0.05 10 20 30 50 70 FREQUENCY (MHz) 100 75 100 200 1000 Input Voltage mV Peak-to-Peak 200 300 MC1650 PEAK-TO-PEAK OUTPUT (VOLTS) 0.85 0.65 0.45 0.25 50 0.05 10 MOTOROLA 75 100 200 1000 Input Voltage mV Peak-to-Peak 20 30 50 70 FREQUENCY (MHz) 4–342 100 200 300 MECL Data DL122 — Rev 6 MC1650 MC1651 FIGURE 8 — INPUT CURRENT versus INPUT VOLTAGE TEST CIRCUIT VCC +5.0 Vdc 0.1 µF 7 VCC V1 V2 10 VCC 50 + – D Q C Q D Q C Q –2.0 Vdc Iin Vin + VIH + – 50 – 0.1 µF VEE 8 Gnd 1 Gnd 16 VEE –5.2 Vdc Typical MC1650 (Complementary Input Grounded) Typical MC1651 (Complementary Input Grounded) 30 –30°C 25 +25°C I in , INPUT CURRENT ( µ A) I in , INPUT CURRENT ( µ A) 5 +85°C 0 +25°C 15 10 +85°C 5 0 –5 –2.5 –30°C 20 –2 MECL Data DL122 — Rev 6 –1 0 +1 Vin, INPUT VOLTAGE (VOLTS) +2 +2.5 –5 –2.5 4–343 –2 –1 0 1 Vin, INPUT VOLTAGE (VOLTS) 2 2.5 MOTOROLA MC1650 MC1651 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A M T B S DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S Motorola reserves the right to make changes without further notice to any products herein. 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