SEMICONDUCTOR TECHNICAL DATA The MC10137 is a high speed synchronous counter that can count up, down, preset, or stop count at frequencies exceeding 100 MHz. The flexibility of this device allows the designer to use one basic counter for most applications. The synchronous count feature makes the MC10137 suitable for either computers or instrumentation. Three control lines (S1, S2, and Carry In) determine the operation mode of the counter. Lines S1 and S2 determine one of four operations; preset (program), increment (count up), decrement (count down), or hold (stop count). Note that in the preset mode a clock pulse is necessary to load the counter, and the information present on the data inputs (D0, D1, D2, and D3) will be entered into the counter. Carry Out goes low on the terminal count. The Carry Out on the MC10137 is partially decoded from Q1 and Q2 directly, so in the preset mode the condition of the Carry Out after the Clock’s positive excursion will depend on the condition of Q1 and/or Q2. The counter changes state only on the positive going edge of the clock. Any other input may change at any time except during the positive transition of the clock. The sequence for counting out of improper states is as shown in the State Diagrams. L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 PD = 625 mW typ/pkg (No Load) fcount = 150 MHz typ tpd = 3.3 ns typ (C–Q) = 7.0 ns typ (C–Cout) = 5.0 ns typ (Cin–Cout) PIN ASSIGNMENT STATE DIAGRAMS COUNT UP 0 1 3 2 15 10 4 11 13 12 14 9 8 7 6 1 2 3 4 5 COUNT DOWN 0 11 14 13 12 15 10 9 8 7 6 5 FUNCTION SELECT TABLE S1 S2 Operating Mode L L Preset (Program) L H Increment (Count Up) H L Decrement (Count Down) H H Hold (Stop Count) 3/93 Motorola, Inc. 1996 3–35 REV 5 VCC1 1 16 VCC2 2 2 15 Q1 3 3 14 Q0 COUT 4 13 C D3 5 12 D0 D2 6 11 D1 S2 7 10 CIN VEE 8 9 S1 MC10137 LOGIC DIAGRAM S1 9 S2 7 10 Carry In T J T Q0 T T Q0 C T K T T J T Q1 Q1 C J T J T T Q2 Q2 C Q3 Q3 C 13 Clock VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 14 Q0 12 D0 11 D1 15 Q1 2 Q2 6 D2 3 Q3 5 D3 4 Carry Out NOTE: Flip–flops will toggle when all T inputs are low. SEQUENTIAL TRUTH TABLE* INPUTS OUTPUTS D3 Carry In Clock ** Q0 Q1 Q2 H L X H H H X X L H L L X X X L H H X X X X L H H X X X X L H X X X X H L H X X X X H H X X X L L H H H L X H L H L S1 Q3 Carry Out H L H L H H L L H L L L L L H H H L L L H L H L L L H H H H L L L H X X H H L L L H L L X H H H L L H X X X L H L H L L H X X X X L H H L L L H X X X X L H L L L L L S2 D0 D1 D2 L L H H L H X X L H X L H L L * Truth table shows logic states assuming inputs vary in sequence shown from top to bottom. ** A clock H is defined as a clock input transition from a low to a high logic level. MOTOROLA 3–36 MECL Data DL122 — Rev 6 MC10137 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Power Supply Drain Current Input Current Symbol Pin Pi Under Test IE 8 165 IinH 5,6,11,12 7 9,10 13 350 425 390 460 –30°C Min +25°C Max Min +85°C Max Unit 150 165 mAdc 220 265 245 290 220 265 245 290 µAdc Typ Max 120 0.5 Min µAdc IinL All 0.5 Output Voltage Logic 1 VOH 14 (2.) –1.060 –0.890 –0.960 –0.810 –0.890 0.3 –0.700 Vdc Output Voltage Logic 0 VOL 14 (2.) –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc Threshold Voltage Logic 1 VOHA 14 (2.) –1.080 Threshold Voltage Logic 0 VOLA 14 (2.) –0.980 –0.910 –1.655 –1.630 Vdc –1.595 Switching Times (50Ω Load) Propagation Delay Clock Input t13+14+ t13+14– t13+4+ t13+4– 14 14 4 4 0.8 0.8 2.0 2.0 4.8 4.8 10.9 10.9 1.0 1.0 2.5 2.5 3.3 3.3 7.0 7.0 4.5 4.5 10.5 10.5 1.1 1.1 2.4 2.4 5.0 5.0 11.5 11.5 Carry In to Carry Out t10–4– t10+4+ 4 (3.) 4 1.6 1.6 7.4 7.4 1.6 1.6 5.0 5.0 6.9 6.9 1.9 1.9 7.5 7.5 Data Inputs t12+13+ t12–13+ 14 14 3.5 3.5 3.5 3.5 3.5 3.5 Select Inputs t9+13+ t7+13+ 14 14 7.5 7.5 7.5 7.5 7.5 7.5 Carry In Input t10–13+ t13+10+ 14 14 4.5 –1.0 3.7 –1.0 4.5 –1.0 Data Inputs t13+12+ t13+12– 14 14 0 0 0 0 0 0 Select Inputs t13+9+ t13+7+ 14 14 –2.5 –2.5 –2.5 –2.5 –2.5 –2.5 Carry In Input t13+10– t10+13+ 14 14 –1.6 4.0 –1.6 3.1 –1.6 4.0 fcountup fcountdown 14 14 125 125 125 125 150 150 Setup Time Hold Time Counting Frequency Vdc ns 125 125 MHz Rise Time (20 to 80%) t4+ t14+ 4 14 0.9 0.9 3.3 3.3 1.1 1.1 2.0 2.0 3.3 3.3 1.1 1.1 3.5 3.5 Fall Time (20 to 80%) t4– t14– 4 14 0.9 0.9 3.3 3.3 1.1 1.1 2.0 2.0 3.3 3.3 1.1 1.1 3.5 3.5 ns 1. Individually apply VILmin to pin under test. VIH appears at clock input (Pin 13). 2. Measure output after clock pulse VIL 3. Before test set Q1 and Q2 outputs to a logic low. MECL Data DL122 — Rev 6 3–37 MOTOROLA MC10137 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE –30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2 Symbol Power Supply Drain Current Input Current Pin Under Test IE 8 IinH 5,6,11,12 7 9,10 13 IinL All VOH 14 (2.) TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VEE (VCC) Gnd 8 1, 16 8 8 8 8 1, 16 1, 16 1, 16 1, 16 Note 1. 8 1, 16 7, 9 8 1, 16 8 1, 16 8 1, 16 VILmin Logic 1 Output Voltage Logic 0 VOL 14 (2.) 7, 9 Threshold Voltage Logic 1 VOHA 14 (2.) 7, 9 Logic 0 VOLA 14 (2.) Switching Times (50Ω Load) Propagation Delay Clock Input VILAmax 5,6,11,12 7 9,10 13 Output Voltage Threshold Voltage VIHAmin 12 12 7, 9 +1.11V 12 8 1, 16 Pulse In Pulse Out –3.2 V +2.0 V 13 13 13 13 14 14 4 4 8 8 8 8 1, 16 1, 16 1, 16 1, 16 13 13 10 10 4 4 8 8 1, 16 1, 16 7, 9 7, 9 12, 13 12, 13 14 14 8 8 1, 16 1, 16 9, 13 7, 13 14 14 8 8 1, 16 1, 16 9 9 10, 13 10, 13 14 14 8 8 1, 16 1, 16 7, 9 7, 9 12, 13 12, 13 14 14 8 8 1, 16 1, 16 9, 13 7, 13 14 14 8 8 1, 16 1, 16 10, 13 10, 13 14 14 8 8 1, 16 1, 16 +0.31V t13+14+ t13+14– t13+4+ t13+4– 14 14 4 4 12 Carry In to Carry Out t10–4– t10+4+ 4 (3.) 4 7 7 Data Inputs t12+13+ t12–13+ 14 14 Select Inputs t9+13+ t7+13+ 14 14 Carry In Inputs t10–13+ t13+10+ 14 14 Data Inputs t13+12+ t13+12– 14 14 Select Inputs t13+9+ t13+7+ 14 14 Carry In Inputs t13+10– t10+13+ 14 14 7 7 fcountup fcountdown 14 14 7 9 13 13 14 14 8 8 1, 16 1, 16 Setup Time Hold Time Counting Frequency 7 7 7 7 9 9 Rise Time (20 to 80%) t4+ t14+ 4 14 7 7 13 13 4 14 8 8 1, 16 1, 16 Fall Time (20 to 80%) t4– t14– 4 14 7 7 13 13 4 14 8 8 1, 16 1, 16 1. Individually test each input; apply VILmin to pin under test. VIH appears at clock input (Pin 13). 2. Measure output after clock pulse VIL 3. Before test set all Q outputs to a logic high. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. MOTOROLA 3–38 MECL Data DL122 — Rev 6 MC10137 SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C (b) Carry In (a) is the minimum time to wait after the counter has been enabled to clock it. (b) is the minimum time before the counter has been disabled that it may be clocked. (a) Clock (c) is the minimum time before the counter is enabled that a clock pulse may be applied with no effect on the state of the counter. (d) is the minimum time to wait after the counter is disabled that a clock pulse may be applied with no effect in the state of the counter. Carry in (c) (b) and (c) may be negative numbers. (d) Clock VCC1 = VCC2 = +2.0 Vdc Vin NOTE: tsetup is the minimum time before the positive transition of the clock pulse (C) that information must be present at the input D or S. thold is the minimum time after the positive transition of the clock pulse (C) that information must remain unchanged at the input D or S. Coax 25 µF Input Pulse t+ = t– = 2.0 ±0.2 ns (20 to 80%) 0.1 µF 1 16 Cin C D0 Q0 Q2 D2 D3 +1.11 V Clock TPin TPout Cout S2 +0.31 V tC+Q+ Q Output Q3 S1 50% Coax Q1 D1 Clock Input Vout 8 tC+Q– 0.1 µF 80% 50% 20% tQ+ VEE = –3.2 Vdc tQ– +1.11 V C 50% +0.31 V thold H thold L 50% D or S tsetup H tsetup L All input and output cables to the scope are equal lengths of 50-ohm coaxial cable. Wire length should be < 1/4 inch from TPin to input pin and TPout to output pin. Unused outputs are connected to a 50-ohm resistor to ground. Q MECL Data DL122 — Rev 6 50-ohm termination to ground located in each scope channel input. 3–39 MOTOROLA MC10137 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M –A– 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R 16 S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 T A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ MOTOROLA 3–40 *MC10137/D* MC10137/D MECL Data DL122 — Rev 6