Order this document by MC12009/D
These devices are two–modulus prescalers which will divide by 5 and
6, 8 and 9, and 10 and 11, respectively. A MECL–to–MTTL translator is
provided to interface directly with the MC12014 Counter Control Logic. In
addition, there is a buffered clock input and MECL bias voltage source.
• MC12009 480 MHz ( 5/6), MC12011 550 MHz ( 8/9), MC12013
550 MHz ( 10/11)
• MECL to MTTL Translator on Chip
B
•
•
•
•
•
B
B
MECL PLL COMPONENTS
DUAL MODULUS PRESCALER
SEMICONDUCTOR
TECHNICAL DATA
MECL and MTTL Enable Inputs
5.0 or –5.2 V Operation*
Buffered Clock Input — Series Input RC Typ, 20 Ohms and 4 pF
VBB Reference Voltage
310 Milliwatts (Typ)
* When using a 5.0 V supply, apply 5.0 V to Pin 1 (VCCO ), Pin 6
(MTTL V CC ), Pin 16 (V CC ), and ground Pin 8 (V EE ). When using
–5.2 V supply, ground Pin 1 (V CCO ), Pin 6 (MTTL V CC ), and
Pin 16 (V CC ) and apply –5.2 V to Pin 8 (V EE ). If the translator is not
required, Pin 6 may be left open to conserve dc power drain.
16
1
P SUFFIX
PLASTIC PACKAGE
CASE 648
PIN CONNECTIONS
MAXIMUM RATINGS
Characteristic
Symbol
Rating
–8.0
Vdc
Input Voltage
(VCC = 0)
Vin
0 to VEE
Vdc
Output Source Current
Continuous
Surge
IO
t 50
t 100
mAdc
Tstg
–65 to +175
°C
Storage Temperature Range
DC Fan–Out (Note 1)
(Gates and Flip–Flops)
TA
–30 to +85
70
NOTES: 1. AC fan–out is limited by desired system performance.
2. ESD data available upon request.
14 VBB
13 E1 MECL
12 E2 MECL
4
6
MTTL Output
7
11 E3 MECL
10 E4 MECL
VEE
8
9 E5 MECL
(Top View)
ORDERING INFORMATION
°C
Device
n
3
2
5
(Recommended Maximum Ratings above which performance may be
degraded)
Operating Temperature Range
MC12009, MC12011, MC12013
Q
(–)
16 VCC
15 Clock
(+)
(Ratings above which device life may be impaired)
VEE
1
MTTL VCC
Unit
Power Supply Voltage
(VCC = 0)
VCCO
Q
—
Operating
Temperature Range
Package
TA = – 35° to +85°C
Plastic
MC12009P
MC12011P
MC12013P
Motorola, Inc. 1997
Rev 2
MC12009 MC12011 MC12013
Figure 1. Logic Diagrams
MC12009
MTTL E5 9
D
Q1
D
C
Q1
C
Q2
D
MTTL E4 10
MECL
to
MTTL
Trans–
lator
Q3
MECL E3 11
MECL E2 12
C
Q3
MECL E1 13
Recommended Circuitry
For ac coupled Inputs.
VBB
15
1000 pF
Clock Input
14
0.1 µF
1k
3
Q3
2
7
MTTL
Out
5 4
+ –
Q3
MC12011
MTTL E5 9
D
Q1
D
Q2
D
Q4
Toggle
Flip
Flop
C
Q4
Q3
MTTL E4 10
MECL E3 11
C
MECL E2 12
MECL E1 13
C
C
Recommended Circuitry
For ac coupled Inputs.
VBB
15
1000 pF
Clock Input
MECL
to
MTTL
Trans–
lator
14
0.1 µF
1k
3 2
Q4 Q4
7
MTTL
Out
5 4
+ –
MC12013
÷ 10 for one or all
E1 thru E5 high
÷ 11 for all
E1 thru E5 low
Tie unused gate inputs low.
MTTL E5 9
D
D
Q1
Q2
D
Q4
Toggle
Flip
Flop
C
Q4
Q3
MTTL E4 10
MECL E3 11
C
C
MECL E2 12
MECL E1 13
C
Recommended Circuitry
For ac coupled Inputs.
Pull–down resistors required on
Pins 2, 3 when not connected
to translator.
Basic IC Capability: ÷ 10/11
15
1000 pF
Clock Input
1k
MECL
to
MTTL
Trans–
lator
VBB
0.1 µF
14
3 2 5 4
Q4 Q4 + –
7
MTTL
Out
Figure 2. Typical Frequency Synthesizer Application
fref
Phase Detector
MC4044
Voltage–Controlled
Oscillator MC1648
Low–Pass Filter
fout
Modulus Enable Line
MC12009
MC12011
MC12013
Counter Control Logic
MC12014
Zero Detect Line
fout
B Np Programmable
Counter MC4016
B A Programmable
Counter MC4016
Counter Reset Line
2
MOTOROLA RF/IF DEVICE DATA
MC12009 MC12011 MC12013
ELECTRICAL CHARACTERISTICS (Supply Voltage = –5.2 V, unless otherwise noted.)
Test Limits
Symbol
Pin
Pi
Under
Test
Min
Power Supply
pp y Drain Current
ICC1
8
–88
ICC2
6
5.2
5.2
5.2
mAdc
Input Current
IinH1
15
11
12
13
375
375
375
375
250
250
250
250
250
250
250
250
µAdc
IinH2
4
5
1.7
1.7
6.0
6.0
2.0
2.0
6.0
6.0
2.0
2.0
6.4
6.4
mAdc
IinH3
5
0.7
3.0
1.0
3.0
1.0
3.6
IinH4
9
10
IinL1
15
11
12
13
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
µAdc
IinL2
9
10
–1.6
–1.6
–1.6
–1.6
–1.6
–1.6
mAdc
VBB
14
VOH1
(Note 1)
2
3
–1.100
–1.100
VOH2
7
–2.8
VOL1
(Note 1)
2
3
–1.990
–1.990
VOL2
7
Logic ‘1’ Threshold Voltage
VOHA
(Note 2)
2
3
Logic ‘0’ Threshold Voltage
VOLA
(Note 3)
2
3
Characteristic
Leakage Current
Reference Voltage
Logic ‘1’ Output Voltage
Logic ‘0’ Output Voltage
–30°C
+25°C
Max
Min
+85°C
Max
–80
100
100
–0.890
–0.890
100
100
–1.360
–1.160
–1.000
–1.000
–0.810
–0.810
–1.950
–1.950
–4.26
–1.120
–1.120
Unit
mAdc
100
100
µAdc
Vdc
–0.930
–0.930
–0.700
–0.700
Vdc
–1.615
–1.615
Vdc
–2.4
–1.650
–1.650
–1.925
–1.925
–4.40
–1.020
–1.020
–1.655
–1.655
Max
–80
–2.6
–1.675
–1.675
Min
–4.48
–0.950
–0.950
–1.630
–1.630
Vdc
–1.595
–1.595
Short Circuit Current
IOS
7
–65
–20
–65
–20
–65
–20
1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
Clock Input
ground voltages must be maintained between tests. The clock input is the waveform shown.
2. In addition to meeting the output levels specified, the device must divide by 5, 8 or 10 during this test. The clock
input is the waveform shown.
3. In addition to meeting the output levels specified, the device must divide by 6, 9 or 11 during this test. The clock
input is the waveform shown.
Vdc
mAdc
VIHmax
VILmin
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50 Ω resistor to –2.0 V. Test procedures are shown for only one gate. The other gates are tested in the same
manner.
MOTOROLA RF/IF DEVICE DATA
3
MC12009 MC12011 MC12013
ELECTRICAL CHARACTERISTICS (Supply Voltage = –5.2 V, unless otherwise noted.) (continued)
TEST VOLTAGE/CURRENT VALUES
Volts
Characteristic
Power Supply Drain Current
Input Current
Leakage Current
Reference Voltage
Logic ‘1’ Output Voltage
@ Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VIH
VILH
–30°C
–0.890
–1.990
–1.205
–1.500
–2.8
–4.7
+25°C
–0.810
–1.950
–1.105
–1.475
–2.8
–4.7
+85°C
–0.700
–1.925
–1.035
–1.440
–2.8
–4.7
Symbol
Pin
Under
Test
ICC1
8
ICC2
6
4
IinH1
15
11
12
13
15
11
12
13
IinH2
4
5
5
5
4
4
6
6
IinH3
5
4
5
6
IinH4
9
10
IinL1
15
11
12
13
IinL2
9
10
VBB
14
VOH1
(Note 1.)
2
3
VOH2
7
Logic ‘0’ Output Voltage
VOL1
(Note 1.)
2
3
VOL2
7
Logic ‘1’ Threshold Voltage
VOHA
(Note 2.)
2
3
Logic ‘0’ Threshold Voltage
VOLA
(Note 3.)
2
3
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmin
VIHAmin
VILAmax
VIL
G d
Gnd
1,16
5
6
1,16
1,16
1,16
1,16
9
10
1,16
1,16
1,16
1,16
1,16
1,16
9
10
1,16
1,16
1,16
11,12,13
11,12,13
5
4
9,10
9,10
1,16
1,16
9,10
9,10
1,16
1,16
4
6
11,12,13
11,12,13
5
6
11,12,13
11,12,13
1,16
1,16
11,12,13
11,12,13
Short Circuit Current
IOS
7
5
4
1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
ground voltages must be maintained between tests. The clock input is the waveform shown.
2. In addition to meeting the output levels specified, the device must divide by 5, 8 or 10 during this test. The clock
input is the waveform shown.
3. In addition to meeting the output levels specified, the device must divide by 6, 9 or 11 during this test. The clock
input is the waveform shown.
4
VIH
1,16
1,16
7
6
Clock Input
VIHmax
VILmin
MOTOROLA RF/IF DEVICE DATA
MC12009 MC12011 MC12013
ELECTRICAL CHARACTERISTICS (Supply Voltage = –5.2 V, unless otherwise noted.) (continued)
TEST VOLTAGE/CURRENT VALUES
Volts
mA
@ Test Temperature
VIHT
VILT
VEE
IL
IOL
IOH
–30°C
–3.2
–4.4
–5.2
–0.25
16
–0.40
+25°C
–3.2
–4.4
–5.2
–0.25
16
–0.40
+85°C
–3.2
–4.4
–5.2
–0.25
16
–0.40
Characteristic
Power Supply Drain Current
Input Current
Leakage Current
Reference Voltage
Logic ‘1’ Output Voltage
Symbol
Pin
Under
Test
ICC1
8
8
1,16
ICC2
6
8
6
IinH1
15
11
12
13
8
8
8
8
1,16
1,16
1,16
1,16
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHT
VILT
9,10
9,10
9,10
VEE
IL
IOH
G d
Gnd
IinH2
4
5
8
8
6
6
IinH3
5
8
6
IinH4
9
10
8
8
1,16
1,16
IinL1
15
11
12
13
8,15
8,11
8,12
8,13
1,16
1,16
1,16
1,16
IinL2
9
10
8
8
1,16
1,16
VBB
14
8
VOH1
(Note 1.)
2
3
8
8
VOH2
7
8
Logic ‘0’ Output Voltage
VOL1
(Note 1.)
2
3
8
8
VOL2
7
Logic ‘1’ Threshold Voltage
VOHA
(Note 2.)
2
3
Logic ‘0’ Threshold Voltage
VOLA
(Note 3.)
2
3
14
8
9,10
9,10
9,10
9,10
1,16
1,16
1,16
7
6
1,16
1,16
7
6
8
8
1,16
1,16
8
8
1,16
1,16
Short Circuit Current
IOS
7
8
1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
ground voltages must be maintained between tests. The clock input is the waveform shown.
2. In addition to meeting the output levels specified, the device must divide by 5, 8 or 10 during this test. The clock
input is the waveform shown.
3. In addition to meeting the output levels specified, the device must divide by 6, 9 or 11 during this test. The clock
input is the waveform shown.
MOTOROLA RF/IF DEVICE DATA
IOL
6
Clock Input
VIHmax
VILmin
5
MC12009 MC12011 MC12013
ELECTRICAL CHARACTERISTICS (Supply Voltage = 5.0 V, unless otherwise noted.)
Test Limits
Symbol
Pin
Pi
Under
Test
Min
Power Supply
pp y Drain Current
ICC1
8
–88
ICC2
6
5.2
5.2
5.2
mAdc
Input Current
IinH1
15
11
12
13
375
375
375
375
250
250
250
250
250
250
250
250
µAdc
IinH2
4
5
1.7
1.7
6.0
6.0
2.0
2.0
6.0
6.0
2.0
2.0
6.4
6.4
mAdc
IinH3
5
0.7
3.0
1.0
3.0
1.0
3.6
IinH4
9
10
100
100
100
100
IinL1
15
11
12
13
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
µAdc
IinL2
9
10
–1.6
–1.6
–1.6
–1.6
–1.6
–1.6
mAdc
VBB
14
VOH1
(Note 4.)
2
3
3.900
3.900
VOH2
7
2.4
VOL1
(Note 4.)
2
3
3.070
3.070
VOL2
7
Logic ‘1’ Threshold Voltage
VOHA
(Note 5.)
2
3
Logic ‘0’ Threshold Voltage
VOLA
(Note 6.)
2
3
Characteristic
Leakage Current
Reference Voltage
Logic ‘1’ Output Voltage
Logic ‘0’ Output Voltage
–30°C
+25°C
Max
Min
+85°C
Max
–80
4.110
4.110
3.67
3.87
4.000
4.000
4.190
4.190
3.110
3.110
0.94
3.880
3.880
Unit
mAdc
100
100
µAdc
Vdc
4.070
4.070
4.300
4.300
Vdc
3.445
3.445
Vdc
2.8
3.410
3.410
3.135
3.135
0.80
3.980
3.980
3.405
3.405
Max
–80
2.6
3.385
3.385
Min
0.72
4.050
4.050
3.430
3.430
Vdc
3.465
3.465
Short Circuit Current
IOS
7
–65
–20
–65
–20
–65
–20
4. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
Clock Input
ground voltages must be maintained between tests. The clock input is the waveform shown.
5. In addition to meeting the output levels specified, the device must divide by 5, 8 or 10 during this test. The clock
input is the waveform shown.
6. In addition to meeting the output levels specified, the device must divide by 6, 9 or 11 during this test. The clock
input is the waveform shown.
Vdc
mAdc
VIHmax
VILmin
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50 Ω resistor to –2.0 V. Test procedures are shown for only one gate. The other gates are tested in the same
manner.
6
MOTOROLA RF/IF DEVICE DATA
MC12009 MC12011 MC12013
ELECTRICAL CHARACTERISTICS (Supply Voltage = 5.0 V, unless otherwise noted.) (continued)
TEST VOLTAGE/CURRENT VALUES
Volts
@ Test Temperature
Characteristic
Power Supply Drain Current
Input Current
Leakage Current
Reference Voltage
Logic ‘1’ Output Voltage
VIHmax
VILmin
VIHAmin
VILAmax
VIH
VILH
–30°C
+4.110
+3.070
+3.795
+3.500
+2.4
+0.5
+25°C
+4.190
+3.110
+3.895
+3.525
+2.4
+0.5
+85°C
+4.300
+3.135
+3.965
+3.560
+2.4
+0.5
Symbol
Pin
Under
Test
ICC1
8
ICC2
6
4
IinH1
15
11
12
13
15
11
12
13
IinH2
4
5
5
5
4
4
8
8
IinH3
5
4
5
8
IinH4
9
10
IinL1
15
11
12
13
IinL2
9
10
VBB
14
VOH1
(Note 4.)
2
3
VOH2
7
Logic ‘0’ Output Voltage
VOL1
(Note 4.)
2
3
VOL2
7
Logic ‘1’ Threshold Voltage
VOHA
(Note 5.)
2
3
Logic ‘0’ Threshold Voltage
VOLA
(Note 6.)
2
3
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
VILmin
VIHAmin
VILAmax
VIL
(VEE)
Gnd
8
5
8
8
8
8
8
9
10
8
8
8,15
8,11
8,12
8,13
9
10
8
8
8
11,12,13
11,12,13
5
9,10
9,10
4
4
8
8
8
11,12,13
11,12,13
9,10
9,10
5
8
8
8
11,12,13
11,12,13
8
8
11,12,13
11,12,13
Short Circuit Current
IOS
7
5
4
4. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
ground voltages must be maintained between tests. The clock input is the waveform shown.
5. In addition to meeting the output levels specified, the device must divide by 5, 8 or 10 during this test. The clock
input is the waveform shown.
6. In addition to meeting the output levels specified, the device must divide by 6, 9 or 11 during this test. The clock
input is the waveform shown.
MOTOROLA RF/IF DEVICE DATA
VIH
8
8
7
8
Clock Input
VIHmax
VILmin
7
MC12009 MC12011 MC12013
ELECTRICAL CHARACTERISTICS (Supply Voltage = 5.0 V, unless otherwise noted.) (continued)
TEST VOLTAGE/CURRENT VALUES
Volts
Characteristic
Power Supply Drain Current
Input Current
Leakage Current
Reference Voltage
Logic ‘1’ Output Voltage
mA
@ Test Temperature
VIHT
VILT
VCC
IL
IOL
IOH
–30°C
+2.0
+0.8
+5.0
–0.25
16
–0.40
+25°C
+2.0
+0.8
+5.0
–0.25
16
–0.40
+85°C
+2.0
+0.8
+5.0
–0.25
16
–0.40
Symbol
Pin
Under
Test
ICC1
8
1,16
8
ICC2
6
6
8
IinH1
15
11
12
13
1,16
1,16
1,16
1,16
8
8
8
8
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHT
VILT
9,10
9,10
9,10
VCC
IL
IOH
(VEE)
Gnd
IinH2
4
5
6
6
8
8
IinH3
5
6
8
IinH4
9
10
1,16
1,16
8
8
IinL1
15
11
12
13
1,16
1,16
1,16
1,16
8,15
8,11
8,12
8,13
IinL2
9
10
1,16
1,16
8
8
VBB
14
1,16
VOH1
(Note 4.)
2
3
1,16
1,16
VOH2
7
6
Logic ‘0’ Output Voltage
VOL1
(Note 4.)
2
3
1,16
1,16
VOL2
7
Logic ‘1’ Threshold Voltage
VOHA
(Note 5.)
2
3
Logic ‘0’ Threshold Voltage
VOLA
(Note 6.)
2
3
14
7
9,10
9,10
8
8
8
6
9,10
9,10
8
8
8
7
8
1,16
1,16
8
8
1,16
1,16
8
8
Short Circuit Current
IOS
7
6
4. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
ground voltages must be maintained between tests. The clock input is the waveform shown.
5. In addition to meeting the output levels specified, the device must divide by 5, 8 or 10 during this test. The clock
input is the waveform shown.
6. In addition to meeting the output levels specified, the device must divide by 6, 9 or 11 during this test. The clock
input is the waveform shown.
8
IOL
8
Clock Input
VIHmax
VILmin
MOTOROLA RF/IF DEVICE DATA
MC12009 MC12011 MC12013
SWITCHING CHARACTERISTICS
MC12009, MC12011, MC12013
TEST VOLTAGES/WAVEFORMS APPLIED TO PINS LISTED BELOW:
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
U it
Pulse
Gen.3
VILmin
Symbol
S
b l
Pulse
Gen.2
VIHmin
Characteristic
Ch
t i ti
Pin
Under
Test
{
VF
–3.0 V
VEE
–3.0 V
VCC
+2.0
Propagation Delay
(See Figures 3 and 5)
t15+ 2+
t15+ 2–
t5+ 7+
t5– 7–
2
2
7
7
—
—
—
—
—
—
—
—
8.1
7.5
8.4
6.5
—
—
—
—
—
—
—
—
8.1
7.5
8.1
6.5
—
—
—
—
—
—
—
—
8.9
82
8.9
7.1
ns
15
15
A
A
—
—
—
—
—
—
—
—
—
—
—
—
11,12,13
11,12,13
—
—
9,10
9,10
—
—
8
8
8
8
1,6,16
1,6,16
1,6,16
1,6,16
Setup Time
(See Figures 4 and 5)
tsetup1
tsetup2
11
9
5.0
5.0
—
—
—
—
5.0
5.0
—
—
—
—
5.0
5.0
—
—
—
—
ns
ns
15
15
*
—
—
*
—
—
*
11,12,13
9,10
*
8
8
1,6,16
1,6,16
Release Time
(See Figures 4 and 5)
trel1
trel2
11
9
5.0
5.0
—
—
—
—
5.0
5.0
—
—
—
—
5.0
5.0
—
—
—
—
ns
ns
15
15
*
—
—
*
—
—
*
11,12,13
9.10
*
8
8
1,6,16
1,6,16
Toggle Frequency
(See Figure 6)
MC12009 : 5/6
MC12011 : 8/9
MC12013 : 10/11
fmax
2
440
500
500
—
—
—
—
—
—
480
550
550
—
—
—
—
—
—
440
500
500
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
11
11
11
—
—
—
—
—
—
8
8
8
16
16
16
–30°C
+25°C
+85°C
Pulse
Gen.1
{
MHz
*Test inputs sequentially, with Pulse Generator 2 or 3 as indicated connected to input under test, and the voltage indicated applied to the other input(s) of the same type ( i.e., MECL or MTTL).
–30°C
+ 25°C
+ 85°C
{VIHmin
+ 1.03
+ 1.115
+ 1.20
Vdc
{VILmin
+ 0.175
+ 0.200
+ 0.235
Vdc
Figure 3. AC Voltage Waveforms
Pulse
Generator
1
VIHmin
80%
50%
20%
VILmin
t++
Q (Pin 2)
50%
t+ –
50%
Q (Pin 3)
+ In
50%
MTTL
Out
t++
t––
–1.5 V
Figure 4. Setup and Release Time Waveforms
Pulse
50
Generator
%
1 tsetup1
Pulse
Generator
tsetup2
2
Pulse
Generator
+1.5 V
3
Q (Pin 2)
80%
20%
80%
50%
VIHmin
VILmin
VIHmin
20%
VILmin
0V
10%
VEE
90%
Divide by 5 — MC12009
Divide by 8 — MC12011
Divide by 10 — MC12013
MOTOROLA RF/IF DEVICE DATA
Pulse
Generator
1
Pulse
50%
Generator t
rel2
2
Pulse
Generator
3
–1.5 V
Q (Pin 2)
80%
20%
50%
trel1
80%
20%
90%
10%
VIHmin
VILmin
VIHmin
VILmin
0V
VEE
Divide by 6 — MC12009
Divide by 9 — MC12011
Divide by 11 — MC12013
9
MC12009 MC12011 MC12013
Figure 5. AC Test Circuit
Vin
25 µF
50
Pulse
Generator
#1
Vout (Scope Channel B)
VCC = +2.0 V
100
Vin
100
Vin
6
0.1 µF
16
E1
13
50
Pulse
Generator
#2
1
12
E2
11
E3
10
E4
9
E5
15
C
Vout
2
Q
3
Vout
Q
VBB
14
950
Pulse
Generator
#3
50
5
+
4
–
MECL
to
MTTL
Trans–
lator
1950
7
8
0.1 µF
Vin
(Scope Channel A)
CT
VEE = –3.0 V
MC10109 or equiv.
A
All Pulse Generators are EH 137 or equiv.
Pulse Generators 1 and 2:
PRF = 10 MHz
PW = 50% Duty Cycle
t + = t – = 2.0 ± 0.2 ns
Pulse Generator 3:
PRF = 2.0 MHz
PW = 50% Duty Cycle
t + = t – = 5.0 ± 0.5 ns
10
50
VEE = –3.0 V
All resistors are + 1%.
All input and output cables to the scope are equal lengths of 50–ohm coaxial cable.
The 1950–ohm resistor at Pin 7 and the scope termination impedance constitute a 40 : 1 attenuator probe.
CT = 15 pF = total parasitic capacitance which includes probe, wiring, and load capacitance.
Unused output connected to a 50–ohm resistor to ground.
MOTOROLA RF/IF DEVICE DATA
MC12009 MC12011 MC12013
Figure 6. Maximum Frequency Test Circuit
Vout
VCC = +2.0 V
0.1 µF
1
to
Scope
5.0 µF
16
13
E1
Vin
(To Scope)
12
VEE
Q
E2
2
11
E3
10
E4
9
E5
0.1 µF
Sine Wave
Input
Q
15
3
C
1k
14
VBB
0.1 µF
8
0.1 µF
VEE = –3.0 V
Unused output connected to a 50 Ω resistor to ground
DIVIDE BY 6
800 mV
Clock
Input
850 mV typ
Q (Pin 2)
3 Cycles
3 Cycles
DIVIDE BY 9
800 mV
Clock
Input
850 mV typ
5 Cycles
Q (Pin 2)
4 Cycles
DIVIDE BY 11
800 mV
Clock
Input
850 mV typ
Q (Pin 2)
MOTOROLA RF/IF DEVICE DATA
6 Cycles
5 Cycles
11
MC12009 MC12011 MC12013
Figure 7. State Diagram
DIVIDE BY 5/6 (MC12009/MC12509)
Enable = 0
Q1
1
0
0
0
1
1
Q2
1
1
0
0
0
1
Q3
1
1
1
0
0
0
111
011
001
110
100
000
0101
0010
1110
0110
010
101
1000
1100
1010
0000
0111
1111
Enable = 1
Enable = 1
DIVIDE BY 8/9 (MC12011)
Enable = 0
Q1
1
0
0
1
1
0
0
1
1
Q2
1
1
0
0
1
1
0
0
1
Q3
1
1
1
0
0
1
1
0
0
Q4
1
1
1
1
1
0
0
0
0
Enable = 1
0001
1101
1001
0011
Enable = 1.
1011
0100
DIVIDE BY 10/11 (MC12013)
1110
Enable = 0
Q1
1
0
0
0
1
1
0
0
0
1
1
Q2
1
1
0
0
0
1
1
0
0
0
1
Q3
1
1
1
0
0
0
1
1
0
0
0
Q4
1
1
1
1
1
1
0
0
0
0
0
0110
1101
Enable = 1
NOTES:
1001
0101
0010
0001
1011
0000
1010
1000
0100
0011
0111
1100
Enable = 1.
The State of the Enable is important only for the positive
Clock Transition when the counter is in state 1100.
12
1111
MOTOROLA RF/IF DEVICE DATA
MC12009 MC12011 MC12013
APPLICATIONS INFORMATION
The primary application of these devices is as a
high–speed variable modulus prescaler in the divide by N
section of a phase–locked loop synthesizer used as the
local oscillator of two–way radios.
Proper VHF termination techniques should be followed
when the clock is separated from the prescaler by any
appreciable distance.
In their basic form, these devices will divide by 5/6, 8/9,
or 10/11. Division by 5, 8, or 10 occurs when any one or all
of the five gate inputs E1 through E5 are high. Division by
6, 9, or 11 occurs when all inputs E1 through E5 are low.
(Unconnected MTTL inputs are normally high, unconnected MECL inputs are normally low). With the addition
of extra parts, many different division configurations may
be obtained (20/21, 40/41, 50/51, 100/101, etc.) A few of
the many configurations are shown below, only for the
MC12013.
Figure 8. Divide By 10/11 (MC12013)
13
E1
2
12
Q4
E2
11
E3
10
E4
Enable = 0
9
3
E5
Q4
15
C
5
4
+
–
MECL
to
MTTL
Trans–
lator
Q1
1
0
0
0
1
1
0
0
0
1
1
Q2
1
1
0
0
0
1
1
0
0
0
1
Q3
1
1
1
0
0
0
1
1
0
0
0
Q4
1
1
1
1
1
1
0
0
0
0
0
Enable = 1
7
MOTOROLA RF/IF DEVICE DATA
13
MC12009 MC12011 MC12013
Figure 9. Divide By 20/21 (MC12013)
13
E1
COUNT
31
30
28
24
25
27
22
20
16
17
19
14
12
8
9
11
6
4
0
1
3
2
Q4
12
E2
11
E3
10
E4
9
3
E5
15
Q4
C
5
+
4
–
E2 + E3 + E4 + E5 = 0
MECL
to
MTTL
Trans–
lator
7
D
Q
C
Q
Q5
Q1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
Q2
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
Q3
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
Q4
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
Q4
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
E2 + E3 + E4 + E5 = 1
To obtain an MTTL output, connect Pins 5 and 4 to Pins 2 and 3 respectively. Termination
resistors for the MECL outputs are not shown, but are required except for the flip–flop driving
the translator section.
The 20/21 counter may also be built using an MTTL flip–flop by connecting Pins 5 and
4 to Pins 2 and 3 respectively, and driving the MTTL flip–flop with Pin 7. MC12013 inputs
E4 and E5 are used rather than E1. With E1 + E2 + E3 = 0, operation remains as shown.
1/2 MC10131
B
Figure 10. Divide By 40/41 (MC12013)
13
E1
For
For
2
12
Q4
E2
D
Q
C
Q
D
Q
C
Q
B 40 : E4 + E5 = 1
B 41 : E4 + E5 = 0
11
E3
10
E4
9
3
E5
Q4
15
C
5
4
14
+
–
MECL
to
MTTL
Trans–
lator
MC10131
7
Termination resistors for MECL
outputs are not shown, but are
required except for the flip–flop
driving the translator section.
MOTOROLA RF/IF DEVICE DATA
MC12009 MC12011 MC12013
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
J
16 PL
0.25 (0.010)
M
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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MOTOROLA RF/IF DEVICE DATA◊
12009/D
15