ONSEMI NCS6415DWR2G

NCS6415
Bus−Controlled Video
Matrix Switch
Description
The main function of the NCS6415 is to switch 8 video input
sources to the 6 outputs.
Each output can be switched to only one of the inputs, whereas any
single input may be connected to several outputs.
All switching possibilities are controlled through the I2C bus.
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MARKING DIAGRAMS*
20
Features
• Cascadable with another NCS6415 (Internal Address can be changed
•
•
•
•
•
•
•
•
•
by Pin 7 Voltage)
8 Inputs (CVBS, RGB, Chroma, ...)
6 Outputs with Low Impedance Driver
Possibility of Chroma Signal for each Input by Switching off the
Clamp with an External Resistor Bridge
Bus Controlled
6.5 dB Gain between any Input and Output
−45 dB Crosstalk at 5 MHz
Compatible with TEA6415C
Full ESD Protection
These are Pb−Free Devices
20
NCS6415
AWLYYWWG
1
SO−20 WB
DW SUFFIX
CASE 751D
A
WL
YY
WW
G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
20 INPUT8
INPUT1 1
DATA1 2
19 GND
INPUT2 3
18 OUTPUT6
CLOCK 4
17 OUTPUT5
INPUT3 5
16 OUTPUT4
INPUT4 6
15 OUTPUT3
PROG 7
14 OUTPUT2
INPUT5 8
13 OUTPUT1
12 GND
VCC 9
11 INPUT7
INPUT6 10
ORDERING INFORMATION
Package
Shipping †
NCS6415DWG
SO−20
(Pb−Free)
38 Units / Rail
NCS6415DWR2G
SO−20
1000 / Tape & Reel
(Pb−Free)
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
September, 2006 − Rev. 0
1
Publication Order Number:
NCS6415/D
NCS6415
OUTPUT6
OUTPUT4
OUTPUT2
OUTPUT5
OUTPUT3
OUTPUT1
GND
18
INPUT1
1
INPUT2
3
INPUT3
5
INPUT4
6
INPUT5
8
INPUT6
10
INPUT7
11
INPUT8
20
17
16
15
14
13
12
Bus Decoder
2
7
4
9
19
DATA
PROG
CLOCK
VCC
GND
Figure 1. Block Diagram
The main function of the NCS6415 is to switch 8 video
input sources to the 6 outputs.
Each output can be switched to only one of the inputs,
whereas any single input may be connected to several
outputs. The lowest level of each signal is aligned on each
input (bottom of sync pulse for CVBS or Black Level for
RGB signals).
The nominal gain between any input and output is 6 dB.
For Chroma signals, the alignment is switched off by
forcing, with an external 5‘ VDC resistor bridge on the input.
Each input can be used as a normal input or as a Chroma
input (with external resistor bridge). All the switching
possibilities are changed through the I2C bus.
The switches configuration is defined by words of 16 bits:
one word of 16 bits for each output channel.
So, 6 words of 16 bits are necessary to determine the
starting configuration upon power−on (power supply: 0 to
10 V). But a new configuration needs only the words of the
changed output channels. Driving a 75 W load requires an
external transistor.
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2
NCS6415
Table 1. ATTRIBUTES
Characteristics
ESD
Value
Human Body Model
Machine Model
4 kV
400 V
Moisture Sensitivity (Note 1)
Flammability Rating
Level 3
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in.
1. For additional information, see Application Note AND8003/D
Table 2. MAXIMUM RATINGS
Parameter
Power Supply Voltage
Symbol
Rating
Unit
VCC
12
V
Operating Temperature Range
TA
0 to +70
°C
Storage Temperature Range
Tstg
−60 to +150
°C
Thermal Resistance, Junction−to−Air
SO−20
°C/W
qJA
30 to 35
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. DC & AC Characteristics (TA = 25°C, VCC = 10 V, RL = 10 kW, CL = 3 pF)
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
8
10
11
V
ICC
Power Supply Current (No Load)
20
30
40
mA
1.5
2
VPP
1
3
mA
3.6
3.9
V
DC Level Shift (0°C to 70°C)
5
100
mV
RIN
Input Resistance
1
MW
CIN
Input Capacitance
2
pF
Dynamic (VIN = 2.5 VPP)
5
VPP
Output Impedance (Note 2)
25
50
W
7
dB
INPUTS
Signal Amplitude (CVBS signal) (Note 2)
Input Current (per output connected, VIN = 5 VDC)
DC Level
3.3
OUTPUTS
AV
Gain (Note 2)
6
6.5
BW
Bandwidth (Note 2)
−1 dB Attenuation
−3 dB Attenuation
7
15
20
0.1 dB Gain Flatness (Note 2)
6
MHz
Crosstalk
f = 3.58 MHz
f = 5 MHz
DC Level
I2C
MHz
−48
−45
dB
2.4
2.75
3.1
V
1.5
2
3
V
BUS INPUT: DATA, CLOCK AND PROG
Threshold Voltage
2. Guaranteed by design and/or characterization.
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3
NCS6415
Table 4. I2C Bus Characteristics
Symbol
Parameter
Test Conditions
Min
Max
Unit
SCL
VIL
Low Level Input Voltage
−0.3
+1.5
V
VIH
High Level Input Voltage
3.0
VCC +0.5
V
ILI
Input Leakage Current
−10
+10
mA
fSCL
Clock Frequency (Note 3)
0
100
kHz
tR
Input Rise Time (Note 3)
1.5 V to 3 V
1000
ns
tF
Input Fall Time (Note 3)
3 V to 1.5 V
300
ns
CI
Input Capacitance (Note 3)
10
pF
VI = 0 to VCC
SDA
VIL
Low Level Input Voltage
−0.3
+1.5
V
VIH
High Level Input Voltage
3.0
VCC +0.5
V
ILI
Input Leakage Current
−10
+10
mA
CI
Input Capacitance (Note 3)
10
pF
tR
Input Rise Time (Note 3)
1.5 V to 3 V
1000
ns
tF
Input Fall Time (Note 3)
3 V to 1.5 V
300
ns
VOL
Low Level Output Voltage
IOL = 3 mA
0.4
V
tF
Output Fall Time (Note 3)
3V to 1.5 V
250
ns
CL
Load Capacitance
400
pF
VI = 0 to VCC
TIMING
tLOW
Clock Low Period (Note 4)
4.7
ms
tHIGH
Clock High Period (Note 4)
4.0
ms
tSU,DAT
Data Setup Time (Note 4)
250
ns
tHD,DAT
Data Hold Time (Note 4)
0
tSU,STO
Setup Time from Clock High to Stop (Note 4)
4.0
ms
tBUF
Start Setup Time following a Stop (Note 4)
4.7
ms
tHD,STA
Start Hold Time (Note 4)
4.0
ms
tSU,STA
Start Setup Time following Clock Low to High Transition
(Note 4)
4.7
ms
3. Guaranteed by design and/or characterization.
4. Functionality guaranteed by design and/or characterization.
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4
340
ns
NCS6415
I2C Bus Selections
The I2C chip address is defined by the first byte. The second byte defines the input/output configuration.
Table 5. CHIP ADDRESS BYTE (1ST BYTE OF TRANSMISSION)
HEX
BINARY
86
1000 0110
When PROG pin is connected to Ground
0000 0110
When PROG pin is connected to VCC
06
Input/Output Selection Byte
(2nd
Comment
byte of transmission)
Table 6. I2C BUS OUTPUT SELECTIONS
Output Address (MSB)
Input Address (LSB)
00000
XXX
Pin 18
Selected Output
00100
XXX
Pin 14
00010
XXX
Pin 16
00110
−
Not Used
00001
XXX
Pin 17
00101
XXX
Pin 13
00011
XXX
Pin 15
00111
−
Not Used
Output is selected by the 5 MSBs.
Table 7. I2C BUS INPUT SELECTIONS
Output Address (MSB)
Input Address (LSB)
Selected Input
00XXX
000
Pin 5
00XXX
100
Pin 8
00XXX
010
Pin 3
00XXX
110
Pin 20
00XXX
001
Pin 6
00XXX
101
Pin 10
00XXX
011
Pin 1
00XXX
111
Pin 11
Input is selected by the 3 LSBs.
Example: 0010 0101 (Binary) or 25 (Hex) connects Pin 10 (input) to Pin 14 (output)
SDA
tBUF
tSU.DAT
tLOW
SCL
tR
tHD.STA
tHD.DAT tHIGH
SDA
tSU.STA
Figure 2. I2C Timing Diagram
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5
tF
tSU.STO
NCS6415
VCC
VCC
14 kW
x3
7 kW
0.36 VCC
8 NPN
Transistors
Pins 1, 3,
5, 6, 8, 10,
11 and 20
Pins 1, 3,
5, 6, 8, 10,
11 and 20
11 kW
Output
6 Times
Figure 3. Input Configuration
Figure 4. Output Configuration
Pins 2, 4, and 7
VREF
250 mA
VCC
To I2L
Part
20 kW
*
150 W
20 kW
ACK
150 W
*For Pin 2
(Data Only)
Figure 5. Bus I/O Configuration
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6
Figure 6. VCC Pin Configuration
NCS6415
USING A SECOND NCS6415
The programming input pin (PROG) allows two
NCS6415 circuits to operate in parallel and to select them
independently through the I2C bus by modifying the address
byte. Consequently, the switching capabilities are doubled,
or IC1 and IC2 can be cascaded (see Figure 7).
NCS6415
PROG
Logical “0”
IC1
MCU
Video Inputs
Video Outputs
NCS6415
PROG
Logical “1”
IC2
Video Inputs
Video Outputs
Figure 7. Cascaded NCS6415
TYPICAL APPLICATION DIAGRAM
NCS6415 is suited for single supply system, running on
broadcast studio quality signals. The layout is not as critical
a single +10 V supply. The high quality of the output stage
to the design and it can be easily realized on a single sided
and excellent linearity provides video signal comparable to
board.
Additional Video Inputs
S TV
receiver
circuit
Outpu 1
1 Input 1
3
5
6
8
10
11
20 Input 8
Additional Video Outputs
Clock
Prog
Data
Bus
Decoder
HDTV
Receiver
circuit
Screen
VCR
NCS6415
Security
Video
Interface
Output 6
18 17 16 15 14 13
VCC
Microcontroller
Figure 8. Typical Application Diagram
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7
8
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Figure 9. Typical Application Circuit
VCC = +10V
Input 6
Input 5
Input 4
Input 3
SCL
Input 2
SDA
Input 1
75W
R9
75W
R8
75W
R5
75W
R3
75W
R1
C10
10mF
R6
75W
R2
R4
C5
100nF
C8
100nF
C6
100nF
100nF
100W
C3
100nF
100W
C2
100nF
C1
C9
100nF
10
9
8
7
6
5
4
3
2
1
INPUT6
VCC
INPUT5
PROG
INPUT4
INPUT3
CLOCK
INPUT2
DATA
INPUT1
INPUT7
GND
OUTPUT1
OUTPUT2
OUTPUT3
OUTPUT4
OUTPUT5
OUTPUT6
GND
INPUT8
11
12
13
14
15
16
17
18
19
20
C11
100nF
C12
100nF
R11
75W
75W
R42
Input 7
R13
10kW
Input 8
R12
470W
R14
10kW
R16
68W
+10V
R32
10kW
R37
10kW
R38
470W
+10V
R27
10kW
R33
470W
R39
10kW
R40
75W
R41
68W
R15
75W
R17
10kW
470W
R21
R18 68W
+10V
R19
10kW
R20
75W
R22
10kW
R23
470W
R28
470W
R35
10kW
R36
68W
R35
75W
+10V
R24
10kW
R25
75W
R26
68W
+10V
R30
10kW
R30
75W
R31
68W
+10V
Output 1
Output 2
Output 3
Output 4
Output 5
Output 6
NCS6415
NCS6415
PACKAGE DIMENSIONS
SO−20 WB
CASE 751D−05
ISSUE G
q
A
20
X 45 _
h
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
B
0.25
M
T A
S
B
S
L
A
18X
e
A1
SEATING
PLANE
C
T
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
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NCS6415/D