MTB30P06V Preferred Device Power MOSFET 30 Amps, 60 Volts P−Channel D2PAK This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. http://onsemi.com 30 AMPERES, 60 VOLTS RDS(on) = 80 mW P−Channel D Features • Avalanche Energy Specified • IDSS and VDS(on) Specified at Elevated Temperature • Pb−Free Packages are Available G S MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc Drain−to−Gate Voltage (RGS = 1.0 MW) VDGR 60 Vdc Gate−to−Source Voltage − Continuous − Non−repetitive (tp ≤ 10 ms) VGS VGSM ± 15 ± 25 Vdc Vpk ID ID 30 19 105 Adc 125 0.83 3.0 W W/°C TJ, Tstg −55 to 175 °C EAS 450 mJ Drain Current − Continuous @ 25°C − Continuous @ 100°C − Single Pulse (tp ≤ 10 ms) Total Power Dissipation @ 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 1) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 30 Apk, L = 1.0 mH, RG = 25 W) Thermal Resistance − Junction−to−Case − Junction−to−Ambient − Junction−to−Ambient (Note 1) Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds IDM PD D2PAK CASE 418B STYLE 2 1 MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain MTB 30P06VG AYWW Apk 1 Gate A Y WW G 3 2 Source Drain = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION °C/W RqJC RqJA RqJA 1.2 62.5 50 TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to an FR4 board using the minimum recommended pad size. Package Shipping † MTB30P06V D2PAK 50 Units/Rail MTB30P06VG D2PAK 50 Units/Rail Device (Pb−Free) MTB30P06VT4 D2PAK 800/Tape & Reel MTB30P06VT4G D2PAK 800/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Preferred devices are recommended choices for future use and best overall value. © Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev.4 1 Publication Order Number: MTB30P06V/D MTB30P06V ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 60 − − 62 − − Vdc mV/°C − − − − 10 100 − − 100 nAdc 2.0 − 2.6 5.3 4.0 − Vdc mV/°C − 0.067 0.08 W − − 2.0 − 2.9 2.8 5.0 7.9 − Ciss − 1562 2190 Coss − 524 730 Crss − 154 310 td(on) − 14.7 30 tr − 25.9 50 td(off) − 98 200 tf − 52.4 100 QT − 54 80 Q1 − 9.0 − Q2 − 26 − Q3 − 20 − − − 2.3 1.9 3.0 − trr − 175 − ta − 107 − tb − 68 − QRR − 0.965 − − 3.5 4.5 − − 7.5 − OFF CHARACTERISTICS Drain−Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) IGSS mAdc ON CHARACTERISTICS (Note 2) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 15 Adc) RDS(on) Drain−Source On−Voltage (VGS = 10 Vdc, ID = 30 Adc) (VGS = 10 Vdc, ID = 15 Adc, TJ = 150°C) VDS(on) Forward Transconductance (VDS = 8.3 Vdc, ID = 15 Adc) Vdc gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 30 Vdc, ID = 30 Adc, VGS = 10 Vdc, RG = 9.1 W) Fall Time Gate Charge (See Figure 8) (VDS = 48 Vdc, ID = 30 Adc, VGS = 10 Vdc) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 30 Adc, VGS = 0 Vdc) (IS = 30 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time (IS = 30 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge VSD Vdc ns mC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS 2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 nH nH MTB30P06V TYPICAL ELECTRICAL CHARACTERISTICS 60 60 TJ = 25°C I D , DRAIN CURRENT (AMPS) 9V I D , DRAIN CURRENT (AMPS) VGS = 10V 50 7V 40 30 6V 20 5V 10 0 25°C 40 30 TJ = −55°C 20 0 12 2 4 6 8 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0 1 0.12 VGS = 10 V TJ = 100°C 0.08 25°C 0.06 − 55°C 0.04 0.02 0 0 10 20 30 40 ID, DRAIN CURRENT (AMPS) 50 60 TJ = 25°C VGS = 10 V 0.07 15 V 0.06 0.05 0.04 0 10 20 30 40 ID, DRAIN CURRENT (AMPS) 50 60 100 VGS = 0 V VGS = 10 V ID = 15 A TJ = 125°C I DSS , LEAKAGE (nA) R DS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 8 Figure 4. On−Resistance versus Drain Current and Gate Voltage 1.8 1.4 7 0.08 Figure 3. On−Resistance versus Drain Current and Temperature 1.6 2 3 4 5 6 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 2. Transfer Characteristics RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) Figure 1. On−Region Characteristics 0.1 100°C 50 10 4V 0 VDS ≥ 10 V 8V 1.2 1 0.8 0.6 10 100°C 0.4 0.2 0 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 1 175 0 Figure 5. On−Resistance Variation with Temperature 50 60 10 20 30 40 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 70 MTB30P06V POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6000 Ciss C, CAPACITANCE (pF) 5000 4000 VDS = 0 V VGS = 0 V TJ = 25°C Crss 3000 Ciss 2000 Coss 1000 Crss 0 10 0 5 VGS 5 10 15 20 25 VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 30 9 VGS QT 27 24 8 Q2 Q1 7 21 6 18 5 15 4 12 9 3 2 VDS 1 0 TJ = 25°C ID = 30 A Q3 0 10 20 30 50 40 6 3 0 60 1000 t, TIME (ns) 10 VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) MTB30P06V TJ = 25°C ID = 30 A VDD = 30 V VGS = 10 V 100 td(off) tf tr td(on) 10 1 1 10 Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 DRAIN−TO−SOURCE DIODE CHARACTERISTICS 30 TJ = 25°C VGS = 0 V IS , SOURCE CURRENT (AMPS) 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance−General Data and Its Use” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. http://onsemi.com 5 MTB30P06V SAFE OPERATING AREA VGS = 20 V SINGLE PULSE TC = 25°C 450 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 1000 100 10 ms 100 ms 10 1 ms 10 ms dc ID = 30 A 400 350 300 250 200 150 100 50 0 1 0.1 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 25 100 50 75 100 125 150 175 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature D = 0.5 0.2 0.1 0.10 P(pk) 0.05 0.02 0.01 t1 SINGLE PULSE 0.01 1.0E−05 t2 DUTY CYCLE, D = t1/t2 1.0E−04 1.0E−03 1.0E−02 RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 1.0E−01 1.0E+00 1.0E+01 t, TIME (s) Figure 13. Thermal Response 3 PD, POWER DISSIPATION (WATTS) r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.00 di/dt IS trr ta tb TIME 0.25 IS tp 2.5 2.0 1.5 1 0.5 0 IS RqJA = 50°C/W Board material = 0.065 mil FR−4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 9 450 mils x 350 mils 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (°C) Figure 15. D2PAK Power Derating Curve Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6 175 MTB30P06V PACKAGE DIMENSIONS D2PAK 3 CASE 418B−04 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B−01 THRU 418B−03 OBSOLETE, NEW STANDARD 418B−04. C E V W −B− 4 DIM A B C D E F G H J K L M N P R S V A 1 2 S 3 −T− SEATING PLANE K W J G D 3 PL 0.13 (0.005) VARIABLE CONFIGURATION ZONE H M T B M N R M STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN P U L L M L M F F F VIEW W−W 1 VIEW W−W 2 VIEW W−W 3 SOLDERING FOOTPRINT* 8.38 0.33 1.016 0.04 10.66 0.42 5.08 0.20 3.05 0.12 17.02 0.67 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40 MTB30P06V ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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