TI OPA830ID

OPA830
SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
Low-Power, Single-Supply, Wideband
Operational Amplifier
FEATURES
DESCRIPTION
D HIGH BANDWIDTH:
D
D
D
D
D
D
D
250MHz (G = +1)
110MHz (G = +2)
LOW SUPPLY CURRENT: 3.9mA (VS = +5V)
FLEXIBLE SUPPLY RANGE:
±1.4V to ±5.5V Dual Supply
+2.8V to +11V Single Supply
INPUT RANGE INCLUDES GROUND ON
SINGLE SUPPLY
4.88V OUTPUT SWING ON +5V SUPPLY
HIGH SLEW RATE: 550V/µs
LOW INPUT VOLTAGE NOISE: 9.2nV/√Hz
Pb-FREE SOT23 PACKAGE
APPLICATIONS
D SINGLE-SUPPLY ANALOG-TO-DIGITAL
D
D
D
D
D
RELATED PRODUCTS
DESCRIPTION
+3V
+3V
374Ω
VIN
100Ω
THS1040
10−Bit
40MSPS
OPA830
Low distortion operation is ensured by the high gain
bandwidth product (110MHz) and slew rate (550V/µs), making
the OPA830 an ideal input buffer stage to 3V and 5V CMOS
ADCs. Unlike other low-power, single-supply amplifiers,
distortion performance improves as the signal swing is
decreased. A low 9.2nV/√Hz input voltage noise supports
wide dynamic range operation.
The OPA830 is available in an industry-standard SO-8
package. The OPA830 is also available in an ultra-small
SOT23-5 package. For fixed-gain line driver applications,
consider the OPA832.
CONVERTER (ADC) INPUT BUFFERS
SINGLE-SUPPLY VIDEO LINE DRIVERS
CCD IMAGING CHANNELS
LOW-POWER ULTRASOUND
PLL INTEGRATORS
PORTABLE CONSUMER ELECTRONICS
2.26kΩ
The OPA830 is a low-power, single-supply, wideband,
voltage-feedback amplifier designed to operate on a single
+3V or +5V supply. Operation on ±5V or +10V supplies is also
supported. The input range extends below the negative
supply and to within 1.7V of the positive supply. Using
complementary common-emitter outputs provides an output
swing to within 25mV of either supply while driving 150Ω. High
output drive current (±80mA) and low differential gain and
phase errors also make them ideal for single-supply
consumer video products.
Rail-to-Rail
Rail-to-Rail Fixed Gain
General-Purpose
(1800V/µs slew rate)
Low-Noise,
High DC Precision
SINGLES
DUALS
TRIPLES
QUADS
—
OPA832
OPA2830
OPA2832
—
OPA3832
OPA4830
—
OPA690
OPA2690
OPA3690
—
OPA820
OPA2822
—
OPA4820
22pF
562Ω
750Ω
DC-Coupled, +3V ADC Driver
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright  2004−2008, Texas Instruments Incorporated
! ! www.ti.com
"#$
www.ti.com
SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12VDC
Internal Power Dissipation . . . . . . . . . . . . . . See Thermal Analysis
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2.5V
Input Voltage Range (Single Supply) . . . . . . . −0.5V to +VS + 0.3V
Storage Temperature Range: D, DBV . . . . . . . . . −65°C to +125°C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
ESD Rating:
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . 2000V
Charge Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . 1500V
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
OPA830
SO-8 Surface-Mount
D
−40°C to +85°C
OPA830
OPA830ID
Rails, 100
″
″
″
″
″
OPA830IDR
Tape and Reel, 2500
OPA830
SOT23-5
DBV
−40°C to +85°C
A72
OPA830IDBVT
Tape and Reel, 250
″
″
″
″
″
OPA830IDBVR
Tape and Reel, 3000
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
PIN CONFIGURATIONS
NC
1
8
NC
Inverting Input
2
7
+VS
Noninverting Input
3
6
Output
−VS
4
5
NC
Output
1
−VS
2
Noninverting Input
3
5
+VS
4
Inverting Input
3
1
A72
2
SO−8
NC = No Connection
4
5
SOT23−5
Pin Orientation/Package Marking
2
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 3).
OPA830ID, IDBV
PARAMETER
AC PERFORMANCE (see Figure 3)
Small-Signal Bandwidth
Gain-Bandwidth Product
Peaking at a Gain of +1
Slew Rate
Rise Time
Fall Time
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Input Current Noise
NTSC Differential Gain
NTSC Differential Phase
DC PERFORMANCE(4)
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
INPUT
Negative Input Voltage(5)
Positive Input Voltage(5)
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential Mode
Common-Mode
OUTPUT
Output Voltage Swing
Current Output, Sinking and Sourcing
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power-Supply Rejection Ratio (+PSRR)
THERMAL CHARACTERISTICS
Specification: ID, IDBV
Thermal Resistance, qJA
D
SO-8
DBV
SOT23-5
TYP
MIN/MAX OVER TEMPERATURE
CONDITIONS
+25°C
+25°C(1)
0°C to
70°C(2)
−40°C to
+85°C(2)
G = +1, VO ≤ 0.2VPP
G = +2, VO ≤ 0.2VPP
G = +5, VO ≤ 0.2VPP
G = +10, VO ≤ 0.2VPP
G ≥ +10
VO ≤ 0.2VPP
G = +2, 2V Step
0.5V Step
0.5V Step
G = +2, 1V Step
VO = 2VPP, f = 5MHz
RL = 150Ω
RL ≥ 500Ω
RL = 150Ω
RL ≥ 500Ω
f > 1MHz
f > 1MHz
310
120
25
11
110
6
600
3.3
3.5
42
70
18
8
85
68
16
7
82
65
15
6
80
280
5.8
5.9
63
270
5.85
5.95
65
260
5.9
6.0
66
−67
−71
−60
−77
9.5
3.7
0.07
0.17
−59
−62
−50
−65
10.5
4.7
−57
−61
−49
−62
11.0
5.2
74
±1.5
—
+5
66
±7
UNITS
MIN/
MAX
TEST
LEVEL
(3)
MHz
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
ns
typ
min
min
min
min
typ
min
max
max
max
C
B
B
B
B
C
B
B
B
B
−56
−60
−48
−59
11.5
5.7
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
%
°
max
max
max
max
max
max
typ
typ
B
B
B
B
B
B
C
C
65
±8.1
±25
+12
±12
±1.2
±5
64
±8.6
±25
+13
±12
±1.4
±5
dB
mV
µV/°C
µA
nA/°C
µA
nA/°C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
−5.3
3.0
74
−5.2
2.9
72
V
V
dB
max
min
min
A
A
A
kΩ  pF
kΩ  pF
typ
typ
C
C
V
V
mA
mA
Ω
min
min
min
typ
typ
A
A
A
C
C
V
V
mA
mA
dB
typ
max
max
min
min
C
A
A
A
A
−40 to +85
°C
typ
C
125
150
°C/W
°C/W
typ
typ
C
C
RL = 150Ω
VCM = 0V
VCM = 0V
Input-Referred
+10
±0.1
—
±1
−5.5
3.2
80
−5.4
3.1
76
10 2.1
400 1.2
G = +2, RL = 1kΩ to GND
G = +2, RL = 150Ω to GND
Output Shorted to Ground
G = +2, f ≤ 100kHz
±4.88
±4.64
±85
150
0.06
±4.86
±4.60
±65
±4.85
±4.58
±60
±4.84
±4.56
±55
±5.5
4.7
4.0
61
±5.5
5.3
3.6
60
±5.5
5.9
3.3
59
±1.4
VS = ±5V
VS = ±5V
Input-Referred
4.25
4.25
66
(1) Junction temperature = ambient for +25°C specifications.
(2) Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over temperature specifications.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical
value only for information.
(4) Current is considered positive out of pin.
(5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.
3
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
OPA830ID, IDBV
PARAMETER
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth
Gain-Bandwidth Product
Peaking at a Gain of +1
Slew Rate
Rise Time
Fall Time
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Input Current Noise
NTSC Differential Gain
NTSC Differential Phase
DC PERFORMANCE(4)
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
INPUT
Least Positive Input Voltage(5)
Most Positive Input Voltage(5)
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
Current Output, Sourcing and Sinking
Short-Circuit Output Current
Closed-Loop Output Impedance
POWER SUPPLY
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power-Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: ID, IDBV
Thermal Resistance, qJA
D
SO-8
DBV
SOT23-5
(1)
TYP
MIN/MAX OVER TEMPERATURE
CONDITIONS
+25°C
+25°C(1)
0°C to
70°C(2)
−40°C to
+85°C(2)
G = +1, VO ≤ 0.2VPP
G = +2, VO ≤ 0.2VPP
G = +5, VO ≤ 0.2VPP
G = +10, VO ≤ 0.2VPP
G ≥ +10
VO ≤ 0.2VPP
G = +2, 2V Step
0.5V Step
0.5V Step
G = +2, 1V Step
VO = 2VPP, f = 5MHz
RL = 150Ω
RL ≥ 500Ω
RL = 150Ω
RL ≥ 500Ω
f > 1MHz
f > 1MHz
250
110
24
11
110
5
550
3.3
3.3
43
72
17
8
84
70
16
7
80
68
15
6
79
280
5.7
5.7
64
270
5.8
5.8
66
260
5.9
5.9
67
−62
−64
−58
−84
9.2
3.5
0.08
0.09
−55
−58
−50
−66
10.2
4.5
−54
−57
−49
−63
10.7
5.0
72
±0.5
—
+5
66
±5.0
±0.1
—
±0.8
−0.5
3.2
80
−0.4
3.1
76
TEST
LEVEL
UNITS
MIN/
MAX
MHz
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
ns
typ
min
min
min
min
typ
min
max
max
max
C
B
B
B
B
C
B
B
B
B
−53
−56
−48
−60
11.2
5.5
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
%
°
max
max
max
max
max
max
typ
typ
B
B
B
B
B
B
C
C
65
±6.0
±20
+12
±12
±1
±5
64
±6.5
±20
+13
±12
±1.2
±5
dB
mV
µV/°C
µA
nA/°C
µA
nA/°C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
−0.3
3.0
74
−0.2
2.9
72
V
V
dB
max
min
min
A
A
A
kΩ  pF
kΩ  pF
typ
typ
C
C
V
V
V
V
mA
mA
Ω
max
max
min
min
min
typ
typ
A
A
A
A
A
C
C
V
V
mA
mA
dB
typ
max
max
min
min
C
A
A
A
A
−40 to +85
°C
typ
C
125
150
°C/W
°C/W
typ
typ
C
C
(3)
RL = 150Ω
VCM = 2.5V
VCM = 2.5V
Input-Referred
+10
10 2.1
4001.2
G = +5, RL = 1kΩ to 2.5V
G = +5, RL = 150Ω to 2.5V
G = +5, RL = 1kΩ to 2.5V
G = +5, RL = 150Ω to 2.5V
Output Shorted to Either Supply
G = +2, f ≤ 100kHz
0.09
0.21
4.91
4.78
±80
140
0.06
0.11
0.24
4.89
4.75
±60
0.12
0.25
4.88
4.73
±55
0.13
0.26
4.87
4.72
±52
+11
4.1
3.7
61
+11
4.8
3.4
60
+11
5.5
3.1
59
+2.8
VS = +5V
VS = +5V
Input-Referred
3.9
3.9
66
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over temperature.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only
for information.
(4) Current considered positive out of pin.
(5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.
(2)
4
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
ELECTRICAL CHARACTERISTICS: VS = +3V
Boldface limits are tested at +25°C.
At TA = 25°C, G = +2, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 2).
OPA830ID, IDBV
TYP
PARAMETER
AC PERFORMANCE (see Figure 2)
Small-Signal Bandwidth
Gain-Bandwidth Product
Slew Rate
Rise Time
Fall Time
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Input Current Noise
DC PERFORMANCE(4)
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
Current Output, Sourcing
Current Output, Sinking
Short-Circuit Output Current
Closed-Loop Output Impedance
POWER SUPPLY
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power-Supply Rejection Ratio (PSRR)
UNITS
MIN/
MAX
TEST
LEVEL
(3)
CONDITIONS
+25°C
+25°C(1)
0°C to
70°C(2)
G = +2, VO ≤ 0.2VPP
G = +5, VO ≤ 0.2VPP
G = +10, VO ≤ 0.2VPP
G ≥ +10
1V Step
0.5V Step
0.5V Step
1V Step
VO = 1VPP, f = 5MHz
RL = 150Ω
RL ≥ 500Ω
RL = 150Ω
RL ≥ 500Ω
f > 1MHz
f > 1MHz
100
22
10
100
225
3.3
3.3
45
72
17
8
80
140
5.5
5.5
72
68
16
7
76
110
5.6
5.6
87
MHz
MHz
MHz
MHz
V/µs
ns
ns
ns
min
min
min
min
min
max
max
max
B
B
B
B
B
B
B
B
−67
−67
−66
−77
9.2
3.5
−61
−61
−59
−59
10.2
4.5
−59
−59
−58
−58
10.7
5.0
dBc
dBc
dBc
dBc
max
max
max
max
nV/√Hz
pA/√Hz
max
max
B
B
B
B
B
B
72
±1.5
—
+5
66
±7
65
±8.1
±25
+12
±12
±1.2
±5
dB
mV
µV/°C
µA
nA/°C
µA
nA/°C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
−0.27
1.0
73
V
V
dB
max
min
min
A
A
A
kΩ  pF
kΩ  pF
typ
typ
C
C
V
V
V
V
mA
mA
mA
Ω
max
max
min
min
min
min
typ
typ
A
A
A
A
A
A
C
C
V
V
mA
mA
dB
min
max
max
min
min
B
A
A
A
A
−40 to +85
°C
typ
C
125
150
°C/W
°C/W
typ
typ
C
C
VCM = 1.0V
VCM = 1.0V
INPUT
Least Positive Input Voltage(5)
Most Positive Input Voltage(5)
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential-Mode
Common-Mode
MIN/MAX OVER
TEMPERATURE
Input-Referred
+10
±0.1
—
±1
−0.45
1.2
80
−0.4
1.1
75
10 2.1
4001.2
G = +5, RL = 1kΩ to 1.5V
G = +5, RL = 150Ω to 1.5V
G = +5, RL = 1kΩ to 1.5V
G = +5, RL = 150Ω to 1.5V
Output Shorted to Either Supply
See Figure 2, f < 100kHz
0.08
0.17
2.91
2.82
30
30
45
0.06
0.11
0.39
2.88
2.74
20
20
0.125
0.40
2.85
2.70
18
18
+11
4.0
3.3
60
+11
4.7
3.1
58
+2.8
VS = +3V
VS = +3V
Input-Referred
THERMAL CHARACTERISTICS
Specification: ID, IDBV
Thermal Resistance, qJA
D
SO-8
DBV
SOT23-5
3.7
3.7
64
(1) Junction temperature = ambient for +25°C specifications.
(2) Junction temperature = ambient at low temperature limits; junction temperature = ambient +5°C at high temperature limit for over temperature.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only
for information.
(4) Current considered positive out of pin.
(5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.
5
"#$
www.ti.com
SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 3).
INVERTING SMALL−SIGNAL FREQUENCY RESPONSE
NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE
3
6
0
0
Normalized Gain (dB)
Normalized Gain (dB)
G = −2
G = +1
RF = 0Ω
3
G = +2
−3
G = +5
−6
−9
G = +10
−12
VO = 0.2VPP
RL = 150Ω
See Figure 3
−15
−18
1
G = −1
−3
−6
G = −5
−9
G = −10
−12
VO = 0.2VPP
RL = 150Ω
−15
−18
10
100
600
1
10
100
400
Frequency (MHz)
Frequency (MHz)
NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE
INVERTING LARGE−SIGNAL FREQUENCY RESPONSE
9
3
6
0
3
−3
VO = 2VPP
Gain (dB)
0
VO = 1VPP
−3
VO = 4VPP
−6
G = +2V/V
RL = 150Ω
See Figure 3
−9
−18
100
500
10
Frequency (MHz)
1.0
0.1
0
0.5
Small−Signal ± 100mV
Left Scale
0
−0.1
−0.5
−0.2
−1.0
−0.3
−1.5
−0.4
−2.0
Time (10ns/div)
6
1.5
Small−Signal Output Voltage (100mV/div)
0.2
Large−Signal Output Voltage (500mV/div)
Small−Signal Output Voltage (100mV/div)
0.3
Large−Signal ± 1V
Right Scale
400
INVERTING PULSE RESPONSE
2.0
G = +2V/V
See Figure 3
100
Frequency (MHz)
NONINVERTING PULSE RESPONSE
0.4
VO = 4VPP
G = −1V/V
RL = 150Ω
−15
VO = 0.5VPP
10
−9
−12
VO = 2VPP
−12
VO = 0.5VPP
−6
0.4
2.0
G = −1V/V
0.3
1.5
0.2
1.0
0.1
0
0.5
Small−Signal ± 100mV
Left Scale
−0.1
−0.2
−0.3
0
−0.5
Large−Signal ± 1V
Right Scale
−0.4
−1.0
−1.5
−2.0
Time (10ns/div)
Large−Signal Output Voltage (500mV/div)
Gain (dB)
VO = 1VPP
"#$
www.ti.com
SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 3).
5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
HARMONIC DISTORTION vs LOAD RESISTANCE
−40
−60
3rd−Harmonic
−65
−70
2nd−Harmonic
−75
−80
−50
−55
Input Limited for VCM = 0V
−60
−65
2nd−Harmonic
−70
−75
−80
3rd−Harmonic
−85
−85
100
−90
2.0
1000
2.5
3.0
Resistance (Ω )
−55
−70
−75
2nd−Harmonic
−80
3rd−Harmonic
−85
−90
5.0
5.5
−60
VO = 2VPP
G = +2V/V
See Figure 3
−65
2nd−Harmonic
RL = 500Ω
−70
−75
−80
−85
−90
3rd−Harmonic
RL = 150Ω
2nd−Harmonic
RL = 150Ω
3rd−Harmonic
RL = 500Ω
−95
−100
−95
−105
0.1
1
10
0.1
1
Output Voltage Swing (VPP)
TWO−TONE, 3RD−ORDER INTERMODULATION SPURIOUS
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
95
6.0
90
5.5
50Ω
PO
OPA830
20MHz
500Ω
−50
750Ω
−55
−60
750Ω
10MHz
−65
−70
−75
5MHz
−80
85
80
4.5
75
4.0
Supply Current
Right Scale
50
−85
−90
−26
−20
−14
−8
−2
Single−Tone Load Power (2dBm/div)
6
5.0
Source/Sink Output Current
Left Scale
25
−50
3.5
Supply Current (4mA/div)
PI
Output Current (50mA/div)
−45
10
Frequency (MHz)
−40
3rd−Order Spurious Level (dBc)
4.5
HARMONIC DISTORTION vs FREQUENCY
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
−65
4.0
−50
f = 5MHz
RL = 500Ω
G = +2V/V
See Figure 3
−60
3.5
Supply Voltage (±VS)
HARMONIC DISTORTION vs OUTPUT VOLTAGE
−55
VO = 2VPP
RL = 500Ω
G = +2V/V
See Figure 3
−45
f = 5MHz
VO = 2VPP
G = +2V/V
See Figure 3
−55
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
−50
3.0
−25
0
25
50
75
100
125
Ambient Temperature (_ C)
7
"#$
www.ti.com
SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 3).
RECOMMENDED RS vs CAPACITIVE LOAD
120
CL = 10pF
7
6
5
100
90
CL = 1000pF
4
80
3
2
1
50Ω
VO
OPA830
CL
−1
750Ω
60
40
1kΩ(1)
750Ω
−2
70
50
RS
VI
0
0dB Peaking Targeted
110
CL = 100pF
RS (Ω)
Normalized Gain to Capacitive Load (dB)
FREQUENCY RESPONSE vs CAPACITIVE LOAD
8
30
NOTE: (1) 1kΩ is optional.
20
−3
10
1
10
100
200
1
10
Frequency (MHz)
5
5
4
4
3
3
2
2
1
G = +5V/V
VS = ±5V
−2
−3
−3
−4
−4
−5
−5
10
100
Resistance (Ω )
1k
1W Internal
Power Lim it
Output
Current Lim it
RL = 500Ω
RL = 50Ω
RL = 100Ω
0
−1
−2
−6
8
VO (V)
Output Voltage (V)
6
0
−1
1k
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
OUTPUT SWING vs LOAD RESISTANCE
6
1
100
Capacitive Load (pF)
Output
1W Internal
Current Limit
P ower Limit
−6
−160
−120
−80
−40
0
IO (mA)
40
80
120
160
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = ±5V, Differential Configuration
At TA = 25°C, GD = +2, RF = 604Ω, and RL = 500Ω, unless otherwise noted.
DIFFERENTIAL SMALL−SIGNAL FREQUENCY RESPONSE
+5V
3
GD = 1
OPA830
Normalized Gain (dB)
0
−5V
6 0 4Ω
RG
6 0 4Ω
VI
RL
50 0 Ω
+5V
VO
RG
−6
GD = 5
−9
G D = 10
−12
OPA830
−5V
GD = 2
−3
GD =
−15
604Ω
RG
VO = 200mVPP
RL = 500Ω
1
10
100
200
Frequency (MHz)
DIFFERENTIAL LARGE−SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
−45
9
VO = 5VPP
Gain (dB)
3
0
VO = 2VPP
−3
VO = 1VPP
−6
GD = 2
RL = 500Ω
−9
Harmonic Distortion (dBc)
−50
6
VO = 200mVPP
1
10
100
−55
3rd−Harmonic
−60
−65
−70
VO = 4VPP
GD = 2
f = 5MHz
−75
−80
−85
−90
2nd−Harmonic
−95
−100
100
200
150
300
350
400
450
500
−55
GD = 2
VO = 4VPP
RL = 500Ω
3rd−Harmonic
−70
−80
−90
−100
GD = 2
RL = 500Ω
f = 5MHz
−60
Harmonic Distrtion (dBc)
Harmonic Distortion (dBc)
−60
250
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
DIFFERENTIAL DISTORTION vs FREQUENCY
−40
−50
200
Resistance (Ω)
Frequency (MHz)
−65
−70
3rd−Harmonic
−75
−80
−85
2nd−Harmonic
−90
−95
−100
2nd−Harmonic
−110
−105
0.1
1
10
Frequency (MHz)
100
1
10
Output Voltage Swing (VPP)
9
"#$
www.ti.com
SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, RL = 150Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 1).
INVERTING SMALL−SIGNAL FREQUENCY RESPONSE
NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE
3
6
G = +1
RF = 0Ω
G = −2
0
Normalized Gain (dB)
0
G = +2
−3
G = +5
−6
−9
G = +10
−12
VO = 0.2VPP
RL = 150Ω
See Figure 1
−15
−18
1
G = −1
−3
−6
G = −5
−9
G = −10
−12
VO = 0.2VPP
RL = 150Ω
See Figure 9
−15
−18
10
100
500
1
10
NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE
3
6
0
Gain (dB)
Gain (dB)
−3
VO = 1VPP
0
VO = 0.5VPP
−3
−6
VO = 0.5VPP
−12
−9
100
500
10
Frequency (MHz)
2.5
3.5
Small−Signal ± 100mV
Left Scale
3.0
2.5
2.4
2.0
2.3
1.5
2.2
1.0
2.1
0.5
Time (10ns/div)
10
4.0
Small−Signal Output Voltage (100mV/div)
2.7
Large−Signal Output Voltage (500mV/div)
Small−Signal Output Voltage (100mV/div)
Large−Signal ± 1V
Right Scale
500
INVERTING PULSE RESPONSE
4.5
G = +2V/V
See Figure 1
100
Frequency (MHz)
NONINVERTING PULSE RESPONSE
2.9
VO = 2VPP
G = −1V/V
RL = 150Ω
See Figure 9
−15
−18
10
2.6
VO = 1VPP
−6
−12
VO = 2VPP
G = +2V/V
RL = 150Ω
See Figure 1
−9
2.8
400
INVERTING LARGE−SIGNAL FREQUENCY RESPONSE
9
3
100
Frequency (MHz)
Frequency (MHz)
2.9
4.5
G = −1V/V
2.8
4.0
2.7
3.5
2.6
3.0
2.5
Small−Signal ± 100mV
Left Scale
2.4
2.3
2.2
2.5
2.0
Large−Signal ± 1V
Right Scale
2.1
1.5
1.0
0.5
Time (10ns/div)
Large−Signal Output Voltage (500mV/div)
Normalized Gain (dB)
3
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = 25°C, G = +2, RF = 750Ω, RL = 150Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 1).
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION vs LOAD RESISTANCE
−50
−50
−55
−55
−60
2nd−Harmonic
−65
−70
−75
f = 5MHz
VO = 2VPP
G = +2V/V
See Figure 1
−80
−85
−60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
G = +2V/V
VO = 2VPP
See Figure 1
3rd−Harmonic
3rd−Harmonic
R L = 150Ω
2nd−Harmonic
RL = 500Ω
−65
−70
−75
2nd−Harmonic
RL = 150Ω
−80
−85
−90
−95
3rd−Harmonic
RL = 500Ω
−100
−105
−90
100
1000
0.1
1
HARMONIC DISTORTION vs OUTPUT VOLTAGE
HARMONIC DISTORTION vs NONINVERTING GAIN
−45
−60
Input Limited
Harmonic Distortion (dBc)
−55
Harmonic Distortion (dBc)
−55
f = 5MHz
RL = 500Ω
G = +2V/V
See Figure 1
−50
−65
−70
−75
2nd−Harmonic
−80
−85
−90
−60
2nd−Harmonic
−65
−70
−75
−80
f = 5MHz
RL = 500Ω
VO = 2VPP
See Figure 1
3rd−Harmonic
−85
3rd−Harmonic
−95
−100
−90
0.1
1
10
1
10
Output Voltage Swing (VPP)
Gain (V/V)
TWO−TONE, 3RD−ORDER INTERMODULATION SPURIOUS
HARMONIC DISTORTION vs INVERTING GAIN
−45
3rd−Order Spurious Level (dBc)
−55
Harmonic Distortion (dBc)
10
Frequency (MHz)
Load Resistance (Ω )
−60
2nd−Harmonic
−65
−70
3rd−Harmonic
−75
f = 5MHz
RL = 500Ω
VO = 2VPP
−80
−85
1
10
Gain ( V/V )
−50
−55
PI
50Ω
PO
OPA830
500Ω
20MHz
750Ω
−60
−65
750Ω
10MHz
−70
−75
−80
5MHz
−85
−90
−95
−26 −24 −22 −20 −18 −16 −14 −12 −10 −8
−6
−4
−2
Single−Tone Load Power (dBm)
11
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = 25°C, G = +2, RF = 750Ω, RL = 150Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 1).
INPUT VOLTAGE AND CURRENT NOISE DENSITY
CLOSED−LOOP OUTPUT IMPEDANCE vs FREQUENCY
100
Output Impedance (Ω)
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
100
Voltage Noise
(9.2nV/√Hz)
10
Current Noise
(3.5pA/√Hz)
10
1
0.1
0.01
1
10
100
1k
10k
100k
1M
10M
1k
10k
100k
Normalized Gain to Capacitive Load (dB)
0dB Peaking Targeted
110
100
RS (Ω)
90
80
70
60
50
40
30
20
10
1
10
100
8
6
CL = 100pF
5
CL = 1000pF
4
3
2
1
RS
VI
50Ω
0
VO
O P A830
CL
−1
750Ω
NOTE: (1) 1kΩis optional.
−3
1k
1
10
−20
4.5
−40
4.0
20 log (AOL)
−60
−80
40
∠(AOL)
−120
10
−140
0
−160
−10
−180
1k
10k
100k
1M
Frequency (Hz)
12
−100
10M
100M
−200
1G
Voltage Range (V)
70
Open−Loop Phase (_ )
Open−Loop Gain (dB)
5.0
−20
100
300
VOLTAGE RANGES vs TEMPERATURE
0
20
100
Frequency (MHz)
OPEN−LOOP GAIN AND PHASE
30
1kΩ(1)
750Ω
−2
80
50
100M
CL = 10pF
7
Capacitive Load (pF)
60
10M
FREQUENCY RESPONSE vs CAPACITIVE LOAD
RECOMMENDED RS vs CAPACITIVE LOAD
130
120
1M
Frequency (Hz)
Frequency (Hz)
Most Positive Output Voltage
3.5
3.0
2.5
Most Positive Input Voltage
2.0
RL = 150Ω
1.5
1.0
Least Positive Output Voltage
0.5
0
−0.5
−1.0
−50
Least Positive Input Voltage
0
50
Ambient Temperature (10_ C/div)
110
"#$
www.ti.com
SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = 25°C, G = +2, RF = 750Ω, RL = 150Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 1).
TYPICAL DC DRIFT OVER TEMPERATURE
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
6
2
4
1
2
10 × Input Offset Current (IOS)
0
0
−1
−2
−2
−4
Input Offset Voltage (VOS)
−3
−8
−50
−25
−6
25
50
75
100
90
85
5.0
4.5
Output Current, Sinking
80
4.0
75
3.5
70
3.0
Output Current, Sourcing
60
−50
125
2.5
−25
2.0
0
25
50
75
100
125
Ambient Temperature (_C)
Ambient Temperature (_ C)
CMRR AND PSRR vs FREQUENCY
OUTPUT SWING vs LOAD RESISTANCE
90
5.5
80
5.0
4.5
70
CMRR
Output Voltage (V)
Common−Mode Rejection Ratio (dB)
Power−Supply Rejection Ratio (dB)
5.5
Quiescent Current
65
−8
0
6.0
95
Output Current (5mA/div)
Input Offset Voltage (mV)
3
100
Supply Current (0.5mA/div)
8
Input Bias Current (IB)
Input Bias and Offset Current (µV)
4
60
50
40
30
PSRR
4.0
3.5
G = +5V/V
3.0
2.5
2.0
1.5
1.0
20
0.5
10
0
0
1k
10k
100k
1M
Frequency (Hz)
10M
100M
−0.5
10
100
1k
Load Resistance (Ω )
13
"#$
www.ti.com
SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = +5V, Differential Configuration
At TA = 25°C, G = +2, RF = 604Ω, and RL = 500Ω differential, unless otherwise noted.
DIFFERENTIAL SMALL−SIGNAL FREQUENCY RESPONSE
+5V
3
1.2kΩ
GD = 1
2.5V
0
R
0.1µF
OPA830
Normalized Gain (dB)
1.2kΩ
60 4Ω
G
60 4Ω
VI
R
VO
L
+5V
R
GD = 2
−3
−6
GD = 5
−9
GD = 10
−12
G
1.2kΩ
1.2kΩ
VO = 200mVPP
RL = 500Ω
OPA830
2.5V
0.1µF
GD =
−15
604Ω
RG
1
10
100
200
Frequency (MHz)
DIFFERENTIAL LARGE−SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
−40
9
VO = 3VPP
Gain (dB)
3
VO = 2VPP
0
−3
−6
−9
VO = 1VPP
GD = 2
RL = 500Ω
1
Harmonic Distortion (dBc)
−45
6
VO = 0.2VPP
10
−50
3rd−Harmonic
−55
−60
−65
VO = 4VPP
GD = 2
f = 5MHz
−70
−75
−80
2nd−Harmonic
−85
100
−90
100
200
150
−50
3rd−Harmonic
−60
−70
2nd−Harmonic
−80
−90
400
450
500
−80
−85
2nd−Harmonic
−90
−95
100
3rd−Harmonic
−75
−100
10
350
−70
−110
Frequency (MHz)
14
−65
−100
1
300
GD = 2
RL = 500Ω
f = 5MHz
−60
Harmonic Distrtion (dBc)
Harmonic Distrtion (dBc)
−55
VO = 4VPP
GD = 2
RL = 500Ω
−40
250
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
DIFFERENTIAL DISTORTION vs FREQUENCY
−30
200
Resistance (Ω)
Frequency (MHz)
1
10
Output Voltage Swing (VPP)
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = +3V
At TA = 25°C, G = +2, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 2).
INVERTING SMALL−SIGNAL FREQUENCY RESPONSE
3
3
0
Normalized Gain (dB)
Normalized Gain (dB)
NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE
6
0
G = +2
−3
G = +5
−6
−9
G = +10
−12
RL = 150Ω
VO = 0.2VPP
See Figure 2
−15
−18
1
G = −1
−3
G = −2
−6
G = −5
−9
G = −10
−12
RL = 150Ω
VO = 0.2VPP
−15
−18
10
100
400
1
10
100
300
Frequency (MHz)
Frequency (MHz)
NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE
INVERTING LARGE−SIGNAL FREQUENCY RESPONSE
9
3
6
0
3
−3
VO = 0.5VPP
VO = 1VPP
VO = 0.5VPP
0
Gain (dB)
VO = 1.5VPP
−3
−6
−6
VO = 1.5VPP
−9
−12
RL = 150Ω
G = +2V/V
See Figure 2
−9
−12
−15
RL = 150Ω
G = −1V/V
−18
10
100
400
10
Frequency (MHz)
Large−Signal ± 0.5V
Right Scale
1.10
1.05
1.00
1.75
1.50
Small−Signal ± 100mV
Left Scale
1.25
1.00
0.95
0.75
0.90
0.50
0.85
0.25
0.80
0
Time (10ns/div)
Small−Signal Output Voltage (90mV/div)
1.15
G = +2V/V
See Figure 2
300
INVERTING PULSE RESPONSE
2.00
Large−Signal Output Voltage (250mV/div)
Small−Signal Output Voltage (90mV/div)
NONINVERTING PULSE RESPONSE
1.20
100
Frequency (MHz)
1.20
1.15
2.00
G = −1V/V
Large−Signal ± 0.5V
Right Scale
1.10
1.05
1.00
1.75
1.50
Small−Signal ± 100mV
Left Scale
1.25
1.00
0.95
0.75
0.90
0.50
0.85
0.25
0.80
0
Large−Signal Output Voltage (250mV/div)
Gain (dB)
VO = 1VPP
Time (10ns/div)
15
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = +3V (continued)
At TA = 25°C, G = +2, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 2).
HARMONIC DISTORTION vs LOAD RESISTANCE
−50
Harmonic Distortion (dBc)
−60
−65
2nd−Harmonic
−70
−75
−80
3rd−Harmonic
f = 5MHz
RL = 500Ω
G = +2V/V
See Figure 2
−50
Harmonic Distortion (dBc)
f = 5MHz
VO = 1VPP
G = +2V/V
See Figure 2
−55
HARMONIC DISTORTION vs OUTPUT VOLTAGE
−40
−60
Input Limited
−70
−90
−85
−100
−90
100
0.1
1000
1
TWO−TONE, 3RD−ORDER INTERMODULATION SPURIOUS
HARMONIC DISTORTION vs FREQUENCY
−55
VO = 1VPP
G = +2V/V
See Figure 2
Harmonic Distortion (dBc)
−65
2nd−Harmonic
RL = 500Ω
−70
−75
3rd−Order Spurious Level (dBc)
−40
−60
2nd−Harmonic
RL = 150Ω
−80
−85
3rd−Harmonic
RL = 150Ω
−90
3rd−Harmonic
RL = 500Ω
−95
−100
0.1
1
10
−45
PI
50Ω
−50
500Ω
750Ω
−55
−60
−65
−70
−75
10MHz
−80
−85
5MHz
−90
−95
−28 −26 −24 −22 −20 −18 −16 −14 −12 −10
150
130
110
90
70
50
30
10
Capacitive Load (pF)
1k
Normalized Gain to Capacitive Load (dB)
0dB Peaking Targeted
170
100
−8
FREQUENCY RESPONSE vs CAPACITIVE LOAD
RECOMMENDED RS vs CAPACITIVE LOAD
10
20MHz
750Ω
Single−Tone Load Power (dBm)
190
1
PO
OPA830
Frequency (MHz)
RS (Ω)
10
Output Voltage Swing (VPP )
Resistance (Ω )
16
3rd−Harmonic
2nd−Harmonic
−80
8
CL = 10pF
7
CL = 100pF
6
5
CL = 1000pF
4
3
2
1
RS
VI
50Ω
0
VO
O P A830
CL
1kΩ(1)
750Ω
−1
−2
750Ω
NOTE: (1) 1kΩ is optional.
−3
1
10
Frequency (MHz)
100
200
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = +3V (continued)
At TA = 25°C, G = +2, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 2).
OUTPUT SWING vs LOAD RESISTANCE
3.5
Output Voltage (V)
3.0
2.5
2.0
G = +5V/V
1.5
1.0
0.5
0
−0.5
10
100
1k
Load Resistance (Ω )
17
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: VS = +3V, Differential Configuration
At TA = 25°C, G = +2, RF = 604Ω, and RL = 500Ω differential, unless otherwise noted.
+3V
DIFFERENTIAL SMALL−SIGNAL FREQUENCY RESPONSE
3
2kΩ
1V
0
OPA830
Normalized Gain (dB)
0.1µF
1kΩ
60 4Ω
RG
60 4Ω
VI
RL
VO
+3V
RG
GD = 1
−3
GD = 5
−9
GD = 10
−12
2kΩ
OPA830
1V
−15
0.1µ F
1kΩ
GD =
GD = 2
−6
604Ω
VO = 200mVPP
RL = 500Ω
1
10
RG
100
200
Frequency (MHz)
DIFFERENTIAL LARGE−SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
−40
9
−45
Gain (dB)
3
Harmonic Distortion (dBc)
6
VO = 2VPP
0
VO = 1VPP
−3
VO = 200mVPP
−6
−55
−60
−65
1
10
100
−70
−75
−80
2nd−Harmonic
−90
100
200
150
GD = 2
VO = 2VPP
RL = 500Ω
−65
3rd−Harmonic
−75
−85
−95
2nd−Harmonic
−105
−115
0.1
1
10
Frequency (MHz)
18
300
350
400
450
500
−75
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
−55
250
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
DIFFERENTIAL DISTORTION vs FREQUENCY
−45
200
Resistance (Ω)
Frequency (MHz)
−35
3rd−Harmonic
VO = 4VPP
GD = 2
f = 5MHz
−85
GD = 2
−9
−50
100
−80
GD = 2
RL = 500Ω
f = 5MHz
3rd−Harmonic
−85
2nd−Harmonic
−90
−95
−100
0.50
0.75
1.00
1.25
1.50
Output Voltage Swing (VPP)
1.75
2.00
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
APPLICATIONS INFORMATION
WIDEBAND VOLTAGE-FEEDBACK
OPERATION
The OPA830 is a unity-gain stable, very high-speed
voltage-feedback op amp designed for single-supply
operation (+3V to +10V). The input stage supports input
voltages below ground and to within 1.7V of the positive
supply. The complementary common-emitter output stage
provides an output swing to within 25mV of ground and the
positive supply. The OPA830 is compensated to provide
stable operation with a wide range of resistive loads.
Figure 1 shows the AC-coupled, gain of +2 configuration
used for the +5V Specifications and Typical Characteristic
Curves. For test purposes, the input impedance is set to
50Ω with a resistor to ground. Voltage swings reported in
the Electrical Characteristics are taken directly at the input
and output pins. For the circuit of Figure 1, the total
effective load on the output at high frequencies is
150Ω || 1500Ω. The 1.5kΩ resistors at the noninverting
input provide the common-mode bias voltage. Their
parallel combination equals the DC resistance at the
inverting input (RF), reducing the DC output offset due to
input bias current.
the Electrical Characteristics are taken directly at the input
and output pins. For the circuit of Figure 2, the total
effective load on the output at high frequencies is
150Ω || 1500Ω. The 1.13kΩ and 2.26kΩ resistors at the
noninverting input provide the common-mode bias
voltage. Their parallel combination equals the DC
resistance at the inverting input (RF), reducing the DC
output offset due to input bias current.
VS = +3V
6.8µF
+
2.26kΩ
0.1µF
53.6Ω
0.1µF
VIN
53.6Ω
0.1µF
2.5V
1.50kΩ
VOUT
OPA830
RL
150Ω
RG
750Ω
+VS/2
RF
750Ω
1.13kΩ
VOUT
OPA830
RL
150Ω
RG
750Ω
RF
750Ω
+VS
3
Figure 2. AC-Coupled, G = +2, +3V Single-Supply
Specification and Test Circuit
6.8µF
+
1.50kΩ
+1V
VIN
+VS/3
VS = +5V
0.1µF
+VS
2
Figure 1. AC-Coupled, G = +2, +5V Single-Supply
Specification and Test Circuit
Figure 2 shows the AC-coupled, gain of +2 configuration
used for the +3V Specifications and Typical Characteristic
Curves. For test purposes, the input impedance is set to
50Ω with a resistor to ground. Voltage swings reported in
Figure 3 shows the DC-coupled, gain of +2, dual
power-supply circuit configuration used as the basis of the
±5V Electrical Characteristics and Typical Characteristics.
For test purposes, the input impedance is set to 50Ω with
a resistor to ground and the output impedance is set to
150Ω with a series output resistor. Voltage swings
reported in the specifications are taken directly at the input
and output pins. For the circuit of Figure 3, the total
effective load will be 150Ω || 1.5kΩ. Two optional
components are included in Figure 3. An additional
resistor (348Ω) is included in series with the noninverting
input. Combined with the 25Ω DC source resistance
looking back towards the signal generator, this gives an
input bias current cancelling resistance that matches the
375Ω source resistance seen at the inverting input (see
the DC Accuracy and Offset Control section). In addition
to the usual power-supply decoupling capacitors to
ground, a 0.01µF capacitor is included between the two
power-supply pins. In practical PC board layouts, this
optional capacitor will typically improve the 2nd-harmonic
distortion performance by 3dB to 6dB.
19
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
+5V
0.1µF
+VS
6.8µF
+
R2
50Ω Source
R1
348Ω
VIN
VIN
VO
50Ω
150Ω
0.01µF
RF
750Ω
RG
750Ω
+
R3
6.8µF
0.1µF
−5V
Figure 3. DC-Coupled, G = +2, Bipolar Supply
Specification and Test Circuit
SINGLE-SUPPLY ADC INTERFACE
The ADC interface on the front page shows a DC-coupled,
single-supply ADC driver circuit. Many systems are now
requiring +3V supply capability of both the ADC and its
driver. The OPA830 provides excellent performance in this
demanding application. Its large input and output voltage
ranges and low distortion support converters such as the
THS1040 shown in the figure on page 1. The input
level-shifting circuitry was designed so that VIN can be
between 0V and 0.5V, while delivering an output voltage
of 1V to 2V for the THS1040.
DC LEVEL-SHIFTING
Figure 4 shows a DC-coupled noninverting amplifier that
level-shifts the input up to accommodate the desired
output voltage range. Given the desired signal gain (G),
and the amount VOUT needs to be shifted up (∆VOUT)
when VIN is at the center of its range, the following
equations give the resistor values that produce the desired
performance. Assume that R4 is between 200Ω and
1.5kΩ.
NG = G + VOUT/VS
R1 = R4/G
R2 = R4/(NG − G)
R3 = R4/(NG −1)
where:
NG = 1 + R4/R3
VOUT = (G)VIN + (NG − G)VS
Make sure that VIN and VOUT stay within the specified
input and output voltage ranges.
20
OPA830
OPA830
VOUT
R4
Figure 4. DC Level-Shifting
The circuit on the front page is a good example of this type
of application. It was designed to take VIN between 0V and
0.5V and produce VOUT between 1V and 2V when using
a +3V supply. This means G = 2.00, and
∆VOUT = 1.50V − G × 0.25V = 1.00V. Plugging these
values into the above equations (with R4 = 750Ω) gives:
NG = 2.33, R1 = 375Ω, R2 = 2.25kΩ, and R3 = 563Ω. The
resistors were changed to the nearest standard values for
the front page circuit.
AC-COUPLED OUTPUT VIDEO LINE DRIVER
Low-power and low-cost video line drivers often buffer
digital-to-analog converter (DAC) outputs with a gain of 2
into a doubly-terminated line. Those interfaces typically
require a DC blocking capacitor. For a simple solution, that
interface often has used a very large value blocking
capacitor (220µF) to limit tilt, or SAG, across the frames.
One approach to creating a very low high-pass pole
location using much lower capacitor values is shown in
Figure 5. This circuit gives a voltage gain of 2 at the output
pin with a high-pass pole at 8Hz. Given the 150Ω load, a
simple blocking capacitor approach would require a 133µF
value. The two much lower valued capacitors give this
same low-pass pole using this simple SAG correction
circuit of Figure 5.
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
+5V
1.87kΩ
Video DAC
47µF
75Ω
VO
OPA830
78.7Ω
75Ω Load
22µF
845Ω
325Ω
528Ω
650Ω
Figure 5. Video Line Driver with SAG Correction
The input is shifted slightly positive in Figure 5 using the
voltage divider from the positive supply. This gives about
a 200mV input DC offset that will show up at the output pin
as a 400mV DC offset when the DAC output is at zero
current during the sync tip portion of the video signal. This
acts to hold the output in its linear operating region. This
will pass on any power-supply noise to the output with a
gain of approximately −20dB, so good supply decoupling
is recommended on the power-supply pin. Figure 6 shows
the frequency response for the circuit of Figure 5. This plot
shows the 8Hz low-frequency high-pass pole and a
high-end cutoff at approximately 100MHz.
impedance source, such as an op amp. The resistor
values are low to reduce noise. Using both RT and RF
helps minimize the impact of parasitic impedances.
+5V
RT
VIN
RC
OPA830
RG
VOUT
RF
3
Normalized Gain (dB)
0
Figure 7. Compensated Noninverting Amplifier
−3
−6
The Noise Gain can be calculated as follows:
−9
G1 + 1 )
−12
−15
RF
RG
(1)
RF
−18
G2 + 1 )
−21
1
10
102
103
104
105
106
107
108
RT ) G
109
Frequency (Hz)
Figure 6. Video Line Driver Response to Matched
Load
NONINVERTING AMPLIFIER WITH REDUCED
PEAKING
Figure 7 shows a noninverting amplifier that reduces
peaking at low gains. The resistor RC compensates the
OPA830 to have higher Noise Gain (NG), which reduces
the AC response peaking (typically 5dB at G = +1 without
RC) without changing the DC gain. VIN needs to be a low
NG + G 1
RC
G2
1
(2)
(3)
A unity-gain buffer can be designed by selecting
RT = RF = 20.0Ω and RC = 40.2Ω (do not use RG). This
gives a noise gain of 2, so the response will be similar to
the Characteristics Plots with G = +2. Decreasing RC to
20.0Ω will increase the noise gain to 3, which typically
gives a flat frequency response, but with less bandwidth.
The circuit in Figure 1 can be redesigned to have less
peaking by increasing the noise gain to 3. This is
accomplished by adding RC = 2.55kΩ across the op amp
inputs.
21
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
SINGLE-SUPPLY ACTIVE FILTER
The OPA830, while operating on a single +3V or +5V
supply, lends itself well to high-frequency active filter
designs. Again, the key additional requirement is to
establish the DC operating point of the signal near the
supply midpoint for highest dynamic range. Figure 8
shows an example design of a 1MHz low-pass Butterworth
filter using the Sallen-Key topology.
Both the input signal and the gain setting resistor are
AC-coupled using 0.1µF blocking capacitors (actually
giving bandpass response with the low-frequency pole set
to 32kHz for the component values shown). As discussed
for Figure 1, this allows the midpoint bias formed by the
two 1.87kΩ resistors to appear at both the input and output
pins. The midband signal gain is set to +4 (12dB) in this
case. The capacitor to ground on the noninverting input is
intentionally set larger to dominate input parasitic terms. At
a gain of +4, the OPA830 on a single supply will show
30MHz small- and large-signal bandwidth. The resistor
values have been slightly adjusted to account for this
limited bandwidth in the amplifier stage. Tests of this circuit
show a precise 1MHz, −3dB point with a maximally-flat
passband (above the 32kHz AC-coupling corner), and a
maximum stop band attenuation of 36dB at the amplifier’s
−3dB bandwidth of 30MHz.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Two printed circuit boards (PCBs) are available to assist
in the initial evaluation of circuit performance using the
OPA830 in its two package options. Both of these are
offered free of charge as unpopulated PCBs, delivered
with a user’s guide. The summary information for these
fixtures is shown in Table 1.
Table 1. Demonstration Fixtures by Package
ORDERING
PACKAGE
NUMBER
NUMBER
OPA830ID
SO-8
DEM-OPA-SO-1A
SBOU009
OPA830IDBV
SOT23-5
DEM-OPA-SOT-1A
SBOU010
The demonstration fixtures can be requested at the Texas
Instruments web site (www.ti.com) through the OPA830
product folder.
+5V
100pF
1.87kΩ
0.1µF
137Ω
432Ω
VI
1.87kΩ
150pF
OPA830
4V I
1MHz, 2nd−Order
Butterworth Filter
1.5kΩ
500Ω
0.1µF
Figure 8. Single-Supply, High-Frequency Active Filter
22
LITERATURE
PRODUCT
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
MACROMODEL AND APPLICATIONS
SUPPORT
Computer simulation of circuit performance using SPICE
is often a quick way to analyze the performance of the
OPA830 and its circuit designs. This is particularly true for
video and RF amplifier circuits where parasitic
capacitance and inductance can play a major role on
circuit performance. A SPICE model for the OPA830 is
available through the TI web page (www.ti.com). The
applications department is also available for design
assistance. These models predict typical small signal AC,
transient steps, DC performance, and noise under a wide
variety of operating conditions. The models include the
noise terms found in the electrical specifications of the
data sheet. These models do not attempt to distinguish
between the package types in their small-signal AC
performance.
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
Since the OPA830 is a unity-gain stable, voltage-feedback
op amp, a wide range of resistor values may be used for
the feedback and gain setting resistors. The primary limits
on these values are set by dynamic range (noise and
distortion) and parasitic capacitance considerations. For a
noninverting unity-gain follower application, the feedback
connection should be made with a direct short.
Below 200Ω, the feedback network will present additional
output loading which can degrade the harmonic distortion
performance of the OPA830. Above 1kΩ, the typical
parasitic capacitance (approximately 0.2pF) across the
feedback resistor may cause unintentional band limiting in
the amplifier response.
A good rule of thumb is to target the parallel combination
of RF and RG (see Figure 3) to be less than about 400Ω.
The combined impedance RF || RG interacts with the
inverting input capacitance, placing an additional pole in
the feedback network, and thus a zero in the forward
response. Assuming a 2pF total parasitic on the inverting
node, holding RF || RG < 400Ω will keep this pole above
200MHz. By itself, this constraint implies that the feedback
resistor RF can increase to several kΩ at high gains. This
is acceptable as long as the pole formed by RF and any
parasitic capacitance appearing in parallel is kept out of
the frequency range of interest.
In the inverting configuration, an additional design
consideration must be noted. RG becomes the input
resistor and therefore the load impedance to the driving
source. If impedance matching is desired, RG may be set
equal to the required termination value. However, at low
inverting gains, the resultant feedback resistor value can
present a significant load to the amplifier output. For
example, an inverting gain of 2 with a 50Ω input matching
resistor (= RG) would require a 100Ω feedback resistor,
which would contribute to output loading in parallel with the
external load. In such a case, it would be preferable to
increase both the RF and RG values, and then achieve the
input matching impedance with a third resistor to ground
(see Figure 9). The total input impedance becomes the
parallel combination of RG and the additional shunt
resistor.
BANDWIDTH vs GAIN:
NONINVERTING OPERATION
Voltage-feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the Gain Bandwidth Product
(GBP) shown in the specifications. Ideally, dividing GBP
by the noninverting signal gain (also called the Noise Gain,
or NG) will predict the closed-loop bandwidth. In practice,
this only holds true when the phase margin approaches
90°, as it does in high-gain configurations. At low gains
(increased feedback factors), most amplifiers will exhibit a
more complex response with lower phase margin. The
OPA830 is compensated to give a slightly peaked
response in a noninverting gain of 2 (see Figure 3). This
results in a typical gain of +2 bandwidth of 110MHz, far
exceeding that predicted by dividing the 110MHz GBP by
2. Increasing the gain will cause the phase margin to
approach 90° and the bandwidth to more closely approach
the predicted value of (GBP/NG). At a gain of +10, the
11MHz bandwidth shown in the Electrical Characteristics
agrees with that predicted using the simple formula and
the typical GBP of 110MHz.
Frequency response in a gain of +2 may be modified to
achieve exceptional flatness simply by increasing the
noise gain to 3. One way to do this, without affecting the +2
signal gain, is to add an 2.55kΩ resistor across the two
inputs, as shown in Figure 7. A similar technique may be
used to reduce peaking in unity-gain (voltage follower)
applications. For example, by using a 750Ω feedback
resistor along with a 750Ω resistor across the two op amp
inputs, the voltage follower response will be similar to the
gain of +2 response of Figure 2. Further reducing the value
of the resistor across the op amp inputs will further dampen
the frequency response due to increased noise gain. The
OPA830 exhibits minimal bandwidth reduction going to
single-supply (+5V) operation as compared with ±5V. This
minimal reduction is because the internal bias control
circuitry retains nearly constant quiescent current as the
total supply voltage between the supply pins is changed.
INVERTING AMPLIFIER OPERATION
All of the familiar op amp application circuits are available
with the OPA830 to the designer. See Figure 9 for a typical
inverting configuration where the I/O impedances and
signal gain from Figure 1 are retained in an inverting circuit
configuration. Inverting operation is one of the more
common requirements and offers several performance
benefits. It also allows the input to be biased at VS/2
without any headroom issues. The output voltage can be
independently moved to be within the output voltage range
with coupling capacitors, or bias adjustment resistors.
23
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
+5V
+
0.1µF
6.8µF
2RT
1.5kΩ
150Ω
0.1µF
50Ω Source
0.1µF
2RT
1.5kΩ
RG
374Ω
OPA830
+VS
2
RF
750Ω
RM
57.6Ω
Figure 9. AC-Coupled, G = −2 Example Circuit
In the inverting configuration, three key design
considerations must be noted. The first consideration is
that the gain resistor (RG) becomes part of the signal
channel input impedance. If input impedance matching is
desired (which is beneficial whenever the signal is coupled
through a cable, twisted pair, long PC board trace, or other
transmission line conductor), RG may be set equal to the
required termination value and RF adjusted to give the
desired gain. This is the simplest approach and results in
optimum bandwidth and noise performance.
However, at low inverting gains, the resulting feedback
resistor value can present a significant load to the amplifier
output. For an inverting gain of 2, setting RG to 50Ω for
input matching eliminates the need for RM but requires a
100Ω feedback resistor. This configuration has the
interesting advantage of the noise gain becoming equal to
2 for a 50Ω source impedance—the same as the
noninverting circuits considered above. The amplifier
output will now see the 100Ω feedback resistor in parallel
with the external load. In general, the feedback resistor
should be limited to the 200Ω to 1.5kΩ range. In this case,
it is preferable to increase both the RF and RG values, as
shown in Figure 9, and then achieve the input matching
impedance with a third resistor (RM) to ground. The total
input impedance becomes the parallel combination of RG
and RM.
The second major consideration, touched on in the
previous paragraph, is that the signal source impedance
becomes part of the noise gain equation and hence
influences the bandwidth. For the example in Figure 9, the
RM value combines in parallel with the external 50Ω
source impedance (at high frequencies), yielding an
effective driving impedance of 50Ω || 57.6Ω = 26.8Ω. This
impedance is added in series with RG for calculating the
noise gain. The resulting noise gain is 2.87 for Figure 9, as
opposed to only 2 if RM could be eliminated as discussed
above. The bandwidth will therefore be lower for the gain
24
of −2 circuit of Figure 9 (NG = +2.87) than for the gain of
+2 circuit of Figure 1.
The third important consideration in inverting amplifier
design is setting the bias current cancellation resistors on
the noninverting input (a parallel combination of
RT = 750Ω). If this resistor is set equal to the total DC
resistance looking out of the inverting node, the output DC
error, due to the input bias currents, will be reduced to
(Input Offset Current) times RF. With the DC blocking
capacitor in series with RG, the DC source impedance
looking out of the inverting mode is simply RF = 750Ω for
Figure 9. To reduce the additional high-frequency noise
introduced by this resistor and power-supply feed-through,
RT is bypassed with a capacitor.
OUTPUT CURRENT AND VOLTAGES
The OPA830 provides outstanding output voltage
capability. For the +5V supply, under no-load conditions at
+25°C, the output voltage typically swings closer than
90mV to either supply rail.
The minimum specified output voltage and current
specifications over temperature are set by worst-case
simulations at the cold temperature extreme. Only at cold
startup will the output current and voltage decrease to the
numbers shown in the ensured tables. As the output
transistors deliver power, their junction temperatures will
increase, decreasing their VBEs (increasing the available
output voltage swing) and increasing their current gains
(increasing the available output current). In steady-state
operation, the available output voltage and current will
always be greater than that shown in the over-temperature
specifications, since the output stage junction
temperatures will be higher than the minimum specified
operating ambient.
To maintain maximum output stage linearity, no output
short-circuit protection is provided. This will not normally
be a problem, since most applications include a series
matching resistor at the output that will limit the internal
power dissipation if the output side of this resistor is
shorted to ground. However, shorting the output pin
directly to the adjacent positive power-supply pin (8-pin
packages) will, in most cases, destroy the amplifier. If
additional short-circuit protection is required, consider a
small series resistor in the power-supply leads. This will
reduce the available output voltage swing under heavy
output loads.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC—including
additional external capacitance which may be recommended to improve ADC linearity. A high-speed, high
open-loop gain amplifier like the OPA830 can be very
susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed directly
on the output pin. When the primary considerations are
frequency response flatness, pulse response fidelity,
and/or distortion, the simplest and most effective solution
"#$
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SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
is to isolate the capacitive load from the feedback loop by
inserting a series isolation resistor between the amplifier
output and the capacitive load.
The Typical Characteristic curves show the recommended
RS versus capacitive load and the resulting frequency
response at the load. Parasitic capacitive loads greater
than 2pF can begin to degrade the performance of the
OPA830. Long PC board traces, unmatched cables, and
connections to multiple devices can easily exceed this
value. Always consider this effect carefully, and add the
recommended series resistor as close as possible to the
output pin (see the Board Layout Guidelines section).
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load. For a gain
of +2, the frequency response at the output pin is already
slightly peaked without the capacitive load, requiring
relatively high values of RS to flatten the response at the
load. Increasing the noise gain will also reduce the peaking
(see Figure 7).
DISTORTION PERFORMANCE
The OPA830 provides good distortion performance into a
150Ω load. Relative to alternative solutions, it provides
exceptional performance into lighter loads and/or
operating on a single +3V supply. Generally, until the
fundamental signal reaches very high frequency or power
levels, the 2nd-harmonic will dominate the distortion with
a negligible 3rd-harmonic component. Focusing then on
the 2nd-harmonic, increasing the load impedance
improves distortion directly. Remember that the total load
includes the feedback network; in the noninverting
configuration (see Figure 3) this is sum of RF + RG, while
in the inverting configuration, only RF needs to be included
in parallel with the actual load. Running differential
suppresses the 2nd-harmonic, as shown in the differential
typical characteristic curves.
NOISE PERFORMANCE
High slew rate, unity-gain stable, voltage-feedback op
amps usually achieve their slew rate at the expense of a
higher input noise voltage. The 9.2nV/√Hz input voltage
noise for the OPA830 however, is much lower than
comparable amplifiers. The input-referred voltage noise
and the two input-referred current noise terms (2.8pA/√Hz)
combine to give low output noise under a wide variety of
operating conditions. Figure 10 shows the op amp noise
analysis model with all the noise terms included. In this
model, all noise terms are taken to be noise voltage or
current density terms in either nV/√Hz or pA/√Hz.
ENI
EO
OPA830
RS
IBN
ERS
RF
√ 4kTRS
RG
4kT
RG
√ 4kTRF
I BI
4kT = 1.6E − 20J
at 290_K
Figure 10. Noise Analysis Model
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 4 shows the general form for the
output noise voltage using the terms shown in Figure 10:
EO +
Ǹǒ
Ǔ
E NI ) ǒI BNRSǓ ) 4kTRS NG 2 ) ǒI BIR FǓ ) 4kTRFNG
2
2
2
(4)
Dividing this expression by the noise gain
(NG = (1 + RF/RG)) will give the equivalent input-referred
spot noise voltage at the noninverting input, as shown in
Equation 5:
EN +
Ǹ
ENI ) ǒIBNR SǓ ) 4kTRS )
2
2
ǒ Ǔ
IBIRF
NG
2
)
4kTRF
NG
(5)
Evaluating these two equations for the circuit and
component values shown in Figure 1 will give a total output
spot noise voltage of 19.3nV/√Hz and a total equivalent
input spot noise voltage of 9.65nV/√Hz. This is including
the noise added by the resistors. This total input-referred
spot noise voltage is not much higher than the 9.2nV/√Hz
specification for the op amp voltage noise alone.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage-feedback
op amp allows good output DC accuracy in a wide variety
of applications. The power-supply current trim for the
OPA830 gives even tighter control than comparable
products. Although the high-speed input stage does
require relatively high input bias current (typically 5µA out
of each input terminal), the close matching between them
may be used to reduce the output DC error caused by this
current. This is done by matching the DC source
resistances appearing at the two inputs. Evaluating the
configuration of Figure 3 (which has matched DC input
25
"#$
www.ti.com
SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
resistances), using worst-case +25°C input offset voltage
and current specifications, gives a worst-case output
offset voltage equal to:
(NG = noninverting signal gain at DC)
±(NG × VOS(MAX)) + (RF × IOS(MAX))
= ±(2 × 7mV) × (375Ω × 1µA)
= ±14.38mV
A fine-scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques are
available for introducing DC offset control into an op amp
circuit. Most of these techniques are based on adding a DC
current through the feedback resistor. In selecting an offset
trim method, one key consideration is the impact on the
desired signal path frequency response. If the signal path
is intended to be noninverting, the offset control is best
applied as an inverting summing signal to avoid interaction
with the signal source. If the signal path is intended to be
inverting, applying the offset control to the noninverting
input may be considered. Bring the DC offsetting current
into the inverting input node through resistor values that
are much larger than the signal path resistors. This will
insure that the adjustment circuit has minimal effect on the
loop gain and hence the frequency response.
THERMAL ANALYSIS
Maximum desired junction temperature will set the
maximum allowed internal power dissipation, as
described below. In no case should the maximum junction
temperature be allowed to exceed 150°C.
Operating junction temperature (TJ) is given by
TA + P D × q JA. The total internal power dissipation (P D)
is the sum of quiescent power (P DQ ) and additional
power dissipated in the output stage (P DL ) to deliver load
power. Quiescent power is simply the specified no-load
supply current times the total supply voltage across the
part. PDL will depend on the required output signal and
load; though, for resistive loads connected to
mid-supply (V S/2), PDL is at a maximum when the output
is fixed at a voltage equal to VS/4 or 3V S/4. Under this
condition, PDL = V S2 /(16 × R L ), where RL includes
feedback network loading.
Note that it is the power in the output stage, and not into the
load, that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using
an OPA830 (SOT23-5 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature
of +85°C and driving a 150Ω load at mid-supply.
PD = 10V × 3.9mA + 52/(16 × (150Ω || 750Ω)) = 51.5mW
Maximum TJ = +85°C + (0.051W × 150°C/W) = 93°C.
Although this is still well below the specified maximum
junction temperature, system reliability considerations
may require lower ensured junction temperatures. The
26
highest possible internal dissipation will occur if the load
requires current to be forced into the output at high output
voltages or sourced from the output at low output voltages.
This puts a high current through a large internal voltage
drop in the output transistors.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency
amplifier like the OPA830 requires careful attention to
board layout parasitics and external component types.
Recommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability: on the
noninverting input, it can react with the source impedance
to cause unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins should
be opened in all of the ground and power planes around
those pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
b) Minimize the distance ( < 0.25”) from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power-plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. Each powersupply connection should always be decoupled with one
of these capacitors. An optional supply decoupling
capacitor (0.1µF) across the two power supplies (for
bipolar operation) will improve 2nd-harmonic distortion
performance. Larger (2.2µF to 6.8µF) decoupling
capacitors, effective at lower frequency, should also be
used on the main supply pins. These may be placed
somewhat farther from the device and may be shared
among several devices in the same area of the PC board.
c) Careful selection and placement of external
components will preserve the high-frequency performance. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter
overall layout. Metal film or carbon composition
axially-leaded resistors can also provide good highfrequency performance. Again, keep their leads and PC
board traces as short as possible. Never use wire-wound
type resistors in a high-frequency application. Since the
output pin and inverting input pin are the most sensitive to
parasitic capacitance, always position the feedback and
series output resistor, if any, as close as possible to the
output pin. Other network components, such as
noninverting input termination resistors, should also be
placed close to the package. Where double-side
component mounting is allowed, place the feedback
resistor directly under the package on the other side of the
board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external
resistors, excessively high resistor values can create
"#$
www.ti.com
SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
significant time constants that can degrade performance.
Good axial metal film or surface-mount resistors have
approximately 0.2pF in shunt with the resistor. For resistor
values > 1.5kΩ, this parasitic capacitance can add a pole
and/or zero below 500MHz that can effect circuit
operation. Keep resistor values as low as possible
consistent with load driving considerations. The 750Ω
feedback used in the Typical Characteristics is a good
starting point for design.
d) Connections to other wideband devices on the board
may be made with short direct traces or through onboard
transmission lines. For short connections, consider the
trace and the input to the next device as a lumped
capacitive load. Relatively wide traces (50mils to 100mils)
should be used, preferably with ground and power planes
opened up around them. Estimate the total capacitive load
and set RS from the typical characteristic curve
Recommended RS vs Capacitive Load. Low parasitic
capacitive loads (< 5pF) may not need an RS since the
OPA830 is nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads without an
RS are allowed as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required, and the
6dB signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a matched
impedance transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω
environment is normally not necessary onboard, and in
fact, a higher impedance environment will improve
distortion as shown in the distortion versus load plots. With
a characteristic board trace impedance defined (based on
board material and trace dimensions), a matching series
resistor into the trace from the output of the OPA830 is
used as well as a terminating shunt resistor at the input of
the destination device. Remember also that the
terminating impedance will be the parallel combination of
the shunt resistor and the input impedance of the
destination device; this total effective impedance should
be set to match the trace impedance. If the 6dB attenuation
of a doubly-terminated transmission line is unacceptable,
a long trace can be series-terminated at the source end
only. Treat the trace as a capacitive load in this case and
set the series resistor value as shown in the typical
characteristic curve Recommended RS vs Capacitive
Load. This will not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the
destination device is low, there will be some signal
attenuation due to the voltage divider formed by the series
output into the terminating impedance.
e) Socketing a high-speed part is not recommended.
The additional lead length and pin-to-pin capacitance
introduced by the socket can create an extremely
troublesome parasitic network which can make it almost
impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the
OPA830 onto the board.
INPUT AND ESD PROTECTION
The OPA830 is built using a very high-speed complementary bipolar process. The internal junction breakdown
voltages are relatively low for these very small geometry
devices. These breakdowns are reflected in the Absolute
Maximum Ratings table. All device pins are protected with
internal ESD protection diodes to the power supplies, as
shown in Figure 11.
+VCC
External
Pin
Internal
Circuitry
− VCC
Figure 11. Internal ESD Protection
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA continuous
current. Where higher currents are possible (that is, in
systems with ±15V supply parts driving into the OPA830),
current-limiting series resistors should be added into the
two inputs. Keep these resistor values as low as possible,
since high values degrade both noise performance and
frequency response.
27
www.ti.com
SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
Revision History
DATE
REV
PAGE
SECTION
8/08
F
2
Absolute Maximum Ratings
8/07
E
1
Features
DESCRIPTION
Changed Storage Temperature minimum value from −40°C to −65°C.
Changed 550V/ns to 550V/µs.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
28
PACKAGE OPTION ADDENDUM
www.ti.com
16-Feb-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
OPA830ID
ACTIVE
SOIC
D
8
OPA830IDBVR
ACTIVE
SOT-23
DBV
OPA830IDBVRG4
ACTIVE
SOT-23
OPA830IDBVT
ACTIVE
OPA830IDBVTG4
75
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA830IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA830IDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA830IDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-May-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
OPA830IDBVR
SOT-23
DBV
5
3000
180.0
8.4
3.2
3.1
1.39
4.0
OPA830IDBVT
SOT-23
DBV
5
250
OPA830IDR
SOIC
D
8
2500
180.0
8.4
3.2
3.1
1.39
330.0
12.4
6.4
5.2
2.1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
8.0
Q3
4.0
8.0
Q3
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-May-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA830IDBVR
SOT-23
DBV
5
3000
190.5
212.7
31.8
OPA830IDBVT
SOT-23
DBV
5
250
190.5
212.7
31.8
OPA830IDR
SOIC
D
8
2500
346.0
346.0
29.0
Pack Materials-Page 2
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