TI OPA2683IDCNT

OPA
OPA2683
2683
OPA2
683
www.ti.com
SBOS244H – MAY 2002 – REVISED JULY 2009
Very Low-Power, Dual, Current-Feedback
Operational Amplifier
FEATURES
APPLICATIONS
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REDUCED BANDWIDTH CHANGE VERSUS GAIN
150MHz BANDWIDTH G = +2
> 80MHz BANDWIDTH TO GAIN > +10
LOW DISTORTION: < –65dBc at 5MHz
HIGH OUTPUT CURRENT: 110mA
SINGLE-SUPPLY OPERATION: +5V to +12V
DUAL-SUPPLY OPERATION: ±2.5V to ±6V
LOW SUPPLY CURRENT: 1.9mA Total
POWER SHUTDOWN VERSION: MSOP-10
DESCRIPTION
The OPA2683 provides a new level of performance for dual, very
low-power, wideband, current-feedback amplifiers. This CFBPLUS
amplifier is among the first to use an internally closed-loop input
buffer stage that significantly enhances performance over earlier
low-power, current-feedback (CFB) amplifiers. This new architecture provides many of the advantages of a more ideal CFB
amplifier while retaining the benefits of very low-power operation.
The closed-loop input stage buffer gives a very low and linearized
impedance path at the inverting input to sense the feedback error
current. This improved inverting input impedance gives exceptional bandwidth retention to much higher gains and improved
harmonic distortion over earlier solutions limited by inverting input
linearity. Beyond simple high gain applications, the OPA2683
CFBPLUS amplifier can allow the gain setting element to be set with
considerable freedom from amplifier bandwidth interaction. This
LOW-POWER BROADCAST VIDEO DRIVERS
µPOWER ACTIVE FILTERS
SHORT-LOOP ADSL CO DRIVERS
MULTICHANNEL SUMMING AMPLIFIERS
PROFESSIONAL CAMERAS
DIFFERENTIAL ADC INPUT DRIVERS
flexibility allows frequency response peaking elements to be
added, multiple input inverting summing circuits to have greater
bandwidth, and low-power differential line drivers to meet the
demanding requirements of DSL.
The output capability for the OPA2683 also sets a new mark in
performance for very low-power, current-feedback amplifiers. Delivering a full ±4VPP swing on ±5V supplies, the OPA2683 also has
the output current to support this swing into a 100Ω load. This
minimal output headroom requirement is complemented by a
similar 1.2V input stage headroom, giving exceptional capability for
single +5V operation.
The OPA2683’s low 1.9mA total supply current is precisely trimmed
at +25°C. This trim, along with low shift over temperature and supply
voltage, gives a very robust design over a wide range of operating
conditions. Further system power reduction is possible using
the shutdown feature of the MSOP-10 package.
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
V+
6
G = 10 G = 1
+
Z(S) IERR
V–
IERR
RF
VO
Normalized Gain (dB)
3
G=2
0
–3
G = 50
–6
G = 10
–9
G = 50
–12
–15
G = 100
RF = 953Ω
RG
Low-Power
–18
Amplifier
1
U.S. Patent No. 6,724,260
10
100
200
Frequency (Hz)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2002-2009, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply ............................................................................... ±6.5VDC
Internal Power Dissipation ...................................... See Thermal Analysis
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ............................................................................ ±VS
Storage Temperature Range: ID, IDCN ......................... –65°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature (TJ ) ........................................................... +150°C
ESD Rating: Human Body Model (HBM) ........................................ 2000V
Charged Device Model (CDM) .................................. 1000V
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
OPA2683 RELATED PRODUCTS
SINGLES
DUALS
TRIPLES
QUADS
OPA684
OPA691
OPA695
OPA2684
OPA2691
OPA2695
OPA3684
OPA3691
OPA3695
OPA4684
—
—
FEATURES
Low-Power CFB
High Slew Rate CFB
> 500MHz CFB
PACKAGE/ORDERING INFORMATION(1)
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
OPA2683
SO-8
D
–40°C to +85°C
OPA2683
"
"
"
"
"
OPA2683ID
OPA2683IDR
Rails,100
Tape and Reel, 2500
OPA2683
SOT23-8
DCN
–40°C to +85°C
B83
OPA2683IDCNT
Tape and Reel, 250
"
"
"
"
"
OPA2683IDCNR
Tape and Reel, 3000
OPA2683
MSOP-10
DGS
–40°C to +85°C
BUI
OPA2683IDGST
Tape and Reel, 250
"
"
"
"
"
OPA2683IDGSR
Tape and Reel, 2500
PRODUCT
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.
PIN CONFIGURATION
Top View
SO-8
Out A
1
8
+VS
–In A
2
7
Out B
+In A
3
6
–In B
–VS
4
5
+In B
Top View
2
Top View
SOT23-8
Out A
1
8
+VS
–In A
2
7
Out B
+In A
3
6
–In B
–VS
4
5
+In B
MSOP-10
+In A
1
10
–In A
DIS A
2
9
Out A
–VS
3
8
+VS
DIS B
4
7
Out B
+In B
5
6
–In B
B83
Pin 1
OPA2683
www.ti.com
SBOS244H
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
RF = 953Ω, RL = 1kΩ, and G = +2 (see Figure 1 for AC performance only), unless otherwise noted.
OPA2683ID, IDCN, IDGS
TYP
PARAMETER
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth (VO = 0.5VPP)
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
Rise-and-Fall Time
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Noninverting Input Current Noise
Inverting Input Current Noise
Differential Gain
Differential Phase
Channel-to-Channel Isolation
DC PERFORMANCE(4)
Open-Loop Transimpedance Gain (ZOL)
Input Offset Voltage
Average Offset Voltage Drift
Noninverting Input Bias Current
Average Noninverting Input Bias Current Drift
Inverting Input Bias Current
Average Inverting Input Bias Current Drift
INPUT
Common-Mode Input Range(5) (CMIR)
Common-Mode Rejection Ratio (CMRR)
Noninverting Input Impedance
Inverting Input Resistance (RI)
OUTPUT
Voltage Output Swing
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
DISABLE (Disabled LOW) (MSOP-10 Only)
Power-Down Supply Current (+VS)
Disable Time
Enable Time
Off Isolation
Output Capacitance in Disable
Turn On Glitch
Turn Off Glitch
Enable Voltage
Disable Voltage
Control Pin Input Bias Current (DIS)
POWER SUPPLY
Specified Operating Voltage
Max Operating Voltage Range
Min Operating Voltage Range
Max Quiescent Current
Min Quiescent Current
Power-Supply Rejection Ratio (–PSRR)
TEMPERATURE RANGE
Specification: D, DCN, DGS
Thermal Resistance, θJA
D
SO-8
DCN SOT23-8
DGS MSOP-10
CONDITIONS
+25°C
G = +1, RF = 953kΩ
G = +2, RF = 953Ω
G = +5, RF = 953Ω
G = +10, RF = 953Ω
G = +20, RF = 953Ω
G = +2, VO = 0.5VPP, RF = 953Ω
RF = 953Ω, VO = 0.5VPP
G = +2, VO = 4VPP
G = –1, VO = 4V Step (see Figure 2)
G = +2, VO = 4V Step
G = +2, VO = 0.5V Step
G = +2, VO = 4V Step
G = +2, f = 5MHz, VO = 2VPP
RL = 100Ω
RL ≥ 1kΩ
RL = 100Ω
RL ≥ 1kΩ
f > 1MHz
f > 1MHz
f > 1MHz
G = +2, NTSC, VO = 1.4VP, RL = 150Ω
G = +2, NTSC, VO = 1.4VP, RL = 150Ω
f = 5MHz
200
150
121
94
72
37
1.8
63
540
400
4.6
7.8
VO = 0V, RL = 1kΩ
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
MIN/MAX OVER TEMPERATURE
+25°C(1)
0°C to
70°C(2)
–40°C to
+85°C(2)
124
121
117
15
6.5
14
7.7
14
8.0
450
345
450
338
430
336
–54
–55
–62
–67
5.0
5.8
11.9
–54
–55
–62
–66
5.5
6.4
12.3
300
typ
min
typ
typ
typ
min
max
typ
min
min
typ
typ
C
B
C
B
C
B
B
C
B
B
C
C
–54
–55
–62
–66
5.8
6.7
12.4
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
%
deg
dB
max
max
max
max
max
max
max
typ
typ
typ
B
B
B
B
B
B
B
C
C
C
270
±4.1
±12
±5.1
±15
±11
±20
250
±4.3
±12
±5.3
±15
±11.5
±20
kΩ
mV
µV/°C
µA
nA/°C
µA
nA°/C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
±3.65
52
±3.60
52
V
dB
kΩ || pF
Ω
min
min
typ
typ
A
A
C
C
120
–100
±4.0
115
–95
±3.9
110
–90
V
mA
mA
Ω
min
min
min
typ
A
A
A
C
–300
–340
–360
3.5
1.7
120
3.6
1.6
130
3.7
1.5
135
µA
ms
ns
dB
pF
mV
mV
V
V
µA
max
typ
typ
typ
typ
typ
typ
min
max
max
A
C
C
C
C
C
C
A
A
A
±6
±6
±6
2.06
1.70
55
2.08
1.6
54
2.10
1.54
54
V
V
V
mA
mA
dB
typ
max
typ
max
min
typ
C
A
C
A
A
A
–40 to +85
°C
typ
C
125
150
140
°C/W
°C/W
°C/W
typ
typ
typ
C
C
C
–63
–71
–67
–77
4.4
5.1
11.6
0.13
0.06
70
±3.5
±2.0
±4.5
±3.0
±10
±3.65
Open-Loop, DC
±3.75
60
50 2
5.0
1kΩ Load
VO = 0
VO = 0
G = +2, f = 100kHz
±4.1
150
–110
0.007
±4.0
VDIS = 0, Both Channel
VIN = +1, See Figure 1
VIN = +1, See Figure 1
G = +2, 5MHz
G = +2, RL = 150Ω, VIN = 0
G = +2, RL = 150Ω, VIN = 0
VDIS = 0V, Each Channel
–200
60
40
70
1.7
±70
±20
3.4
1.8
80
±5
VS = ±5V, Both Channels
VS = ±5V, Both Channels
Input Referred
MIN/ TEST
MAX LEVEL(3)
MHz
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
V/µs
ns
ns
700
±1.5
VCM = 0V
UNITS
±2
1.88
1.88
62
Junction-to-Ambient
53
NOTES: (1) Junction temperature = ambient for +25°C tested specifications.
(2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +2°C at high temperature limit for over-temperature tested
specifications.
(3) Test levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterizationand simulation.
(C) Typical value only for information.
(4) Current is considered positive out-of-node. VCM is the input common-mode voltage.
(5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.
OPA2683
SBOS244H
www.ti.com
3
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
RF = 1.2kΩ, RL = 1kΩ, and G = +2 (see Figure 3 for AC performance only), unless otherwise noted.
OPA2683ID, IDCN, IDGS
TYP
PARAMETER
AC PERFORMANCE (see Figure 3)
Small-Signal Bandwidth (VO = 0.2VPP)
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
Rise-and-Fall Time
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Noninverting Input Current Noise
Inverting Input Current Noise
Differential Gain
Differential Phase
Channel-to-Channel Crosstalk
DC PERFORMANCE(4)
Open-Loop Transimpedance Gain (ZOL)
Input Offset Voltage
Average Offset Voltage Drift
Noninverting Input Bias Current
Average Noninverting Input Bias Current Drift
Inverting Input Bias Current
Average Inverting Input Bias Current Drift
INPUT
Least Positive Input Voltage(5)
Most Positive Input Voltage(5)
Common-Mode Rejection Ratio (CMRR)
Noninverting Input Impedance
Inverting Input Resistance (RI )
OUTPUT
Most Positive Output Voltage
Least Positive Output Voltage
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
DISABLE (Disabled LOW) (MSOP-10 Only)
Power-Down Supply Current (+VS)
Off Isolation
Output Capacitance in Disable
Turn On Glitch
Turn Off Glitch
Enable Voltage
Disable Voltage
Control Pin Input Bias Current (DIS)
POWER SUPPLY
Specified Single-Supply Operating Voltage
Max Single-Supply Operating Voltage
Min Single-Supply Operating Voltage
Max Quiescent Current
Min Quiescent Current
Power-Supply Rejection Ratio (+PSRR)
TEMPERATURE RANGE
Specification: D, DCN, DGS
Thermal Resistance, θJA
D
SO-8
DCN SOT23-8
DGS MSOP-10
CONDITIONS
+25°C
G = +1, RF = 1.2kΩ
G = +2, RF = 1.2kΩ
G = +5, RF = 1.2kΩ
G = +10, RF = 1.2kΩ
G = +20, RF = 1.2kΩ
G = +2, VO < 0.5VPP, RF = 1.2kΩ
RF = 1.2kΩ, VO < 0.5VPP
G = +2, VO = 2VPP
G = +2, VO = 2V Step
G = +2, VO = 0.5V Step
G = +2, VO = 2V Step
G = 2, f = 5MHz, VO = 2VPP
RL = 100Ω to VS/2
RL ≥ 1kΩ to VS/2
RL = 100Ω to VS/2
RL ≥ 1kΩ to VS/2
f > 1MHz
f > 1MHz
f > 1MHz
G = +2, NTSC, VO = 1.4VP, RL = 150Ω
G = +2, NTSC, VO = 1.4VP, RL = 150Ω
f = 5MHz
145
119
95
87
60
14
1
70
210
5.9
7.8
VO = VS/2, RL = 1kΩ to VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
VCM = VS/2
–60
–66
–59
–74
4.4
5.1
11.6
0.24
0.19
70
MIN/MAX OVER TEMPERATURE
+25°C(1)
0°C to
70°C(2)
–40°C to
+85°C(2)
96
92
90
9
6
8
8
8
8
180
175
170
–54
–55
–58
–57
5.0
5.8
11.9
–53
–55
–58
–56
5.5
6.4
12.3
300
UNITS
MIN/ TEST
MAX LEVEL(3)
MHz
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
ns
ns
typ
min
typ
typ
typ
min
max
typ
min
typ
typ
B
C
C
C
B
B
C
B
C
C
–53
–55
–58
–56
5.8
6.7
12.4
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
%
deg
dB
max
max
max
max
max
max
max
typ
typ
type
B
B
B
B
B
B
B
C
C
C
270
±3.6
±12
±5.1
±12
±8.7
±15
250
±3.8
±12
±5.3
±12
±8.9
±15
kΩ
mV
µV/°C
µA
nA/°C
µA
nA°/C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
700
±1.0
±3.0
±2
±4.5
±3
±8
1.25
3.75
51
1.29
3.73
50
1.34
3.67
50
Open-Loop, DC
1.1
3.9
56
50 2
5.6
V
V
dB
kΩ || pF
Ω
max
min
min
typ
typ
A
A
A
C
C
RL = 1kΩ to VS/2
RL = 1kΩ to VS/2
VO = VS/2
VO = VS/2
G = +2, f = 100kHz
4.2
0.8
80
–70
0.009
4.1
0.9
65
–52
4.1
0.9
63
–50
4.0
1.0
58
–45
V
V
mA
mA
Ω
min
max
min
min
typ
A
A
A
A
C
µA
dB
pF
mV
mV
V
V
µA
typ
typ
typ
typ
typ
min
max
max
C
C
C
C
C
A
A
A
V
V
V
mA
mA
dB
typ
max
typ
max
min
typ
C
A
C
A
A
C
–40 to +85
°C
typ
C
125
150
140
°C/W
°C/W
°C/W
typ
typ
typ
C
C
C
VCM = VS/2
VDIS = 0, Both Channels
G = +2, 5MHz
G = +2, RL = 150Ω, VIN = VS/2
G = +2, RL = 150Ω, VIN = VS/2
VDIS = 0V, Each Channel
–200
70
1.7
±70
±20
3.4
1.8
80
3.5
1.7
120
3.6
1.6
130
3.7
1.5
135
+12
+12
+12
1.76
1.36
1.76
1.32
1.76
1.28
+5
VS = +5V, Both Channels
VS = +5V, Both Channels
Input Referred
+4
1.58
1.58
65
Junction-to-Ambient
NOTES: (1) Junction temperature = ambient for +25°C tested specifications.
(2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +2°C at high temperature limit for over-temperature tested
specifications.
(3) Test levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
(4) Current is considered positive out-of-node. VCM is the input common-mode voltage.
(5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.
4
OPA2683
www.ti.com
SBOS244H
TYPICAL CHARACTERISTICS: VS = ±5V
TA = +25°C, G = +2, RF = 953Ω, and RL = 1kΩ, unless otherwise noted.
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
6
6
G = 10 G = 1
3
VO = 0.5VPP
RF = 953Ω
3
G = –1
–3
Normalized Gain (dB)
G = 50
–6
G = 10
–9
G = 50
–12
–15
–6
–9
G = –10
G = –20
–18
1
10
100
200
1
10
100
Frequency (MHz)
Frequency (MHz)
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
9
3
RF = 953Ω
G = +2
0.5VPP
Normalized Gain (dB)
6
3
1VPP
0
See Figure 1
RF = 953Ω
G = –2
200
1VPP
0
0.5VPP
–3
2VPP
–6
5VPP
–9
2VPP
See Figure 2
5VPP
–3
–12
1
10
100
200
1
10
Frequency (MHz)
0.8
G = +2
3.2
Large-Signal Right Scale
0.2
1.6
0.8
Small-Signal Left Scale
0
0
–0.2
–0.8
–0.4
–1.6
–0.6
Output Voltage (200mV/div)
2.4
Output Voltage (800mV/div)
G = –1
0.6
–2.4
0.6
2.4
0.4
1.6
0.2
0.8
0
0
Small-Signal Left Scale
–0.2
–0.8
Large-Signal Right Scale
–0.4
–0.6
See Figure 1
–1.6
–2.4
See Figure 2
–0.8
–3.2
Time (10ns/div)
–0.8
–3.2
Time (10ns/div)
OPA2683
SBOS244H
200
INVERTING PULSE RESPONSE
3.2
0.4
100
Frequency (MHz)
NONINVERTING PULSE RESPONSE
0.8
Output Voltage (200mV/div)
G = –5
–12
See Figure 2
–18
Normalized Gain (dB)
G = –2
–3
–15
G = 100
See Figure 1
0
www.ti.com
5
Output Voltage (800mV/div)
Normalized Gain (dB)
G=2
0
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = +25°C, G = +2, RF = 953Ω, and RL = 1kΩ, unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs FREQUENCY
–50
–50
VO = 2VPP
f = 5MHz
G = +2
–60
–65
VO = 2VPP
RL = 1kΩ
–55
Normalized Distortion (dB)
Harmonic Distortion (dBc)
–55
2nd-Harmonic
–70
–75
–80
3rd-Harmonic
–85
–60
–65
–70
–75
2nd-Harmonic
–80
–85
–90
See Figure 1
–90
100
3rd-Harmonic
See Figure 1
–95
0.1
1k
1
HARMONIC DISTORTION vs OUTPUT VOLTAGE
20
5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
–50
–50
f = 5MHz
RL = 1kΩ
VO = 2VPP
RL = 1kΩ
–55
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
10
Frequency (MHz)
Load Resistance (Ω)
–60
–70
2nd-Harmonic
–80
–60
–65
2nd-Harmonic
–70
–75
3rd-Harmonic
–80
3rd-Harmonic
See Figure 1
–90
See Figure 1
–85
0.1
1
5
2.5
3.0
Output Voltage (VPP)
4.0
4.5
5.0
5.5
6.0
Supply Voltage (±V)
HARMONIC DISTORTION vs NONINVERTING GAIN
HARMONIC DISTORTION vs INVERTING GAIN
–50
–50
VO = 2VPP
RL = 1kΩ
VO = 2VPP
RL = 1kΩ
–55
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
3.5
–60
2nd-Harmonic
–70
3rd-Harmonic
–80
–60
–65
2nd-Harmonic
–70
–75
3rd-Harmonic
–80
–85
See Figure 1
See Figure 2
–90
–90
1
10
1
20
6
10
20
Gain |(–V/V)|
Gain (V/V)
OPA2683
www.ti.com
SBOS244H
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = +25°C, G = +2, RF = 953Ω, and RL = 1kΩ, unless otherwise noted.
2-TONE, 3RD-ORDER
INTERMODULATION DISTORTION
INPUT VOLTAGE AND CURRENT NOISE DENSITY
–45
3rd-Order Spurious Level (dBc)
Inverting Current Noise
11.6pA/√Hz
Noninverting Current Noise
5.2pA/√Hz
10
Voltage Noise
4.4nV/√Hz
1
fO = 20MHz
–50
+5V
–55
PI
50Ω
–60
1kΩ
–5V
953Ω
–65
–70
953Ω
fO = 5MHz
–75
–80
fO = 1MHz
–85
–90
100
1k
10k
100k
1M
0.1
10M
1
Frequency (Hz)
RS vs CLOAD
SMALL-SIGNAL BANDWIDTH vs CLOAD
9
0.5dB Peaking
45
22pF 10pF
RS Adjusted to CLOAD
Normalized Gain (dBc)
40
35
RS (Ω)
2
VPP at 1kΩ Load (Each tone)
50
30
25
20
15
6
100pF
+5V
3
RS
VI
VO
47pF
50Ω OPA2683
CL
0
1kΩ
–5V
953Ω
–3
10
953Ω
5
–6
100k
0
1
10
100
1M
Open-Loop Transimpedance Gain (dBΩ)
CMRR
60
50
+PSRR
40
–PSRR
20
10
0
100
1k
10k
100k
1M
Frequency (Hz)
10M
100M
OPA2683
SBOS244H
100M 1G
OPEN-LOOP TRANSIMPEDANCE GAIN AND PHASE
CMRR AND PSRR vs FREQUENCY
70
30
10M
Frequency (Hz)
CLOAD (pF)
Common-Mode Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
fO = 10MHz
PO
OPA2683
www.ti.com
120
0
20log (ZOL)
100
–30
80
–60
60
–90
∠ ZOL
40
–120
20
–150
0
–180
10k
100k
1M
10M
Frequency (Hz)
100M
1G
7
Open-Loop Phase (°)
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
100
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = +25°C, G = +2, RF = 953Ω, and RL = 1kΩ, unless otherwise noted.
OUTPUT CURRENT AND VOLTAGE LIMITATIONS
COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE
2
0.10
dG
L
3
0.15
=1
00Ω
1W Power
Limit
R
4
VO (V)
=
RL
50
Ω
1
0
–1
–2
0.05
–3
dP
–4
1
2
3
4
Number of 150Ω Video Loads
–150
0
IO (mA)
TYPICAL DC DRIFT OVER TEMPERATURE
SUPPLY AND OUTPUT CURRENT
vs TEMPERATURE
–100
–50
50
100
150
200
4
2.0
Sourcing Output Current
3
2
1
Output Current (mA)
Input Bias Currents (µA)
and Offset Voltage (mV)
1W Power
Limit
Each Channel
–5
0
Noninverting Input Bias Current
0
Input Offset Voltage
–1
–2
175
1.9
Supply Current
Right Scale
150
1.8
Sinking Output Current
125
1.7
–3
Inverting Input Bias Current
100
–4
–50
–25
0
25
50
75
100
1.6
–25
125
0
25
50
75
Ambient Temperature (°C)
Ambient Temperature (°C)
125
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
SETTLING TIME
100
0.05
2V Step
See Figure 1
0.04
0.03
Output Impedance (Ω)
% Error to Final Value
100
0.02
0.01
0
–0.01
–0.02
–0.03
1/2
OPA2683
10
ZO
953Ω
953Ω
1
0.01
–0.04
0.001
–0.05
0
8
10
20
30
Time (ns)
40
50
100
60
1k
10k
100k
1M
10M
100M
Frequency (Hz)
OPA2683
www.ti.com
SBOS244H
Supply Current (mA)
Differential Gain (%)
Differential Phase (°)
Gain = +2
NTSC, Positive Video
RL = 500Ω
5
0.20
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = +25°C, G = +2, RF = 953Ω, and RL = 1kΩ, unless otherwise noted.
8.0
3.2
6.4
6.4
6.4
2.4
4.8
4.8
4.8
1.6
3.2
0.8
1.6
0
0
Output Voltage
Right Scale
–0.8
–1.6
See Figure 1
–1.6
–2.4
–3.2
–4.8
Input Voltage
Left Scale
–3.2
–4.0
Input Voltage (1.6V/div)
8.0
3.2
3.2
Output Voltage
Right Scale
1.6
0
–1.6
–1.6
–3.2
–3.2
–4.8
–6.4
–6.4
–8.0
–8.0
–8.0
CHANNEL-TO-CHANNEL CROSSTALK
0
Input Referred
–10
Input
Voltage
Range
Harmonic Distortion (dBc)
Input and Output Voltage Range
–6.4
See Figure 2
Time (100ns/div)
INPUT AND OUTPUT RANGE vs SUPPLY VOLTAGE
Output
Voltage
Range
–20
–30
–40
–50
–60
–70
–80
–90
±2
±3
±4
±5
±6
1M
10M
± Supply Voltage
100M
Frequency (Hz)
DISABLE SUPPLY CURRENT vs TEMPERATURE
DISABLE TIME
290
6
Both Channels
270
VDIS
5
250
VOUT and VDIS (V)
Disable Supply Current (µA)
–4.8
Input Voltage
Left Scale
Time (100ns/div)
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
1.6
0
230
210
190
VIN = 1VDC
See Figure 1
4
3
2
VOUT
1
170
150
0
50
25
0
25
50
75
100
125
10
20
30
40
50
60
70
80
90
100
Time (ms)
Ambient Temperature (°C)
OPA2683
SBOS244H
0
www.ti.com
9
Input Voltage (1.6V/div)
INVERTING OVERDRIVE RECOVERY
8.0
Output Voltage (1.6V/div)
Input Voltage (0.8V/div)
NONINVERTING OVERDRIVE RECOVERY
4.0
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = +25°C, G = +2, RF = 953Ω, and RL = 1kΩ, unless otherwise noted.
DISABLED FEEDTHRU
–40
G = +2
VDIS = 0V
Feedthru (dB)
–50
Each Channel
–60
–70
–80
–90
See Figure 1
–100
0.1
1
10
100
Frequency (MHz)
10
OPA2683
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SBOS244H
TYPICAL CHARACTERISTICS: VS = +5V
TA = +25°C, VS = 5V, G = +2, RF = 1.2kΩ, and RL = 1kΩ, unless otherwise noted.
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
6
6
G=2
3
G=1
0
Normalized Gain (dB)
Normalized Gain (dB)
3
G=5
–3
G = 10
–6
G = 20
–9
G = 50
–12
0
G = –1
–3
–6
G = –5
–9
G = –10
–12
G = –20
–15
–15
G = –2
See Figure 4
G = 100
See Figure 3
–18
–18
1
10
100
1
200
10
Frequency (MHz)
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
9
200
3
0.2VPP
0.2VPP
0.5VPP
6
0
1VPP
Gain (dB)
Gain (dB)
100
Frequency (MHz)
1VPP
3
2VPP
–3
0.5VPP
2VPP
–6
0
–9
See Figure 4
See Figure 3
–3
–12
10
100
200
1
10
Frequency (MHz)
0.4
1.6
1.2
0.3
1.2
0.2
0.8
0.1
0.4
0.8
0.1
0.4
Small-Signal Left Scale
0
0
–0.1
–0.4
–0.2
–0.8
–0.3
Output Voltage (100mV/div)
0.2
1.6
Output Voltage (400mV/div)
Output Voltage (100mV/div)
Large-Signal Right Scale
0.3
–1.2
0
0
Small-Signal Left Scale
–0.1
–0.4
Large-Signal Right Scale
–0.2
–0.3
See Figure 3
–0.8
–1.2
See Figure 4
–0.4
–1.6
–0.4
–1.6
Time (10ns/div)
Time (10ns/div)
OPA2683
SBOS244H
200
INVERTING PULSE RESPONSE
NONINVERTING PULSE RESPONSE
0.4
100
Frequency (MHz)
www.ti.com
11
Output Voltage (400mV/div)
1
TYPICAL CHARACTERISTICS: VS = +5V (Cont.)
TA = +25°C, VS = 5V, G = +2, RF = 1.2kΩ, and RL = 1kΩ, unless otherwise noted.
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION vs LOAD RESISTANCE
–50
–50
f = 5MHz
VO = 2VPP
VO = 2VPP
RL = 1kΩ
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–55
2nd-Harmonic
–60
–65
3rd-Harmonic
–70
–75
–80
–60
2nd-Harmonic
–70
3rd-Harmonic
–80
–85
See Figure 3
See Figure 3
–90
–90
100
0.1
1k
1
10
Load Resistance (Ω)
Frequency (MHz)
HARMONIC DISTORTION vs OUTPUT VOLTAGE
2-TONE, 3RD-ORDER
INTERMODULATION DISTORTION
20
–40
–50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–55
–60
–65
–70
–75
3rd-Harmonic
–80
2nd-Harmonic
–85
–50
20MHz
–60
10MHz
–70
5MHz
–80
See Figure 3
See Figure 3
–90
–90
0.1
1
3
1
0.1
Output Voltage (VPP)
VPP at 1kΩ Load (each tone)
SUPPLY AND OUTPUT CURRENT
vs TEMPERATURE
COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE
Sourcing Output Current
Left Scale
80
Supply Current
Right Scale
1.8
0.25
1.7
1.6
70
Left Scale
Sinking Output Current
1.5
60
1.4
50
–50
12
0.30
Differential Gain (%)
Differential Phase (°)
Output Current (mA)
90
1.9
Supply Current (mA)
100
–25
0
25
50
75
Ambient Temperature (°C)
100
G = +2
NTSC, Positive Video
0.20
dG
0.15
0.10
dP
0.05
0
1
125
2
3
4
Number of 150Ω Video Loads
OPA2683
www.ti.com
SBOS244H
APPLICATIONS INFORMATION
LOW-POWER, CURRENT-FEEDBACK OPERATION
The dual channel OPA2683 gives a new level of performance in low-power, current-feedback op amps. Using a
new input stage buffer architecture, the OPA2683 CFBPLUS
amplifier holds nearly constant AC performance over a wide
gain range. This closed-loop internal buffer gives a very low
and linearized impedance at the inverting node, isolating the
amplifier’s AC performance from gain element variations.
This low impedance allows both the bandwidth and distortion
to remain nearly constant over gain, moving closer to the
ideal current- feedback performance of gain bandwidth independence. This low-power amplifier also delivers exceptional
output power—its ±4V swing on ±5V supplies with > 100mA
output drive gives excellent performance into standard video
loads or doubly-terminated 50Ω cables. This dual-channel
device can provide adequate drive for several emerging
differential driver applications with exceptional power efficiency. Single +5V supply operation is also supported with
similar bandwidths but reduced output power capability. For
higher output power in a dual current-feedback op amp,
consider the OPA2684, OPA2691, or OPA2677.
Figure 2 shows the DC-coupled, gain of –1V/V, dual powersupply circuit used as the basis of the inverting Typical
Characteristics for each channel. Inverting operation offers
several performance benefits. Since there is no commonmode signal across the input stage, the slew rate for inverting
operation is typically higher and the distortion performance is
slightly improved. An additional input resistor, RM, is included
in Figure 2 to set the input impedance equal to 50Ω. The
parallel combination of RM and RG set the input impedance.
As the desired gain increases for the inverting configuration,
RG is adjusted to achieve the desired gain, while RM is also
adjusted to hold a 50Ω input match. A point will be reached
where RG will equal 50Ω, RM is removed, and the input match
is set by RG only. With RG fixed to achieve an input match to
50Ω, increasing RF will increase the gain. However, this will
reduce the achievable bandwidth as the feedback resistor
increases from its recommended value of 953Ω. If the source
does not require an input match to 50Ω, either adjust RM to
get the desired load, or remove it and let the RG resistor
alone provide the input load.
+5V
Figure 1 shows the DC-coupled, gain of +2, dual powersupply circuit used as the basis of the ±5V Electrical and
Typical Characteristics for each channel. For test purposes,
the input impedance is set to 50Ω with a resistor to ground,
and the output impedance is set to a 1kΩ load. Voltage
swings reported in the characteristics are taken directly at the
input and output pins. For the circuit of Figure 1, the total
effective load will be 1kΩ || 1.9kΩ = 656Ω. Gain changes are
most easily accomplished by simply resetting the RG value,
holding RF constant at its recommended value of 953Ω.
0.1µF
50Ω Source
RG
953Ω
RF
953Ω
VI
+
+
6.8µF
FIGURE 2. DC-Coupled, G = –1V/V, Bipolar Supply Specifications and Test Circuit.
6.8µF
These circuits show ±5V operation. The same circuit can be
applied with bipolar supplies from ±2.5V to ±6V. Internal
supply independent biasing gives nearly the same performance for the OPA2683 over this wide range of supplies.
Generally, the optimum feedback resistor value (for nominally flat frequency response at G = +2) will increase in value
as the total supply voltage across the OPA2683 is reduced
from ±5V.
VI
1/2
OPA2683
VO
1kΩ
RF
953Ω
0.1µF
+
6.8µF
–5V
FIGURE 1. DC-Coupled, G = +2V/V, Bipolar Supply Specifications and Test Circuit.
See Figure 3 for the AC-coupled, single +5V supply, gain of
+2V/V circuit configuration used as a basis only for the +5V
Electrical and Typical Characteristics for each channel. The
key requirement of broadband single-supply operation is to
maintain input and output signal swings within the usable
voltage ranges at both the input and the output. The circuit
of Figure 3 establishes an input midpoint bias using a simple
resistive divider from the +5V supply (two 10kΩ resistors) to
the noninverting input. The input signal is then AC-coupled
OPA2683
SBOS244H
0.1µF
–5V
0.1µF
RG
953Ω
VO
1kΩ
+5V
RM
50Ω
6.8µF
1/2
OPA2683
RM
52.3Ω
50Ω Source
+
www.ti.com
13
into this midpoint voltage bias. The input voltage can swing
to within 1.25V of either supply pin, giving a 2.5VPP input
signal range centered between the supply pins. The input
impedance of Figure 3 is set to give a 50Ω input match. If the
source does not require a 50Ω match, remove this and drive
directly into the blocking capacitor. The source will then see
the 5kΩ load of the biasing network. The gain resistor (RG)
is AC-coupled, giving the circuit a DC gain of +1, which puts
the noninverting input DC bias voltage (2.5V) on the output
as well. The feedback resistor value has been adjusted from
the bipolar ±5V supply condition to re-optimize for a flat
frequency response in +5V only, gain of +2, operation. On a
single +5V supply, the output voltage can swing to within
0.9V of either supply pin while delivering more than 70mA
output current, giving 3.2V output swing into 100Ω (8dBm
maximum at a matched 50Ω load). The circuit of Figure 3
shows a blocking capacitor driving into a 1kΩ load. Alternatively, the blocking capacitor could be removed if the load is
tied to a supply midpoint or to ground if the DC current
required by the load is acceptable.
a current-feedback amplifier, wideband operation is retained
even under this condition.
The circuits of Figure 3 and 4 show single-supply operation
at +5V. These same circuits may be used up to single
supplies of +12V with minimal change in the performance of
the OPA2683.
+5V
0.1µF
+
6.8µF
10kΩ
0.1µF
0.1µF
10kΩ
1/2
OPA2683
VO
1kΩ
50Ω Source
RF
1.2kΩ
RG
0.1µF 1.2kΩ
VI
RM
52.3Ω
+5V
0.1µF
50Ω Source
+
FIGURE 4. AC-Coupled, G = –1V/V, Single-Supply Specifications and Test Circuit.
6.8µF
10kΩ
0.1µF
DIFFERENTIAL INTERFACE APPLICATIONS
VI
0.1µF
RM
50Ω
10kΩ
1/2
OPA2683
VO
1kΩ
RF
1.2kΩ
RG
1.2kΩ
0.1µF
Dual op amps are particularly suitable to differential input to
differential output applications. Typically, these fall into either
Analog-to-Digital Converter (ADC) input interfaces or line
driver applications. Two basic approaches to differential I/O
are noninverting or inverting configurations. Since the output
is differential, the signal polarity is somewhat meaningless—
the noninverting and inverting terminology applies here to
where the input is brought into the OPA2683. Each has its
advantages and disadvantages. Figure 5 shows a basic
starting point for noninverting differential I/O applications.
FIGURE 3. AC-Coupled, G = +2V/V, Single-Supply Specifications and Test Circuit.
+VCC
Figure 4 shows the AC-coupled, single +5V supply, gain of
–1V/V circuit configuration used as a basis for the +5V
Typical Characteristics for each channel. In this case, the
midpoint DC bias on the noninverting input is also decoupled
with an additional 0.1µF decoupling capacitor. This reduces
the source impedance at higher frequencies for the
noninverting input bias current noise. This 2.5V bias on the
noninverting input pin appears on the inverting input pin and,
since RG is DC blocked by the input capacitor, will also
appear at the output pin. One advantage to inverting operation is that since there is no signal swing across the input
stage, higher slew rates and operation to even lower supply
voltages is possible. To retain a 1VPP output capability,
operation down to 3V supply is allowed. At +3V supply, the
input stage is saturated, but for the inverting configuration of
1/2
OPA2683
RF
953Ω
VI
RG
RF
953Ω
VO
1/2
OPA2683
–VCC
FIGURE 5. Noninverting Differential I/O Amplifier.
14
OPA2683
www.ti.com
SBOS244H
This approach provides for a source termination impedance
that is independent of the signal gain. For instance, simple
differential filters may be included in the signal path right up
to the noninverting inputs without interacting with the gain
setting. The differential signal gain for the circuit of Figure 5 is:
(1)
AD = 1 + 2 • RF /RG
Since the OPA2683 is a CFBPLUS amplifier, its bandwidth is
principally controlled with the feedback resistor value; see
Figure 5 for the recommended value of 953Ω. The differential
gain, however, may be adjusted with considerable freedom
using just the RG resistor. In fact, RG may be a reactive
network providing a very isolated shaping to the differential
frequency response. Since the inverting inputs of the OPA2683
are very low impedance closed-loop buffer outputs, the RG
element does not interact with the amplifier’s bandwidth;
wide ranges of resistor values and/or filter elements may be
inserted here with minimal amplifier bandwidth interaction.
Various combinations of single-supply or AC-coupled gain
can also be delivered using the basic circuit of Figure 5.
Common-mode bias voltages on the two noninverting inputs
pass on to the output with a gain of 1 since an equal DC
voltage at each inverting node creates no current through
RG. This circuit does show a common-mode gain of 1 from
input to output. The source connection should either remove
this common-mode signal if undesired (using an input transformer can provide this function), or the common-mode
voltage at the inputs can be used to set the output commonmode bias. If the low common-mode rejection of this circuit
is a concern, the output interface may also be used to reject
that common-mode. For instance, most modern differential
input ADCs reject common-mode signals very well, while a
line driver application through a transformer will also attenuate the common-mode signal through to the line.
The two noninverting inputs provide an easy common-mode
control input. This is particularly simple if the source is
AC-coupled through either blocking caps or a transformer.
In either case, the common-mode input voltages on the two
noninverting inputs again have a gain of 1 to the output pins,
giving particularly easy common-mode control for singlesupply operation. The OPA2683 used in this configuration
does constrain the feedback to the 953Ω region for best
frequency response. With RF fixed, the input resistors may be
adjusted to the desired gain but will also be changing the
input impedance as well. The high-frequency common-mode
gain for this circuit from input to output will be the same as
for the signal gain. Again, if the source might include an
undesired common-mode signal, that signal could be rejected at the input using blocking caps (for low frequency and
DC common-mode) or a transformer coupling.
DC-COUPLED SINGLE TO DIFFERENTIAL CONVERSION
The previous differential output circuits were also set up to
receive a differential input. A simple way to provide a DCcoupled single to differential conversion using a dual op amp
is shown in Figure 7. Here, the output of the first stage is
simply inverted by the second to provide an inverting version
of a single amplifier design. This approach works well for
lower frequencies but will start to depart from ideal differential
outputs as the propagation delay and distortion of the inverting stage adds significantly to that present at the noninverting
output pin.
+5V
1VPP
50Ω
Figure 6 shows a differential I/O stage configured as an
inverting amplifier. In this case, the gain resistors (RG)
become part of the input resistance for the source. This
provides a better noise performance than the noninverting
configuration but does limit the flexibility in setting the input
impedance separately from the gain.
1/2
OPA2683
953Ω
191Ω
953Ω
12VPP Differential
953Ω
+VCC
VCM
1/2
OPA2683
1/2
OPA2683
VI
RG
RF
953Ω
RG
RF
953Ω
1/2
OPA2683
VCM
–VCC
FIGURE 6. Inverting Differential I/O Amplifier.
–5V
VO
FIGURE 7. Single to Differential Conversion.
The circuit of Figure 7 is set up for a single-ended gain of 6
to the output of the first amplifier, then an inverting gain of
–1 through the second stage to provide a total differential
gain of 12. See Figure 8 for the 75MHz small-signal bandwidth delivered by the circuit of Figure 7. Large-signal distortion at 12VPP output at 1MHz into the 1kΩ differential load is
≤ –76dBc.
OPA2683
SBOS244H
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15
of Figure 9 designs the filter for a differential gain of 5 using
the OPA2683. The resistor values have been adjusted slightly
to account for the amplifier bandwidth effects.
SINGLE TO DIFFERENTIAL CONVERSION
24
While this circuit is bipolar, using ±5V supplies, it can easily
be adapted to single-supply operation. This is typically done
by providing a supply midpoint reference at the noninverting
inputs, then adding DC blocking caps at each input and in
series with the amplifier gain resistor, RG. This will add two
real zeroes in the response, transforming the circuit into a
bandpass. Figure 10 shows the frequency response for the
filter of Figure 9.
21
Gain (dB)
18
15
12
9
6
3
1
10
100
200
10MHz, 3RD-ORDER BUTTERWORTH LOW PASS
FREQUENCY RESPONSE
Frequency (MHz)
14
FIGURE 8. Small-Signal Bandwidth for Figure 7.
Differential Gain (dB)
11
DIFFERENTIAL ACTIVE FILTER
The OPA2683 can provide a very capable gain block for lowpower active filters. The dual design lends itself very well to
differential active filters. Where the filter topology is looking
for a simple gain function to implement the filter, the
noninverting configuration is preferred to isolate the filter
elements from the gain elements in the design. Figure 9
shows an example of a very low-power, 10MHz, 3rd-order
Butterworth low-pass Sallen-Key filter. Often, these filters are
designed at an amplifier gain of 1 to minimize amplifier
bandwidth interaction with the desired filter shape. Since the
OPA2683 shows minimal bandwidth change with gain, this
feature would not be a constraint in this design. The example
8
5
2
–1
–4
1
10
20
Frequency (MHz)
FIGURE 10. Frequency Response for 10MHz, 3rd-Order
Butterworth Low-Pass Filter.
100pF
47Ω
183Ω
+5V
20Ω
1/2
OPA2683
75pF
VI
47Ω
183Ω
953Ω
357Ω
953Ω
357Ω
RG
475Ω
22pF
VO
1/2
OPA2683
20Ω
100pF
–5V
FIGURE 9. Low-Power, Differential I/O, 4th-Order Butterworth Active Filter.
16
OPA2683
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SINGLE-SUPPLY, HIGH GAIN DIFFERENTIAL
ADC DRIVER
+5V
Where a very low-power differential I/O interface to a moderate performance ADC is required, the circuit of Figure 11 may
be considered. The circuit builds on the inverting differential
I/O configuration of Figure 6 by adding the input transformer
and the output low-pass filter. The input transformer provides
a single-to-differential conversion where the input signal is
still very low power—it also provides a gain of 2 and removes
any common-mode signal from the inputs. This single +5V
design sets a midpoint bias from the supply at each of the
noninverting inputs.
VDIS
Power-Supply
Decoupling
Not Shown
+5V
U1
CH0
75Ω
78.7Ω
1/2
OPA2683
VOUT
75Ω Line
681Ω
953Ω
CH1
+5V
75Ω
78.7Ω
1/2
OPA2683
VOUT
10kΩ
75Ω Line
VCM
681Ω
0.1µF
10kΩ
1/2
OPA2683
953Ω
ADC
500Ω (Optional)
200Ω
800Ω
RS
200Ω
800Ω
RS
1:2
50Ω
Source
+5V
U2
CL
CH0
75Ω
15.3dB
Noise Figure
Gain = 8V/V
18.1dB
1/2
OPA2683
78.7Ω
1/2
OPA2683
681Ω
VCM
953Ω
500Ω (Optional)
FIGURE 11. Single-Supply Differential ADC Driver.
CH1
75Ω
This circuit also includes optional 500Ω pull-down resistors at
the output. With a 2.5V DC common-mode operating point
(set by VCM), this will add 5mA to ground in the output stage.
This essentially powers up the NPN side of the output stage
significantly reducing distortion. It is important for good 2ndorder distortion to connect the grounds of these two resistors
at the same point to minimize ground plane current for the
differential output signal.
LOW-POWER MUX/LINE DRIVER
Using the shutdown feature, two OPA2683s can provide an
easy low-power way to select one of two possible sources for
moderate-resolution monitors. Figure 12 shows a recommended circuit where each of the outputs are combined in a
way that provides a net gain of 1 to the matched 75Ω load
with a 75Ω output impedance. This brings the two outputs for
each color together through a 78.7Ω resistor with a slightly
> 2 gain provided by the amplifiers. When one channel is
shutdown, the feedback network is still present, slightly
attenuating the signal and combining in parallel with the
78.7Ω to give a 75Ω source impedance.
681Ω
78.7Ω
953Ω
FIGURE 12. Frequency Response for 10MHz, 3rd-Order
Butterworth Low-Pass Filter.
Since the OPA2683 does not disable quickly, this approach
is not suitable for pixel-by-pixel multiplexing—however, it
does provide an easy way to switch between two possible
RGB sources. The output swing provided by the active
channel will divide back through the inactive channel feedback to appear at the inverting input of the OFF channel. To
retain good pulse fidelity, or low distortion, this divided down
output signal at the inverting inputs of the OFF channels, plus
the OFF channel input signals, should not exceed 0.7VPP. As
the signal across the buffers of the inactive channels exceeds 0.7VPP, diodes across the inputs may begin to turn on
causing a nonlinear load to the active channel. This will
degrade signal linearity under those conditions.
OPA2683
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OPA2683
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17
DESIGN-IN TOOLS
OPERATING SUGGESTIONS
DEMONSTRATION FIXTURES
SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH
Two printed circuit boards (PCBs) are available to assist in
the initial evaluation of circuit performance using the OPA2683
in its two package options. Both of these are offered free of
charge as unpopulated PCBs, delivered with a user’s guide.
The summary information for these fixtures is shown in
Table I.
Any current-feedback op amp like the OPA2683 can hold
high bandwidth over signal-gain settings with the proper
adjustment of the external resistor values. A low-power part
like the OPA2683 typically shows a larger change in bandwidth due to the significant contribution of the inverting input
impedance to loop-gain changes as the signal gain is changed.
Figure 13 shows a simplified analysis circuit for any currentfeedback amplifier.
PRODUCT
OPA2683ID
OPA2683IDCN
OPA2683IDGS
PACKAGE
ORDERING
NUMBER
LITERATURE
NUMBER
SO-8
SOT23-8
MSOP-10
DEM-OPA-SO-2A
DEM-OPA-SOT-2A
DEM-OPA-MSOP-2B
SBOU003
SBOU001
SBOU040
VI
TABLE I. Demonstration Fixtures by Package.
α
VO
The demonstration fixtures can be requested at the Texas
Instruments web site (www.ti.com) through the OPA2683
product folder.
RI
iERR
Z(S) iERR
RF
MACROMODELS
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for higher speed
designs where parasitic capacitance and inductance can
have a major effect on circuit performance. A SPICE model
for the OPA683 is available in the product folder on the TI
web site (www.ti.com). This is the single channel model for
the OPA2683—simply use two of these to implement an
OPA2683 simulation. These models do a good job of predicting small-signal AC and transient performance under a wide
variety of operating conditions. However, they are less accurate in predicting the harmonic distortion or dG/dP characteristics. These models do not attempt to distinguish between
the package types in their small-signal AC performance.
18
RG
FIGURE 13. Current-Feedback Transfer Function Analysis
Circuit.
The key elements of this current-feedback op amp model are:
α ⇒ Buffer gain from the noninverting input to the inverting input
RI ⇒ Buffer output impedance
iERR ⇒ Feedback error current signal
Z(s) ⇒ Frequency dependent open-loop transimpedance
gain from iERR to VO
OPA2683
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SBOS244H
The buffer gain is typically very close to 1.00 and is normally
neglected from signal gain considerations. It will, however, set
the CMRR for a single op amp differential amplifier configuration. For the buffer gain α < 1.0, the CMRR = –20 • log(1 – α).
The closed-loop input stage buffer used in the OPA2683 gives
a buffer gain more closely approaching 1.00 and this shows up
in a slightly higher CMRR than previous current-feedback op
amps.
RI, the buffer output impedance, is a critical portion of the
bandwidth control equation. The OPA2683 reduces this
element to approximately 5.0Ω using the loop gain of the
closed-loop input buffer stage. This significant reduction in
output impedance, on very low power, contributes significantly to extending the bandwidth at higher gains.
A current-feedback op amp senses an error current in the
inverting node (as opposed to a differential input error voltage for a voltage-feedback op amp) and passes this on to
the output through an internal frequency dependent
transimpedance gain. The Typical Characteristics show this
open-loop transimpedance response. This is analogous to
the open-loop voltage gain curve for a voltage-feedback op
amp. Developing the transfer function for the circuit of Figure
13 gives Equation 2:

R 
α 1 + F 
R

VO
α NG
G
=
=
VI

RF  1 + RF + RI NG
RF + RI 1 +

Z (S )
 RG 
1+
Z (S )


R 
NG = 1 + F  
 R G  

(2)
This is written in a loop-gain analysis format where the errors
arising from a non-infinite open-loop gain are shown in the
denominator. If Z(S) were infinite over all frequencies, the
denominator of Equation 2 would reduce to 1 and the ideal
desired signal gain shown in the numerator would be achieved.
The fraction in the denominator of Equation 2 determines the
frequency response. Equation 3 shows this as the loop-gain
equation.
Z (S )
RF + RI NG
= Loop Gain
(3)
If 20 • log(RF + NG • RI) were drawn on top of the open-loop
transimpedance plot, the difference between the two would
be the loop gain at a given frequency. Eventually, Z(S) rolls off
to equal the denominator of Equation 3, at which point the
loop gain has reduced to 1 (and the curves have intersected).
This point of equality is where the amplifier’s closed-loop
frequency response given by Equation 2 will start to roll off,
and is exactly analogous to the frequency at which the noise
gain equals the open-loop voltage gain for a voltage-feedback op amp. The difference here is that the total impedance
in the denominator of Equation 3 may be controlled somewhat separately from the desired signal gain (or NG).
The OPA2683 is internally compensated to give a maximally
flat frequency response for RF = 953Ω at NG = 2 on ±5V
supplies. That optimum value goes to 1.2kΩ on a single +5V
supply. Normally, with a current-feedback amplifier, it is
possible to adjust the feedback resistor to hold this bandwidth up as the gain is increased. The CFBPLUS architecture
has reduced the contribution of the inverting input impedance
to provide exceptional bandwidth to higher gains without
adjusting the feedback resistor value. The Typical Characteristics show the small-signal bandwidth over gain with a fixed
feedback resistor.
Putting a closed-loop buffer between the noninverting and
inverting inputs does bring some added considerations. Since
the voltage at the inverting output node is now the output of
a locally closed-loop buffer, parasitic external capacitance on
this node can cause frequency response peaking for the
transfer function from the noninverting input voltage to the
inverting node voltage. While it is always important to keep
the inverting node capacitance low for any current-feedback
op amp, it is critically important for the OPA2683. External
layout capacitance in excess of 2pF will start to peak the
frequency response. This peaking can be easily reduced by
then increasing the feedback resistor value—but it is preferable, from a noise and dynamic range standpoint, to keep
that capacitance low, allowing a close to nominal 953Ω
feedback resistor for flat frequency response. Very high
parasitic capacitance values on the inverting node (> 5pF)
can possibly cause input stage oscillation that cannot be
filtered by a feedback element adjustment.
An added consideration is that at very high gains, 2nd-order
effects in the inverting output impedance cause the overall
response to peak up. If desired, it is possible to retain a flat
frequency response at higher gains by adjusting the feedback resistor to higher values as the gain is increased. Since
the exact value of feedback that will give a flat frequency
response at high gains depends strongly in inverting and
output node parasitic capacitance values, it is best to experiment in the specific board with increasing values until the
desired flatness (or pulse response shape) is obtained. In
general, increasing RF (and then adjusting RG to the desired
gain) will move towards flattening the response, while decreasing it will extend the bandwidth at the cost of some
peaking. The OPA683 data sheet gives an example of this
optimization of RF versus gain.
OPA2683
SBOS244H
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19
OUTPUT CURRENT AND VOLTAGE
DRIVING CAPACITIVE LOADS
The OPA2683 provides output voltage and current capabilities that can support the needs of driving doubly-terminated
50Ω lines. If the 1kΩ load of Figure 1 is changed to a 100Ω
load, the total load is the parallel combination of the 100Ω
load, and the 1.9kΩ total feedback network impedance. This
95Ω load will require no more than 42mA output current to
support the ±4.0V minimum output voltage swing specified
for 1kΩ loads. This is well below the specified minimum
+120/–90mA specifications over the full temperature range.
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC, including additional
external capacitance which may be recommended to improve ADC linearity. A high-speed, high open-loop gain
amplifier like the OPA2683 can be very susceptible to decreased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier’s open-loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem have been suggested. When the
primary considerations are frequency response flatness, pulse
response fidelity, and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole,
thus increasing the phase margin and improving stability.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage • current, or V-I product,
which is more relevant to circuit operation. Refer to the
Output Voltage and Current Limitations plot in the Typical
Characteristics. The X- and Y-axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA2683’s output drive capabilities.
Superimposing resistor load lines onto the plot shows the
available output voltage and current for specific loads.
The minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
electrical characteristic tables. As the output transistors deliver power, their junction temperatures will increase, decreasing their VBEs (increasing the available output voltage
swing) and increasing their current gains (increasing the
available output current). In steady-state operation, the available output voltage and current will always be greater than
that shown in the over-temperature specifications since the
output stage junction temperatures will be higher than the
minimum specified operating ambient.
To maintain maximum output stage linearity, no output shortcircuit protection is provided. This will not normally be a
problem, since most applications include a series matching
resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground.
However, shorting the output pin directly to the adjacent
positive power-supply pin can destroy the amplifier. If additional short-circuit protection is required, consider a small
series resistor in the power-supply leads. This resistor will,
under heavy output loads, reduce the available output voltage swing. A 5Ω series resistor in each power-supply lead
will limit the internal power dissipation to less than 1W for an
output short-circuit, while decreasing the available output
voltage swing only 0.25V for up to 50mA desired load
currents. Always place the 0.1µF power-supply decoupling
capacitors after these supply current limiting resistors directly
on the supply pins.
20
The Typical Characteristics show the recommended RS vs
CLOAD and the resulting frequency response at the load. The
1kΩ resistor shown in parallel with the load capacitor is a
measurement path and may be omitted. The required series
resistor value may be reduced by increasing the feedback
resistor value from its nominal recommended value. This will
increase the phase margin for the loop gain, allowing a lower
series resistor to be effective in reducing the peaking due to
capacitive load. SPICE simulation can be effectively used to
optimize this approach. Parasitic capacitive loads greater
than 5pF can begin to degrade the performance of the
OPA2683. Long PC board traces, unmatched cables, and
connections to multiple devices can easily cause this value
to be exceeded. Always consider this effect carefully, and
add the recommended series resistor as close as possible to
the OPA2683 output pin (see Board Layout Guidelines).
OPA2683
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SBOS244H
DISTORTION PERFORMANCE
The OPA2683 provides very low distortion in a low-power
part. The CFBPLUS architecture also gives two significant
areas of distortion improvement. First, in operating regions
where the 2nd-harmonic distortion due to output stage
nonlinearities is very low (frequencies < 1MHz, low output
swings into light loads) the linearization at the inverting node
provided by the CFBPLUS design gives 2nd-harmonic distortions that extend into the –90dBc region. Previous currentfeedback amplifiers have been limited to approximately
–85dBc due to the nonlinearities at the inverting input. The
second area of distortion improvement comes in a distortion
performance that is largely gain independent. To the extent
that the distortion at a specific output power is output stage
dependent, 3rd-harmonics particularly, and to a lesser extend 2nd-harmonic distortion, remains constant as the gain
increases. This is due to the constant loop gain versus signal
gain provided by the CFBPLUS design. As shown in the
Typical Characteristics, while the 3rd-harmonic is constant
with gain, the 2nd-harmonic degrades at higher gains. This
is largely due to board parasitic issues. Slightly imbalanced
load return currents will couple into the gain resistor to cause
a portion of the 2nd-harmonic distortion. At high gains, this
imbalance has more gain to the output giving increased
2nd-harmonic distortion.
Relative to alternative amplifiers with < 2mA supply current,
the OPA2683 holds much lower distortion at higher frequencies (> 5MHz) and to higher gains. Generally, until the
fundamental signal reaches very high frequency or power
levels, the 2nd-harmonic will dominate the distortion with a
lower 3rd-harmonic component. Focusing then on the 2ndharmonic, increasing the load impedance improves distortion
directly. Remember that the total load includes the feedback
network—in the noninverting configuration (see Figure 1) this
is the sum of RF + RG, while in the inverting configuration it
is just RF. Also, providing an additional supply decoupling
capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB).
In most op amps, increasing the output voltage swing increases harmonic distortion directly. A low-power part like
the OPA2683 includes quiescent boost circuits to provide the
full-power bandwidth shown in the Typical Characteristics.
These act to increase the bias in a very linear fashion only
when high slew rate or output power are required. This also
acts to actually reduce the distortion slightly at higher output
power levels. The Typical Characteristics show the 2ndharmonic holding constant from 500mVPP to 5VPP outputs
while the 3rd-harmonics actually decrease with increasing
output power.
The OPA2683 has an extremely low 3rd-order harmonic
distortion, particularly for light loads and at lower frequencies. This also gives low 2-tone, 3rd-order intermodulation
distortion as shown in the Typical Characteristics. Since the
OPA2683 includes internal power boost circuits to retain
good full-power performance at high frequencies and outputs, it does not show a classical 2-tone, 3rd-order intermodulation intercept characteristic. Instead, it holds relatively
low and constant 3rd-order intermodulation spurious levels
over power. The Typical Characteristics show this spurious
level as a dBc below the carrier at fixed center frequencies
swept over single-tone power at a matched 50Ω load. These
spurious levels drop significantly (> 12dB) for lighter loads
than the 100Ω used in that plot. Converter inputs, for instance, will see ≤ 82dBc 3rd-order spurious to 10MHz for fullscale inputs. For even lower 3rd-order intermodulation distortion to much higher frequencies, consider the OPA2691.
NOISE PERFORMANCE
Wideband current-feedback op amps generally have a higher
output noise than comparable voltage-feedback op amps.
The OPA2683 offers an excellent balance between voltage
and current noise terms to achieve low output noise in a lowpower amplifier. The inverting current noise (11.6pA/√Hz) is
lower than most other current-feedback op amps while the
input voltage noise (4.4nV/√Hz) is lower than any unity-gain
stable, comparable slew rate, < 5mA/ch voltage-feedback op
amp. This low input voltage noise was achieved at the price
of higher noninverting input current noise (5.1pA/√Hz). As
long as the AC source impedance looking out of the
noninverting node is less than 200Ω, this current noise will
not contribute significantly to the total output noise. The op
amp input voltage noise and the two input current noise
terms combine to give low output noise under a wide variety
of operating conditions. Figure 14 shows the op amp noise
analysis model with all the noise terms included. In this
model, all noise terms are taken to be noise voltage or
current density terms in either nV/√Hz or pA/√Hz.
ENI
1/2
OPA2683
RS
EO
IBN
ERS
RF
√4kTRS
4kT
RG
RG
IBI
√4kTRF
4kT = 1.6E –20J
at 290°K
FIGURE 14. Op Amp Noise Analysis Model.
OPA2683
SBOS244H
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21
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 4 shows the general form for the
output noise voltage using the terms presented in Figure 14.
(4)
2
2
EO =  ENI2 + (IBNR S ) + 4kTRS  NG2 + (IBIRF ) + 4kTRFNG
Dividing this expression by the noise gain (NG = (1 + RF /RG))
will give the equivalent input referred spot noise voltage at
the noninverting input, as shown in Equation 5.
(5)
2
4kTRF
2
I R 
EN = ENI2 + (IBNR S ) + 4kTRS +  BI F  +
 NG 
NG
While the last term, the inverting bias current error, is
dominant in this low-gain circuit, the input offset voltage will
become the dominant DC error term as the gain exceeds
5V/V. Where improved DC precision is required in a highspeed amplifier, consider the OPA656 single and OPA2822
dual voltage-feedback amplifiers.
DISABLE OPERATION
The OPA2683 provides an optional disable feature that may
be used to reduce system power when channel operation is
not required. If the V DIS control pin is left unconnected, the
OPA2683 will operate normally. To disable, the control pin
must be asserted LOW. Figure 14 shows a simplified internal
circuit for the disable control feature.
+VS
Evaluating these two equations for the OPA2683 circuit and
component values (see Figure 1) will give a total output spot
noise voltage of 15.2nV/√Hz and a total equivalent input spot
noise voltage of 7.6nV/√Hz. This total input referred spot
noise voltage is higher than the 4.4nV/√Hz specification for
the op amp voltage noise alone. This reflects the noise
added to the output by the inverting current noise times the
feedback resistor. As the gain is increased, this fixed output
noise power term contributes less to the total output noise
and the total input referred voltage noise given by Equation 5
will approach just the 4.4nV/√Hz of the op amp itself. For
example, going to a gain of +20 in the circuit of Figure 1,
adjusting only the gain resistor to 50Ω, will give a total input
referred noise of 4.6nV/√Hz. A more complete description of
op amp noise analysis can be found in TI application note
AB-103, Noise Analysis for High-Speed Op Amps (SBOA066),
located at www.ti.com.
DC ACCURACY AND OFFSET CONTROL
A current-feedback op amp like the OPA2683 provides
exceptional bandwidth in high gains, giving fast pulse settling
but only moderate DC accuracy. The Electrical Characteristics show an input offset voltage comparable to high slew
rate voltage-feedback amplifiers. The two input bias currents,
however, are somewhat higher and are unmatched. Whereas
bias current cancellation techniques are very effective with
most voltage-feedback op amps, they do not generally reduce the output DC offset for wideband current-feedback op
amps. Since the two input bias currents are unrelated in both
magnitude and polarity, matching the source impedance
looking out of each input to reduce their error contribution to
the output is ineffective. Evaluating the configuration of
Figure 1, using worst-case +25°C input offset voltage and the
two input bias currents, gives a worst-case output offset
range equal to:
±(NG • VOS) + (IBN • RS / 2 • NG) ± (IBI • RF)
where NG = noninverting signal gain
= ±(2 • 3.5mV) ± (4.5µA • 25Ω • 2) ± (953Ω • 10mA)
= ±7.0mV + 0.23mV ± 9.5mV
40kΩ
Q1
25kΩ
VDIS
250kΩ
IS
Control
–VS
FIGURE 14. Simplified Disable Control Circuit.
In normal operation, base current to Q1 is provided through
the 250kΩ resistor while the emitter current through the 40kΩ
resistor sets up a voltage drop that is inadequate to turn on
the two diodes in Q1’s emitter. As V DIS is pulled LOW,
additional current is pulled through the 40kΩ resistor eventually turning on these two diodes (≈ 33µA). At this point, any
further current pulled out of V DIS goes through those diodes
holding the emitter-base voltage of Q1 at approximately 0V.
This shuts off the collector current out of Q1, turning the
amplifier off. The supply current in the disable mode are only
those required to operate the circuit of Figure 14.
When disabled, the output and input nodes go to a high
impedance state. If the OPA2683 is operating in a gain of +1
(with a 1.2kΩ feedback resistor still required for stability), this
will show a very high impedance (1.7pF || 1MΩ) at the output
and exceptional signal isolation. If operating at a gain greater
than +1, the total feedback network resistance (RF + RG) will
appear as the impedance looking back into the output, but
the circuit will still show very high forward and reverse
isolation. If configured as an inverting amplifier, the input and
output will be connected through the feedback network
resistance (RF + RG) giving relatively poor input to output
isolation.
= ±16.73mV
22
OPA2683
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SBOS244H
The OPA2683 provides very high power gain on low quiescent current levels. When disabled, internal high impedance
nodes discharge slowly which, with the exceptional power
gain provided, give a self powering characteristic that leads
to a slow turn off characteristic. Typical full turn off times to
rated 100µA disabled supply current are 60ms. Turn on times
are very fast—less than 40ns.
b)
Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power-plane
layout should not be in close proximity to the signal I/O
pins. Avoid narrow power and ground traces to minimize
inductance between the pins and the decoupling capacitors. The power-supply connections should always be
decoupled with these capacitors. An optional supply
decoupling capacitor (0.01µF) across the two power
supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF)
decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These may
be placed somewhat farther from the device and may be
shared among several devices in the same area of the
PC board.
c)
Careful selection and placement of external components will preserve the high-frequency performance
of the OPA2683. Resistors should be a very low reactance type. Surface-mount resistors work best and allow
a tighter overall layout. Metal film and carbon composition axially-leaded resistors can also provide good highfrequency performance. Again, keep their leads and
PCB trace length as short as possible. Never use
wirewound type resistors in a high-frequency application. Since the output pin and inverting input pin are the
most sensitive to parasitic capacitance, always position
the feedback and series output resistor, if any, as close
as possible to the output pin. Other network components, such as noninverting input termination resistors,
should also be placed close to the package. The frequency response is primarily determined by the feedback resistor value as described previously. Increasing
its value will reduce the peaking at higher gains, while
decreasing it will give a more peaked frequency response at lower gains. The 800Ω feedback resistor used
in the Electrical Characteristics at a gain of +2 on ±5V
supplies is a good starting point for design. Note that a
953Ω feedback resistor, rather than a direct short, is
required for the unity-gain follower application. A current-feedback op amp requires a feedback resistor even
in the unity-gain follower configuration to control stability.
THERMAL ANALYSIS
The OPA2683 will not require external heatsinking for most
applications. Maximum desired junction temperature will set
the maximum allowed internal power dissipation as described below. In no case should the maximum junction
temperature be allowed to exceed 150°C.
Operating junction temperature (TJ) is given by TA + PD • θJA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in the
output stage (PDL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. PDL will depend on the
required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition PDL = VS2/(4 • RL)
where RL includes feedback network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As an absolute worst-case example, compute the maximum
TJ using an OPA2683IDCN (SOT23-8 package) in the circuit
of Figure 1 operating at the maximum specified ambient
temperature of +85°C with both outputs driving a grounded
100Ω load to 2.5VDC.
PD = 10V • 2.1mA + 2 • (52 /(4 • (100Ω || 1.9kΩ))) = 153mW
Maximum TJ = +85°C + (0.153W • 150°C/W) = 108°C
This maximum operating junction temperature is well below
most system level targets. Most applications will be lower
than this since an absolute worst-case output stage power in
both channels simultaneously was assumed in this calculation.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency amplifier like the OPA2683 requires careful attention to board
layout parasitics and external component types. Recommendations that will optimize performance include:
a)
Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability; on
the noninverting input, it can react with the source
impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and
power planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the
board.
OPA2683
SBOS244H
www.ti.com
23
d)
24
Connections to other wideband devices on the board
may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50mils to
100mils) should be used, preferably with ground and
power planes opened up around them. Estimate the
total capacitive load and set RS from the plot of recommended Rs vs CLOAD. Low parasitic capacitive loads
(< 5pF) may not need an RS since the OPA2683 is
nominally compensated to operate with a 2pF parasitic
load. If a long trace is required, and the 6dB signal loss
intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline
layout techniques). A 50Ω environment is normally not
necessary onboard, and in fact a higher impedance
environment will improve distortion, as shown in the
distortion versus load plots. With a characteristic board
trace impedance defined based on board material and
trace dimensions, a matching series resistor into the
trace from the output of the OPA2683 is used, as well as
a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor
and the input impedance of the destination device; this
total effective impedance should be set to match the
trace impedance. The high output voltage and current
capability of the OPA2683 allows multiple destination
devices to be handled as separate transmission lines,
each with their own series and shunt terminations. If the
6dB attenuation of a doubly-terminated transmission line
is unacceptable, a long trace can be series-terminated
at the source end only. Treat the trace as a capacitive
load in this case and set the series resistor value as
shown in the plot of Rs vs CLOAD. This will not preserve
signal integrity as well as a doubly-terminated line. If the
input impedance of the destination device is low, there
will be some signal attenuation due to the voltage divider
formed by the series output into the terminating impedance.
e)
Socketing a high-speed part like the OPA2683 is not
recommended. The additional lead length and pin-topin capacitance introduced by the socket can create an
extremely troublesome parasitic network which can make
it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering
the OPA2683 onto the board.
INPUT AND ESD PROTECTION
The OPA2683 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table where an absolute maximum 13V across
the supply pins is reported. All device pins have limited ESD
protection using internal diodes to the power supplies, as
shown in Figure 15.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (for example, in systems with ±15V
supply parts driving into the OPA2683), current-limiting series resistors should be added into the two inputs. Keep
these resistor values as low as possible since high values
degrade both noise performance and frequency response.
+VCC
External
Pin
Internal
Circuitry
–VCC
FIGURE 15. Internal ESD Protection.
OPA2683
www.ti.com
SBOS244H
Revision History
DATE
REVISION PAGE
7/09
H
2
7/08
G
2
SECTION
DESCRIPTION
Package/Ordering Information Changed package markings for D (SO-8) and DGS (MSOP-10) packages.
Absolute Maximum Ratings
Changed minimum storage temperature from −40°C to −65°C.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
OPA2683
SBOS244H
www.ti.com
25
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
OPA2683ID
ACTIVE
SOIC
D
8
OPA2683IDCNR
ACTIVE
SOT-23
DCN
OPA2683IDCNRG4
ACTIVE
SOT-23
OPA2683IDCNT
ACTIVE
OPA2683IDG4
75
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DCN
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SOT-23
DCN
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2683IDGSR
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2683IDGSRG4
ACTIVE
MSOP
DGS
10
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2683IDGST
ACTIVE
MSOP
DGS
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2683IDGSTG4
ACTIVE
MSOP
DGS
10
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
OPA2683IDCNR
SOT-23
3000
180.0
DCN
8
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
8.4
3.2
3.1
1.39
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
OPA2683IDCNT
SOT-23
DCN
8
250
180.0
8.4
3.2
3.1
1.39
4.0
8.0
Q3
OPA2683IDGSR
MSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2683IDGST
MSOP
DGS
10
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2683IDCNR
SOT-23
DCN
8
3000
190.5
212.7
31.8
OPA2683IDCNT
SOT-23
DCN
8
250
190.5
212.7
31.8
OPA2683IDGSR
MSOP
DGS
10
2500
346.0
346.0
29.0
OPA2683IDGST
MSOP
DGS
10
250
190.5
212.7
31.8
Pack Materials-Page 2
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