OPA842 OPA 842 SBOS267C – NOVEMBER 2002 – REVISED DECEMBER 2008 www.ti.com Wideband, Low Distortion, Unity-Gain Stable, Voltage-Feedback OPERATIONAL AMPLIFIER FEATURES DESCRIPTION ● UNITY-GAIN BANDWIDTH: 400MHz The OPA842 provides a level of speed and dynamic range previously unattainable in a monolithic op amp. Using unitygain stable, voltage-feedback architecture with two internal gain stages, the OPA842 achieves exceptionally low harmonic distortion over a wide frequency range. The “classic” differential input provides all the familiar benefits of precision op amps, such as bias current cancellation and very low inverting current noise compared with wideband current differential gain/phase performance, low-voltage noise, and high output current drive make the OPA842 ideal for most high dynamic range applications. ● GAIN-BANDWIDTH PRODUCT: 200MHz ● LOW INPUT VOLTAGE NOISE: 2.6nV/√Hz ● VERY LOW DISTORTION: –93dBc (5MHz) ● HIGH OPEN-LOOP GAIN: 110dB ● FAST 12-BIT SETTLING: 22ns (0.01%) ● LOW DC VOLTAGE OFFSET: 300µV Typical ● PROFESSIONAL LEVEL DIFF GAIN/PHASE ERROR: 0.003%/0.008° Unity-gain stability makes the OPA842 particularly suitable for low-gain differential amplifiers, transimpedance amplifiers, gain of +2 video line drivers, wideband integrators, and low-distortion Analog-to-Digital Converter (ADC) buffers. Where higher gain or even lower harmonic distortion is required, consider the OPA843—a higher-gain bandwidth and lower-noise version of the OPA842. APPLICATIONS ● ADC/DAC BUFFER DRIVER ● LOW DISTORTION “IF” AMPLIFIER ● ACTIVE FILTER CONFIGURATION ● LOW-NOISE DIFFERENTIAL RECEIVER OPA842 RELATED PRODUCTS ● HIGH-RESOLUTION IMAGING ● TEST INSTRUMENTATION ● PROFESSIONAL AUDIO ● OPA642 UPGRADE SINGLES INPUT NOISE VOLTAGE (nV/ √Hz ) GAIN-BANDWIDTH PRODUCT (MHz) OPA843 OPA846 OPA847 2.0 1.1 0.8 800 2500 3700 +5V +5V 2kΩ RS 0.1µF 24.9Ω VIN 50Ω REFT (+3V) 2kΩ IN OPA842 100pF ADS850 14-Bit 10MSPS –5V 402Ω 2kΩ IN 0.1µF 402Ω (+2V) REFB 2kΩ (+1V) VREF SEL AC-Coupled to 14-Bit ADS850 Interface Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2002-2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Power Supply ............................................................................... ±6.5VDC Internal Power Dissipation ...................................... See Thermal Analysis Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Voltage Range: D, DBV ................................... –65°C to +125°C Lead Temperature (soldering, 10s) ............................................... +300°C Junction Temperature (TJ) ............................................................ +175°C ESD Rating (Human Body Model) .................................................. 2000V (Charge Device Model) ............................................... 1500V (Machine Model) ........................................................... 200V This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING SO-8 D –40°C to +85°C OPA842 OPA842ID Rails, 100 " " " " OPA842IDR Tape and Reel, 2500 SOT23-5 DBV –40°C to +85°C OAQI OPA842IDBVT Tape and Reel, 250 " " " " OPA842IDBVR Tape and Reel, 3000 OPA842 " OPA842 " ORDERING NUMBER TRANSPORT MEDIA, QUANTITY NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. PIN CONFIGURATIONS 8 NC Inverting Input 2 7 +VS Noninverting Input 3 6 Output –VS 4 5 NC Output 1 –VS 2 Noninverting Input 3 NC = No Connection 5 +VS 4 Inverting Input 1 OAQI 3 1 SOT 2 NC Top View 4 SO 5 Top View Pin Orientation/Package Marking 2 OPA842 www.ti.com SBOS267C ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at +25°C. At TA = +25°C, VS = ±5V, RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted. See Figure 1 for AC performance. OPA842ID, OPA842IDBV TYP PARAMETER AC PERFORMANCE (see Figure 1) Closed-Loop Bandwidth (VO = 100mVPP) Gain-Bandwidth Product Bandwidth for 0.1dB Gain Flatness Harmonic Distortion 2nd-Harmonic 3rd-Harmonic 2-Tone, 3rd-Order Intercept Input Voltage Noise Input Current Noise Rise-and-Fall Time Slew Rate Settling Time to 0.01% 0.1% 1.0% Differential Gain Differential Phase DC PERFORMANCE(4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift INPUT Common-Mode Input Range (CMIR)(5) Common-Mode Rejection (CMRR) Input Impedance Differential-Mode Common-Mode OUTPUT Output Voltage Swing Current Output, Sourcing Closed-Loop Output Impedance POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Max Quiescent Current Min Quiescent Current Power-Supply Rejection Ratio (+PSRR, –PSRR) THERMAL CHARACTERISTICS Specified Operating Range: D, DBV Thermal Resistance, θJA D SO-8 DBV SOT23-5 CONDITIONS +25°C G = +1, RF = 25Ω G = +2 G = +5 G = +10 350 150 45 21 200 56 105 G = +2, RL = 100Ω, VO = 100mVPP G = +1, RL = 100Ω, RF = 25Ω G = +2, f = 5MHz, VO = 2VPP RL = 100Ω RL = 500Ω RL = 100Ω RL = 500Ω G = +2, f = 10MHz f > 1MHz f > 1MHz 0.2V Step 2V Step 2V Step 2V Step 2V Step G = +2, NTSC, RL = 150Ω G = +2, NTSC, RL = 150Ω –80 –94 –97 –93 44 2.6 2.7 2.3 400 22 15 9 0.003 0.008 VO = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C –40°C to +85°C(2) 105 30 15 136 101 29 14 135 100 29 14 135 –78 –92 –96 –91 –77 –91 –95 –90 –76 –90 –94 –90 2.8 2.8 3.3 300 3.0 2.9 3.4 250 3.1 3.0 3.5 225 19.6 10.2 20.3 11.3 21.3 12.5 100 96 ±1.4 ±4 –36 25 ±1.15 ±2 ±2.9 84 110 ±0.30 ±1.2 –20 –35 ±0.35 ±1.0 VCM = ±1V, Input Referred ±3.2 95 ±3.0 VCM = 0V VCM = 0V 14 || 1 3.1 || 1.2 RL > 1kΩ, Positive Output RL > 1kΩ, Negative Output RL = 100Ω, Positive Output RL = 100Ω, Negative Output VO = 0V G = +2, f = 1kHz 3.2 –3.7 3.0 –3.5 ±100 0.00038 85 UNITS MIN/ MAX TEST LEVEL(3 ) MHz MHz MHz MHz MHz MHz MHz typ min min min min typ typ C B B B B C C dBc dBc dBc dBc dBm nV/ √Hz pA/ √Hz ns V/µs ns ns ns % deg max max max max typ max max max min typ max max typ typ B B B B C B B B B C B B C C 92 ±1.5 ±4 –37 25 ±1.17 ±2 dB mV µV/°C µA nA/°C µA nA/°C min max max max max max max A A B A B A B ±2.8 82 V dB min min A A kΩ || pF MΩ || pF typ typ C C V V V V mA Ω min min min min min typ A A A A A C 3.0 –3.5 2.8 –3.3 ±90 ±2.9 –3.4 2.7 –3.2 ±85 ±2.8 –3.3 2.6 –3.1 ±80 ±6 ±6 22.5 18.3 V V mA mA typ min max min C A A A 85 dB min A –40 to +85 °C typ C 125 150 °C °C typ typ C C ±5 VS = ±5V VS = ±5V 20.2 20.2 20.8 19.6 ±6 22.2 19.1 |VS| = 4.5V to 5.5V, Input Referred 100 90 88 Junction-to-Ambient NOTES: (1) Junction temperature = ambient temperature for +25°C min/max specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature min/max specifications. (3) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive outof-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at ±CMIR limits. OPA842 SBOS267C www.ti.com 3 TYPICAL CHARACTERISTICS: VS = ±5V At TA = 25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE 3 G = +1 RF = 25Ω 0 G = +2 –3 VO = 0.1Vp-p G = +5 –6 G = +10 –9 0 Normalized Gain (3dB/div) –12 G = –1 –3 G = –5 –9 –12 G = –10 –15 –15 See Figure 1 See Figure 2 –18 –18 1 10 100 500 1 NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE INVERTING LARGE-SCALE FREQUENCY RESPONSE 500 9 0.1Vp-p 0.5Vp-p 1.0Vp-p 6 3 RL = 100Ω G = +2V/V 0 RL = 100Ω G = –2V/V RG = 200Ω 3 VO = 2Vp-p VO = 5Vp-p –3 0.1Vp-p 1Vp-p 2Vp-p 6 0 Gain (3dB/div) Normalized Gain (3dB/div) 100 Frequency (MHz) 5Vp-p –3 –6 –9 –6 –12 –9 –15 See Figure 1 See Figure 2 –12 –18 1 10 100 500 1 10 100 NONINVERTING PULSE RESPONSE INVERTING PULSE RESPONSE 1.2 G = +2 200 Right Scale 100 0.8 0.4 0 Small Signal ± 100mV Left Scale –100 –200 0 –0.4 –0.8 Output Voltage (100mV/div) Frequency (MHz) Output Voltage (400mV/div) Frequency (MHz) Large Signal ± 1V Output Voltage (100mV/div) 10 Frequency (MHz) 9 G = –2 RG = 200Ω Large Signal ± 1V 200 500 1.2 0.8 Right Scale 100 0.4 0 0 Small Signal ± 100mV Left Scale –100 –200 –0.4 –0.8 –1.2 See Figure 1 –1.2 See Figure 2 Time (5ns/div) 4 G = –2 VO = 0.1Vp-p –6 Time (5ns/div) OPA842 www.ti.com SBOS267C Output Voltage (400mV/div) Normalized Gain (3dB/div) 3 INVERTING SMALL-SIGNAL FREQUENCY RESPONSE TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) At TA = 25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. 1MHz HARMONIC DISTORTION vs LOAD RESISTANCE 5MHz HARMONIC DISTORTION vs LOAD RESISTANCE –85 –75 VO = 2Vp-p Harmonic Distortion (dBc) Harmonic Distortion (dBc) VO = 2Vp-p –80 2nd-Harmonic –85 –90 –95 –90 –95 2nd-Harmonic –100 –105 3rd-Harmonic 3rd-Harmonic See Figure 1 See Figure 1 –110 –100 100 150 200 250 300 350 400 450 100 500 150 200 HARMONIC DISTORTION vs FREQUENCY 350 400 450 500 HARMONIC DISTORTION vs OUTPUT VOLTAGE VO = 2Vp-p RL = 200Ω G = +2 –70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 300 –80 –60 –80 2nd-Harmonic –90 3rd-Harmonic –100 RL = 200Ω F = 5MHz –85 –90 2nd-Harmonic –95 3rd-Harmonic –100 –105 See Figure 1 See Figure 1 –110 –110 0.5 1 10 0.1 20 1 10 Output Voltage Swing (Vp-p) Frequency (MHz) HARMONIC DISTORTION vs NONINVERTING GAIN HARMONIC DISTORTION vs INVERTING GAIN –70 –70 VO = 2Vp-p RL = 200Ω F = 5MHz –80 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 250 Load Resistance (Ω) Load Resistance (Ω) 2nd-Harmonic –90 3rd-Harmonic –100 VO = 2Vp-p RL = 200Ω F = 5MHz RF = 402Ω –80 2nd-Harmonic –90 –100 3rd-Harmonic See Figure 2 See Figure 1 –110 –110 1 10 1 Noninverting Gain (V/V) OPA842 SBOS267C 10 Inverting Gain |V/V| www.ti.com 5 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) At TA = 25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. 2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT INPUT VOLTAGE AND CURRENT NOISE 50 100 PI 50Ω Intercept Point (+dBm) Voltage Noise (nV√Hz) Current Noise (pA√Hz) 45 10 Current Noise 2.7pA/√Hz Voltage Noise 50Ω OPA842 PO 50Ω 402Ω 40 402Ω 35 30 25 2.6nV/√Hz 20 1 102 103 104 105 106 5 107 10 15 20 Frequency (Hz) RECOMMENDED RS vs CAPACITIVE LOAD 35 40 45 50 3 Normalized Gain to Capacitive Load (dB) RS (Ω) 10 1 10 30 FREQUENCY RESPONSE vs CAPACITIVE LOAD 100 1 25 Frequency (MHz) 100 0 C = 10pF –3 C = 47pF C = 22pF –6 C = 100pF –9 VI RS VO 50Ω OPA842 –12 CL 1kΩ 402Ω –15 402Ω –18 1k 10 100 Capacitive Load (pF) Frequency (MHz) GAIN = +1 FLATNESS PULSE RESPONSE G = +1 500 Large Signal ± 1V Output Voltage (100mV/div) 0.1 Gain (0.1dB/div) 0 VO = 0.1Vp-p RF = 25Ω RL = 100Ω –0.1 –0.2 –0.3 –0.4 200 1.2 0.8 Right Scale 100 0.4 0 –100 0 Small Signal Left Scale –200 –0.4 –0.8 –0.5 –1.2 –0.6 0 25 50 75 100 125 150 175 200 Time (2ns/div) Frequency (25MHz/div) 6 OPA842 www.ti.com SBOS267C Output Voltage (400mV/div) 0.2 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) At TA = 25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. CMRR AND PSRR vs FREQUENCY OPEN-LOOP GAIN AND PHASE 120 20log (AOL) CMRR 80 +PSRR 60 40 80 –60 ∠AOL 60 20 –90 40 –120 20 –150 0 –180 –20 102 103 104 105 106 107 108 –210 101 102 103 104 106 107 108 Frequency (Hz) Frequency (Hz) OUTPUT VOLTAGE AND CURRENT LIMITATIONS CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY 4 Output Impedance (Ω) 1 2 RL = 100 1 0 1W Internal Power Limit RL = 25 RL = 50 –1 1W Internal Power Limit –2 0.1 0.01 0.001 0.0001 –3 –4 –0.15 0.00001 –0.10 –0.05 0 0.05 0.10 0.15 102 103 104 IO (mA) NONINVERTING OVERDRIVE RECOVERY Output Left Scale RL = 100Ω G=2 See Figure 1 2 1 4 3 2 1 0 0 –2 –1 0 –2 –1 –4 –2 –6 –3 –6 –4 –8 Time (40ns/div) RL = 100Ω G=2 See Figure 2 2 0 –8 108 4 Input Right Scale 6 3 Output Voltage (2V/div) 4 107 INVERTING OVERDRIVE RECOVERY Input Voltage (1V/div) 6 106 8 4 Input Right Scale 105 Frequency (Hz) 8 2 109 10 3 –4 –2 Output Left Scale –3 –4 Time (40ns/div) OPA842 SBOS267C 105 Input Voltage (1V/div) 101 Output Voltage (2V/div) –30 www.ti.com 7 Open-Loop Phase (°) 100 100 0 VO (V) 0 –PSRR Open-Loop Gain (dB) Common-Mode Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 120 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) At TA = 25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. SETTLING TIME VIDEO DIFFERENTIAL GAIN/DIFFERENTIAL PHASE 0.250 0.008 0.100 0.050 0.000 –0.050 –0.100 0.006 0.06 DG Negative Video DP Negative Video 0.004 0.04 DP Positive Video 0.002 0.02 DG Positive Video –0.150 –0.200 See Figure 1 0 –0.250 5 10 15 20 25 30 35 40 45 0 50 1 2 3 TYPICAL DC DRIFT OVER TEMPERATURE SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 12.5 Input Offset Voltage Left Scale 0 –0.5 –12.5 Input Bias Current 24 115 Output Current (5mA/div) 0.5 120 Input Bias and Offset Current (µA) 25 100x (Input Offset Current) Right Scale 0 5 Video Loads Time (ns) 1 4 22 Supply Current 110 20 Right Scale 105 18 100 16 Sink/Source Output Current 95 14 Left Scale 90 12 85 10 Supply Current (2mA/div) 0 Input Offset Voltage (mV) Differential Phase (°) Differential Gain (%) Percent of Final Value (%) 0.150 0.08 G=2 VO = 2V step RL = 100Ω G=2 0.200 Right Scale –1 –50 –25 0 25 50 75 100 –25 125 80 –50 –25 Ambient Temperature (°C) 0 25 50 75 100 8 125 Ambient Temperature (°C) COMMON-MODE AND DIFFERENTIAL INPUT IMPEDANCE COMMON-MODE INPUT RANGE AND OUTPUT SWING vs SUPPLY VOLTAGE 107 6 Common-Mode Impedance 106 Input Impedance (Ω) Voltage Range (V) 4 2 0 ±Voltage Output ±Voltage Input –2 104 Differential Impedance 103 –4 102 –6 ±3 ±4 ±5 ±6 102 Supply Voltage (±V) 8 105 103 104 105 106 107 108 109 Frequency (Hz) OPA842 www.ti.com SBOS267C TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) At TA = 25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. DIFFERENTIAL PERFORMANCE TEST CIRCUIT DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE 3 +5V GD = 1 OPA842 GD = VI RG –5V 402Ω RG 402Ω Normalized Gain (dB) 0 402Ω RL RG VO GD = 2 –3 GD = 5 –6 GD = 10 –9 –12 +5V –15 OPA842 –18 1 10 100 –5V Frequency (MHz) DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE DIFFERENTIAL DISTORTION vs LOAD RESISTANCE 9 –85 G=2 F = 5MHz VO = 4Vp-p 6 Harmonic Distortion (dBc) Gain (dB) 0.2Vp-p 1Vp-p 2Vp-p GD = 2 RL = 400Ω 3 0 –3 5Vp-p –6 8Vp-p –9 –90 –95 2nd-Harmonic –100 –105 3rd-Harmonic –12 –110 10 100 50 500 100 150 DIFFERENTIAL DISTORTION vs FREQUENCY 250 300 350 400 450 500 DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE –60 –80 RL = 400Ω RL = 400Ω VO = 4Vp-p GD = 2 –85 Harmonic Distortion (dBc) –70 200 Load Resistance (Ω) Frequency (MHz) Harmonic Distortion (dBc) 500 GD = 2 –80 –90 2nd-Harmonic –100 F = 5MHz –90 –95 2nd-Harmonic –100 –105 3rd-Harmonic –110 3rd-Harmonic –115 –110 1 10 100 1 Frequency (MHz) OPA842 SBOS267C 10 Output Voltage Swing (Vp-p) www.ti.com 9 APPLICATIONS INFORMATION +5V WIDEBAND VOLTAGE-FEEDBACK OPERATION The OPA842’s combination of speed and dynamic range is easily achieved in a wide variety of application circuits, providing that simple principles of good design practice are observed. For example, good power-supply decoupling, as shown in Figure 1, is essential to achieve the lowest possible harmonic distortion and smooth frequency response. Proper PC board layout and careful component selection will maximize the performance of the OPA842 in all applications, as discussed in the following sections of this data sheet. Figure 1 shows the gain of +2 configuration used as the basis for most of the typical characteristics. Most of the curves were characterized using signal sources with 50Ω driving impedance and with measurement equipment presenting 50Ω load impedance. In Figure 1, the 50Ω shunt resistor at the VI terminal matches the source impedance of the test generator while the 50Ω series resistor at the VO terminal provides a matching resistor for the measurement equipment load. Generally, data sheet specifications refer to the voltage swing at the output pin (VO in Figure 1). The 100Ω load, combined with the 804Ω total feedback network load, presents the OPA842 with an effective load of approximately 90Ω in Figure 1. +5V +VS 0.1µF + 2.2µF 50Ω Source VIN 50Ω RS 50Ω Load 50Ω VO OPA842 RF 402Ω RG 402Ω 0.1µF + 2.2µF –VS –5V FIGURE 1. Gain of +2. High-frequency application and characterization circuit. WIDEBAND INVERTING OPERATION Operating the OPA842 as an inverting amplifier has several benefits and is particularly useful when a matched 50Ω source and input impedance is required. Figure 2 shows the inverting gain of –2 circuit used as the basis of the inverting mode Typical Characteristics. 10 0.1µF 0.1µF 50Ω Source RT 147Ω VO + 2.2µF 50Ω 50Ω Load OPA843 RG 200Ω RF 402Ω VI RM 66.5Ω 0.1µF + 2.2µF –5V FIGURE 2. Inverting G = –2 Specifications and Test Circuit. In the inverting case, just the feedback resistor appears as part of the total output load in parallel with the actual load. For the 100Ω load used in the Typical Characteristics, this gives a total load of 80Ω in this inverting configuration. The gain resistor is set to get the desired gain (in this case 200Ω for a gain of –2) while an additional input matching resistor (RM) can be used to set the total input impedance equal to the source if desired. In this case, RM = 66.5Ω in parallel with the 200Ω gain setting resistor gives a matched input impedance of 50Ω. This matching is only needed when the input needs to be matched to a source impedance, as in the characterization testing done using the circuit of Figure 2. The OPA842 offers extremely good DC accuracy as well as low noise and distortion. To take full advantage of that DC precision, the total DC impedance looking out of each of the input nodes must be matched to get bias current cancellation. For the circuit of Figure 2, this requires the 147Ω resistor shown to ground on the noninverting input. The calculation for this resistor includes a DC-coupled 50Ω source impedance along with RG and RM. Although this resistor will provide cancellation for the bias current, it must be well decoupled (0.1µF in Figure 2) to filter the noise contribution of the resistor and the input current noise. As the required RG resistor approaches 50Ω at higher gains, the bandwidth for the circuit in Figure 2 will far exceed the bandwidth at that same gain magnitude for the noninverting circuit of Figure 1. This occurs due to the lower noise gain for the circuit of Figure 2 when the 50Ω source impedance is included in the analysis. For instance, at a signal gain of –8 (RG = 50Ω, RM = open, RF = 402Ω) the noise gain for the circuit of Figure 2 will be 1 + 402Ω/(50Ω + 50Ω) = 5 due to the addition of the 50Ω source in the noise gain equation. This gives considerable higher bandwidth than the noninverting gain of +8. Using the 200MHz gain bandwidth product for the OPA842, an inverting gain of –8 from a 50Ω source to a 50Ω RG will give approximately 40MHz bandwidth, whereas the noninverting gain of +8 will give 25MHz. OPA842 www.ti.com SBOS267C BUFFERING HIGH-PERFORMANCE ADCs To achieve full performance from a high dynamic range ADC, considerable care must be exercised in the design of the input amplifier interface circuit. The example circuit on the front page shows a typical AC-coupled interface to a very high dynamic range converter. This AC-coupled example allows the OPA842 to be operated using a signal range that swings symmetrically around ground (0V). The 2VPP swing is then level-shifted through the blocking capacitor to a midscale reference level, which is created by a well-decoupled resistive divider off the converter’s internal reference voltages. To have a negligible effect on the rated Spurious-Free Dynamic Range (SFDR) of the converter, the amplifier’s SFDR should be at least 10dB greater than the converter. The OPA842 has no effect on the rated distortion of the ADS850, given its 82dB SFDR at 2Vp-p, 5MHz. The > 92dB SFDR for the OPA842 in this configuration will not degrade the converter. Successful application of the OPA842 for ADC driving requires careful selection of the series resistor at the amplifier output, along with the additional shunt capacitor at the ADC input. To some extent, selection of this RC network will be determined empirically for each model of the converter. Many high-performance CMOS ADCs, like the ADS850, perform better with the shunt capacitor at the input pin. This capacitor provides low source impedance for the transient currents produced by the sampling process. Improved SFDR is often obtained by adding this external capacitor, whose value is often recommended in this converter data sheet. The external capacitor, in combination with the built-in capacitance of the ADC input, presents a significant capacitive load to the OPA842. Without a series isolation resistor, an undesirable peaking or loss of stability in the amplifier may result. Since the DC bias current of the CMOS ADC input is negligible, the resistor has no effect on overall gain or offset accuracy. Refer to the typical characteristic RS vs Capacitive Load to obtain a good starting value for the series resistor. This will ensure flat frequency response to the ADC input. Increasing the external capacitor value will allow the series resistor to be reduced. Intentionally bandlimiting using this RC network can also be used to limit noise at the converter input. OPA842 will provide exceptional results in video distribution applications. Differential gain and phase measure the change in overall small-signal gain and phase for the color sub-carrier frequency (3.58MHz in NTSC systems) versus changes in the large-signal output level (which represents luminance information in a composite video signal). The OPA842, with the typical 150Ω load of a single matched video cable, shows less than 0.01%/0.01° differential gain/phase errors over the standard luminance range for a positive video (negative sync) signal. Similar performance would be observed for negative video signals. SINGLE OP AMP DIFFERENTIAL AMPLIFIER The voltage-feedback architecture of the OPA842, with its high Common-Mode Rejection Ratio (CMRR), will provide exceptional performance in differential amplifier configurations. Figure 3 shows a typical configuration. The starting point for this design is the selection of the RF value in the range of 200Ω to 2kΩ. Lower values reduce the required RG, increasing the load on the V2 source and on the OPA842 output. Higher values increase output noise and exacerbate the effects of parasitic board and device capacitances. Following the selection of RF, RG must be set to achieve the desired inverting gain for V2. Remember that the bandwidth will be set approximately by the Gain Bandwidth Product (GBP) divided by the noise gain (1 + RF/RG). For accurate differential operation (i.e., good CMRR), the ratio R2/R1 must be set equal to RF/RG. +5V V1 50Ω R2 OPA842 RG RF V2 VO = when RF (V – V2) RG 1 R2 RF = R1 RG –5V FIGURE 3. High-Speed, Single Differential Amplifier. VIDEO LINE DRIVING Most video distribution systems are designed with 75Ω series resistors to drive a matched 75Ω cable. In order to deliver a net gain of 1 to the 75Ω matched load, the amplifier is typically set up for a voltage gain of +2, compensating for the 6dB attenuation of the voltage divider formed by the series and shunt 75Ω resistors at either end of the cable. The circuit of Figure 1 applies to this requirement if all references to 50Ω resistors are replaced by 75Ω values. Often, the amplifier gain is further increased to 2.2, which recovers the additional DC loss of a typical long cable run. This change would require the gain resistor (RG) in Figure 1 to be reduced from 402Ω to 335Ω. In either case, both the gain flatness and the differential gain/phase performance of the Usually, it is best to set the absolute values of R2 and R1 equal to RF and RG, respectively; this equalizes the divider resistances and cancels the effect of input bias currents. However, it is sometimes useful to scale the values of R2 and R1 in order to adjust the loading on the driving source V1. In most cases, the achievable low-frequency CMRR will be limited by the accuracy of the resistor values. The 85dB CMRR of the OPA842 itself will not determine the overall circuit CMRR unless the resistor ratios are matched to better than 0.003%. If it is necessary to trim the CMRR, then R2 is the suggested adjustment point. OPA842 SBOS267C Power-supply decoupling not shown. R1 www.ti.com 11 THREE OP AMP DIFFERENCING (Instrumentation Topology) The primary drawback of the single op amp differential amplifier is its relatively low input impedances. Where high impedance is required at the differential input, a standard instrumentation amplifier (INA) topology may be built using the OPA842 as the differencing stage. Figure 4 shows an example of this, in which the two input amplifiers are packaged together as a dual voltage-feedback op amp, the OPA2822. This approach saves board space, cost, and power compared to using two additional OPA842 devices, and still achieves very good noise and distortion performance due to the moderate loading on the input amplifiers. requires its outputs terminated to a compliance voltage other than ground for operation, then the appropriate voltage level may be applied to the noninverting input of the OPA842. OPA842 High-Speed DAC VO = ID RF RF CF CD ID GBP → Gain Bandwidth Product (Hz) for the OPA842 +5V V1 OPA2822 RF1 500Ω RG 500Ω RF1 500Ω ID Power-supply decoupling not shown. +5V 500Ω 500Ω OPA842 VO FIGURE 5. Wideband Low-Distortion DAC Transimpedance Amplifier. –5V 500Ω 500Ω The DC gain for this circuit is equal to RF. At high frequencies, the DAC output capacitance will produce a zero in the noise gain for the OPA842 that may cause peaking in the closed-loop frequency response. CF is added across RF to compensate for this noise-gain peaking. To achieve a flat transimpedance frequency response, this pole in the feedback network should be set to: OPA2822 V2 –5V FIGURE 4. Wideband 3-Op Amp Differencing Amplifier. In this circuit, the common-mode gain to the output is always 1, due to the four matched 500Ω resistors, whereas the differential gain is set by (1 + 2RF1/RG), which is equal to 2 using the values in Figure 4. The differential to single-ended conversion is still performed by the OPA842 output stage. The high-impedance inputs allow the V1 and V2 sources to be terminated or impedance matched as required. If the V1 and V2 inputs are already truly differential, such as the output from a signal transformer, then a single matching termination resistor may be used between them. Remember, however, that a defined DC signal path must always exist for the V1 and V2 inputs; for the transformer case, a center-tapped secondary connected to ground would provide an optimum DC operating point. DAC TRANSIMPEDANCE AMPLIFIER High-frequency Digital-to-Analog Converters (DACs) require a low-distortion output amplifier to retain their SFDR performance into real-world loads. A single-ended output drive implementation is shown in Figure 5. In this circuit, only one side of the complementary output drive signal is used. The diagram shows the signal output current connected into the virtual ground-summing junction of the OPA842, which is set up as a transimpedance stage or I-V converter. The unused current output of the DAC is connected to ground. If the DAC 12 1 = 2πRF CF GBP 4 πRF CD (1) which will give a corner frequency f–3dB of approximately: f −3dB = GBP 2πRF CD (2) ACTIVE FILTERS Most active filter topologies will have exceptional performance using the broad bandwidth and unity-gain stability of the OPA842. Topologies employing capacitive feedback require a unity-gain stable, voltage-feedback op amp. Sallen-Key filters simply use the op amp as a noninverting gain stage inside an RC network. Either current- or voltage-feedback op amps may be used in Sallen-Key implementations. See Figure 6 for an example Sallen-Key low-pass filter, in which the OPA842 is set up to deliver a low-frequency gain of +2. The filter component values have been selected to achieve a maximally flat Butterworth response with a 5MHz, –3dB bandwidth. The resistor values have been slightly adjusted to compensate for the effects of the 150MHz bandwidth provided by the OPA842 in this configuration. This filter may be combined with the ADC driver suggestions to provide moderate (2pole) Nyquist filtering, limiting noise, and out-of-band harmonics into the input of an ADC. This filter will deliver the exceptionally low harmonic distortion required by high SFDR ADCs such as the ADS850 (14-bit, 10MSPS, 82dB SFDR). OPA842 www.ti.com SBOS267C C1 150pF +5V R1 124Ω R2 505Ω V1 C2 100pF VO OPA842 RF 402Ω Power-supply decoupling not shown. –5V RG 402Ω FIGURE 6. 5MHz Butterworth Low-Pass Active Filter. DESIGN-IN TOOLS DEMONSTRATION FIXTURES Two printed circuit boards (PCBs) are available to assist in the initial evaluation of circuit performance using the OPA842 in its two package options. Both of these are offered free of charge as unpopulated PCBs, delivered with a user's guide. The summary information for these fixtures is shown in the table below. PRODUCT OPA842ID OPA842IDBV PACKAGE ORDERING NUMBER LITERATURE NUMBER SO-8 SOT23-5 DEM-OPA-SO-1A DEM-OPA-SOT-1A SBOU009 SBOU010 The demonstration fixtures can be requested at the Texas Instruments web site (www.ti.com) through the OPA842 product folder. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often a quick way to analyze the performance of the OPA842 and its circuit designs. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can play a major role on circuit performance. A SPICE model for the OPA842 is available through the TI web page (www.ti.com). The applications group is also available for design assistance. These models predict typical small-signal AC, transient steps, DC performance, and noise under a wide variety of operating conditions. The models include the noise terms found in the electrical specifications of the data sheet. These models do not attempt to distinguish between the package types in their small-signal AC performance. OPERATING SUGGESTIONS OPTIMIZING RESISTOR VALUES Since the OPA842 is a unity-gain stable, voltage-feedback op amp, a wide range of resistor values may be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. For a noninverting unity-gain follower application, the feedback connection should be made with a 25Ω resistor—not a direct short. This will isolate the inverting input capacitance from the output pin and improve the frequency response flatness. Usually, the feedback resistor value should be between 200Ω and 1kΩ. Below 200Ω, the feedback network will present additional output loading which can degrade the harmonic distortion performance of the OPA842. Above 1kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor may cause unintentional band limiting in the amplifier response. A good rule of thumb is to target the parallel combination of R F and RG (see Figure 1) to be less than about 200Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network, and thus a zero in the forward response. Assuming a 2pF total parasitic on the inverting node, holding RF || RG < 200Ω will keep this pole above 400MHz. By itself, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest. In the inverting configuration, an additional design consideration must be noted. RG becomes the input resistor and therefore the load impedance to the driving source. If impedance matching is desired, RG may be set equal to the required termination value. However, at low inverting gains, the resultant feedback resistor value can present a significant load to the amplifier output. For example, an inverting gain of 2 with a 50Ω input matching resistor (= RG) would require a 100Ω feedback resistor, which would contribute to output loading in parallel with the external load. In such a case, it would be preferable to increase both the RF and RG values, and then achieve the input matching impedance with a third resistor to ground (see Figure 2). The total input impedance becomes the parallel combination of RG and the additional shunt resistor. BANDWIDTH vs GAIN Voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the GBP shown in the specifications. Ideally, dividing GBP by the noninverting signal gain (also called the Noise Gain, or NG) will predict the closedloop bandwidth. In practice, this only holds true when the phase margin approaches 90°, as it does in high-gain configurations. At low signal gains, most amplifiers will exhibit a more complex response with lower phase margin. The OPA842 is optimized to give a maximally flat 2nd-order Butterworth response in a gain of 2. In this configuration, the OPA842 has approximately 60° of phase margin and will show a typical –3dB bandwidth of 150MHz. When the phase margin is 60°, the closed-loop bandwidth is approximately √2 greater than the value predicted by dividing GBP by the noise gain. Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +10, the OPA842 SBOS267C www.ti.com 13 21MHz bandwidth shown in the Electrical Characteristics agrees with that predicted using the simple formula and the typical GBP of 200MHz. OUTPUT DRIVE CAPABILITY The OPA842 has been optimized to drive the demanding load of a doubly-terminated transmission line. When a 50Ω line is driven, a series 50Ω into the cable and a terminating 50Ω load at the end of the cable are used. Under these conditions, the cable’s impedance will appear resistive over a wide frequency range, and the total effective load on the OPA842 is 100Ω in parallel with the resistance of the feedback network. The Electrical Characteristics show a +2.8V/–3.3V swing into this load—which will then be reduced to a +1.4V/–1.65V swing at the termination resistor. The ±90mA output drive over temperature provides adequate current drive margin for this load. Higher voltage swings (and lower distortion) are achievable when driving higher impedance loads. A single video load typically appears as a 150Ω load (using standard 75Ω cables) to the driving amplifier. The OPA842 provides adequate voltage and current drive to support up to three parallel video loads (50Ω total load) for an NTSC signal. With only one load, the OPA842 achieves an exceptionally low 0.003%/0.008° dG/dP error. DRIVING CAPACITIVE LOADS One of the most demanding, and yet very common, load conditions for an op amp is capacitive loading. A high-speed, high open-loop gain amplifier like the OPA842 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. In simple terms, the capacitive load reacts with the open-loop output resistance of the amplifier to introduce an additional pole into the loop and thereby decrease the phase margin. This issue has become a popular topic of application notes and articles, and several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended RS vs Capacitive Load and the resulting frequency response at the load. The criterion for setting the recommended resistor is maximum bandwidth, flat frequency response at the load. Since there is now a passive low-pass filter between the output pin and the load capacitance, the response at the output pin itself is typically somewhat peaked, and becomes flat after the roll-off action of the RC network. This is not a concern in most applications, but can cause clipping if the desired signal swing at the load is very close to the amplifier’s swing limit. Such clipping would be most likely to occur in 14 pulse response applications where the frequency peaking is manifested as an overshoot in the step response. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA842. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA842 output pin (see Board Layout section). DISTORTION PERFORMANCE The OPA842 is capable of delivering an exceptionally low distortion signal at high frequencies and low gains. The distortion plots in the Typical Characteristics show the typical distortion under a wide variety of conditions. Most of these plots are limited to 100dB dynamic range. The OPA842’s distortion does not rise above –100dBc until either the signal level exceeds 0.5V and/or the fundamental frequency exceeds 500kHz. Distortion in the audio band is ≤ –120dBc. Generally, until the fundamental signal reaches very high frequencies or powers, the 2nd-harmonic will dominate the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network—in the noninverting configuration this is the sum of RF + RG, whereas in the inverting configuration this is just RF (see Figure 1). Increasing the output voltage swing increases harmonic distortion directly. Increasing the signal gain will also increase the 2ndharmonic distortion. Again, a 6dB increase in gain will increase the 2nd- and 3rd-harmonic by 6dB even with a constant output power and frequency. Finally, the distortion increases as the fundamental frequency increases due to the roll off in the loop gain with frequency. Conversely, the distortion will improve going to lower frequencies down to the dominant open-loop pole at approximately 600Hz. Starting from the –100dBc 2nd-harmonic for 2Vp-p into 200Ω, G = +2 distortion at 1MHz (from the Typical Characteristics), the 2nd-harmonic distortion at 20kHz should be approximately: –100dB – 20log (1MHz/20kHz) = –134dBc The OPA842 has an extremely low 3rd-order harmonic distortion. This also gives an exceptionally good 2-tone, 3rd-order intermodulation intercept, as shown in the Typical Characteristics. This intercept curve is defined at the 50Ω load when driven through a 50Ω-matching resistor to allow direct comparisons to RF MMIC devices. This network attenuates the voltage swing from the output pin to the load by 6dB. If the OPA842 drives directly into the input of a high-impedance device, such as an ADC, this 6dB attenuation is not taken. Under these conditions, the intercept will increase by a minimum 6dBm. The intercept is used to predict the intermodulation spurious for two closely spaced frequencies. If the two test frequencies, f1 and f2, are specified in terms of average and delta frequency, fO = (f1 + f2)/2 and ∆f = |f2 – f1|/2, the two 3rdorder, close-in spurious tones will appear at f O ± (3 • ∆f). The difference between the two equal test-tone power levels and these intermodulation spurious power levels is given by OPA842 www.ti.com SBOS267C 2 • (IM3 – PO), where IM3 is the intercept taken from the typical characteristic curve and PO is the power level in dBm at the 50Ω load for one of the two closely spaced test frequencies. For instance, at 10MHz the OPA842 at a gain of +2 has an intercept of 45dBm at a matched 50Ω load. If the full envelope of the two frequencies needs to be 2Vp-p, this requires each tone to be 4dBm. The 3rd-order intermodulation spurious tones will then be 2 • (45 – 4) = 82dBc below the test-tone power level (–80dBm). If this same 2VPP 2-tone envelope were delivered directly into the input of an ADC without the matching loss or loading of the 50Ω network, the intercept would increase to at least 51dBm. With the same signal and gain conditions driving directly into a light load, the spurious tones will then be at least 2 • (51 – 4) = 94dBc below the 1VPP test-tone signal levels. EN = ENI 2 + (IBN RS )2 + 4kTRS + (4) Evaluating these two equations for the OPA842 circuit presented in Figure 1 will give a total output spot noise voltage of 6.6nV/√Hz and an equivalent input spot noise voltage of 3.3nV/√Hz. Narrow band communications systems are more commonly concerned with the noise figure for the amplifier. The total input referred voltage noise expression (see Equation 4), may be used to calculate the noise figure. Equation 5 shows this noise figure expression using the NG of Equation 4 for the noninverting configuration where the input terminating resistor, RT, has been set to match the source impedance, RS (see Figure 1). EN 2 NF = 10 log 2 + kTRS NOISE PERFORMANCE The OPA842 complements its ultra low harmonic distortion with low input noise terms. Both the input-referred voltage noise and the two input-referred current noise terms combine to give a low output noise under a wide variety of operating conditions. Figure 7 shows the op amp noise analysis model IBI RF 2 4kTRF + NG NG kT = 4E − 21J at 290°K (5) Evaluating Equation 5 for the circuit of Figure 1 gives a noise figure = 17.6dB. DC OFFSET CONTROL ENI EO OPA842 RS IBN ERS RF √4kTRS 4kT RG RG IBI √4kTRF 4kT = 1.6E – 20J at 290°K FIGURE 7. Op Amp Noise Analysis Model. with all the noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. The total output spot noise voltage is computed as the square root of the squared contributing terms to the output noise voltage. This computation is adding all the contributing noise powers at the output by superposition, then taking the square root to get back to a spot noise voltage. Equation 3 shows the general form for this output noise voltage using the terms presented in Figure 7. EO = ENI 2 + (IBN RS )2 + 4kTRS NG2 + (IBI RF )2 + 4kTRF NG (3) Dividing this expression by the noise gain (NG = 1 + RF/RG) will give the equivalent input referred spot noise voltage at the noninverting input, as shown in Equation 4. The OPA842 can provide excellent DC signal accuracy due to its high open-loop gain, high common-mode rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full advantage of this low input offset voltage, careful attention to input bias current cancellation is also required. The high-speed input stage for the OPA842 has a relatively high input bias current (20µA typ into the pins) but with a very close match between the two input currents—typically 0.35µA input offset current. The total output offset voltage may be considerably reduced by matching the source impedances looking out of the two inputs. For example, one way to add bias current cancellation to the circuit of Figure 1 would be to insert a 175Ω series resistor into the noninverting input from the 50Ω terminating resistor. When the 50Ω source resistor is DC-coupled, this will increase the source impedance for the noninverting input bias current to 200Ω. Since this is now equal to the impedance looking out of the inverting input (RF || RG), the circuit will cancel the gains for the bias currents to the output leaving only the offset current times the feedback resistor as a residual DC error term at the output. Using a 402Ω feedback resistor, this output error will now be less than 1µA • 402Ω = 0.4mV at 25°C. THERMAL ANALYSIS The OPA842 will not require heat sinking or airflow in most applications. Maximum desired junction temperature would set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed +175°C. Operating junction temperature (TJ ) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is OPA842 SBOS267C www.ti.com 15 simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this worst-case condition, PDL = VS2/(4 • RL), where RL includes feedback network loading. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA842IDBV (SOT23-5 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C. PD = 10V(22.5mA) + 52/(4 • (100Ω || 800Ω)) = 291mW Maximum TJ = +85°C + (0.29W • 150°C/W) = 129°C BOARD LAYOUT Achieving optimum performance with a high-frequency amplifier such as the OPA842 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA842. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wire-wound type resistors in a highfrequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should 16 also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5kΩ, this parasitic capacitance can add a pole and/or a zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load-driving considerations. It has been suggested here that a good starting point for design would be to set RG || RF ≤ 200Ω. Doing this will automatically keep the resistor noise terms low, and minimize the effect of their parasitic capacitance. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an RS since the OPA842 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA842 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and input impedance of the destination device; this total effective impedance should be set to match the trace impedance. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be seriesterminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA842 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it OPA842 www.ti.com SBOS267C almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA842 onto the board. INPUT AND ESD PROTECTION The OPA842 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are currents are possible (e.g., in systems with ±15V supply parts driving into the OPA842), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. Figure 9 shows an example protection circuit for I/O voltages that may exceed the supplies. +VCC +5V 50Ω Source External Pin Power-supply decoupling not shown. 174Ω V1 50Ω 50Ω D1 –VCC D2 OPA842 VO FIGURE 8. Internal ESD Protection. RF 301Ω 50Ω relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 8. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher 301Ω RG D1 = D2 IN5911 (or equivalent) FIGURE 9. Gain of +2 with Input Protection. OPA842 SBOS267C –5V www.ti.com 17 Revision History DATE REVISION PAGE 12/08 C 2 3/06 B 13 SECTION DESCRIPTION Absolute Maximum Ratings Changed minimum Storage Temperature Range from −40°C to −65°C. Design-In Tools Board part number changed. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 18 OPA842 www.ti.com SBOS267C PACKAGE OPTION ADDENDUM www.ti.com 16-Feb-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty OPA842ID ACTIVE SOIC D 8 OPA842IDBVR ACTIVE SOT-23 DBV OPA842IDBVRG4 ACTIVE SOT-23 OPA842IDBVT ACTIVE OPA842IDBVTG4 75 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA842IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA842IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA842IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-May-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) OPA842IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.1 1.39 4.0 OPA842IDBVT SOT-23 DBV 5 250 OPA842IDR SOIC D 8 2500 180.0 8.4 3.2 3.1 1.39 330.0 12.4 6.4 5.2 2.1 Pack Materials-Page 1 W Pin1 (mm) Quadrant 8.0 Q3 4.0 8.0 Q3 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 20-May-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA842IDBVR SOT-23 DBV 5 3000 190.5 212.7 31.8 OPA842IDBVT SOT-23 DBV 5 250 190.5 212.7 31.8 OPA842IDR SOIC D 8 2500 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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