Product Specification PE4231 SPDT High Power UltraCMOS™ DC – 1.3 GHz RF Switch Product Description The PE4231 SPDT High Power UltraCMOS™ RF Switch is designed to cover a broad range of applications from DC to 1.3 GHz. This single-supply reflective switch integrates on-board CMOS control logic driven by a simple, single-pin CMOS or TTL compatible control input. Using a nominal +3-volt power supply, a typical input 1 dB compression point of +32 dBm can be achieved. The PE4231 also exhibits input-output isolation of better than 42 dB at 1.0 GHz and is offered in a small 8-lead MSOP package. Features • Optimized for 75 Ω systems • Single +3-volt power supply • Low insertion loss: 0.80 dB at 1.0 GHz • High isolation: 42 dB at 1.0 GHz • Typical input 1 dB compression point of +32 dBm • Single-pin CMOS or TTL logic control The PE4231 SPDT High Power UltraCMOS™ RF Switch is manufactured in Peregrine’s patented Ultra Thin Silicon (UTSi®) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. • Low cost Figure 2. Package Type Figure 1. Functional Diagram 8-lead MSOP RFCommon RF1 RF2 CMOS Control Driver CTRL Table 1. Electrical Specifications @ +25 °C, VDD = 3 V (ZS = ZL = 75 Ω) Parameter Operation Frequency Conditions Minimum 1 Typical DC Maximum Units 1300 MHz 50 MHz 0.50 0.60 1000 MHz 50 MHz 0.90 73 0.80 75 1000 MHz 50 MHz 40 58 42 60 1000 MHz 33 35 Return Loss 1000 MHz 16 17 dB ‘ON’ Switching Time CTRL to 0.1 dB final value, 2 GHz 2000 ns ‘OFF’ Switching Time CTRL to 25 dB isolation, 2 GHz 900 ns 15 mVpp 32 dBm Insertion Loss Isolation – RFCommon to RF1/RF2 Isolation – RF1 to RF2 2 Video Feedthrough 3 Input 1 dB Compression 3 Input IP3 Notes: 1000 MHz 30 1000 MHz, 17 dBm 50 dB dB dB dBm 1. Device linearity will begin to degrade below 1 MHz. 2. Measured with a 1 ns risetime, 0/3 V pulse and 500 MHz bandwidth. 3. Measured in a 50 Ω system. Document No. 70-0097-01 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 7 PE4231 Product Specification Figure 3. Pin Configuration (Top View) Table 4. DC Electrical Specifications Parameter VDD 1 8 RF1 VDD Power Supply Voltage IDD Power Supply Current CTRL 2 7 GND (VDD = 3V, VCNTL = 3V) GND 3 6 GND RFCommon 4 5 RF2 4231 Control Voltage High Min Typ Max Units 2.7 3.0 3.3 V 29 35 µA Control Voltage Low Pin Name 1 VDD 2 CTRL 0.3xVDD V Table 5. Truth Table Table 2. Pin Descriptions Pin No. V 0.7xVDD Description Nominal +3 V supply connection. CMOS or TTL logic level: High = RFCommon to RF1 signal path Low = RFCommon to RF2 signal path Ground connection. Traces should be physically short and connected to ground 3 GND 4 RF Common 5 RF2 RF2 port.1 6 GND Ground Connection. Traces should be physically short and connected to ground 7 GND Ground Connection. Traces should be physically short and connected to ground 8 RF1 RF1 port.1 Common RF port for switch.1 Control Voltage Signal Path CTRL = CMOS or TTL High CTRL = CMOS or TTL Low RFCommon to RF1 RFCommon to RF2 The control logic input pin (CTRL) is typically driven by a 3-volt CMOS logic level signal, and has a threshold of 50% of VDD. For flexibility to support systems that have 5-volt control logic drivers, the control logic input has been designed to handle a 5-volt logic HIGH signal. (A minimal current will be sourced out of the VDD pin when the control logic input voltage level exceeds VDD.) Latch-Up Avoidance Electrostatic Discharge (ESD) Precautions Note 1: All RF pins must be DC blocked with an external series capacitor or held at 0 VDC. Table 3. Absolute Maximum Ratings Symbol VDD VI VCTRL TST TOP PIN VESD Parameter/ Conditions Power supply voltage Voltage on any input except for the CTRL input Min Max Units -0.3 4.0 VDD+ 0.3 V -0.3 Voltage on CTRL input V -65 150 °C -40 85 °C Input power (50Ω) 33 dBm ESD voltage (Human Body Model) 200 V ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 7 When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 3. V 5.0 Storage temperature range Operating temperature range Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Document No. 70-0097-01 │ UltraCMOS™ RFIC Solutions PE4231 Product Specification Typical Performance Data @ -40 °C to 85 °C (Unless Otherwise Noted) Figure 4. Insertion Loss – RFC to RF1 Figure 5. Input 1dB Compression Point 40 0 -40 8C -0.25 1dB Compression Point (dBm) Insertion Loss (dB) -40 8C -0.5 -0.75 85 8C 25 8C -1 30 85 8C 25 8C 20 10 -1.25 0 -1.5 0 200 400 600 800 1000 0 1200 200 400 Frequency (MHz) Figure 6. Insertion Loss – RFC to RF2 800 1000 1200 Figure 7. Isolation – RFC to RF1 0 0 -0.25 -20 -40 8C -0.5 Isolation (dB) Insertion Loss (dB) 600 Frequency (MHz) -0.75 85 8C 25 8C -40 -60 -1 -80 -1.25 -1.5 0 200 400 600 800 Frequency (MHz) Document No. 70-0097-01 │ www.psemi.com 1000 1200 -100 0 200 400 600 800 1000 1200 Frequency (MHz) ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 7 PE4231 Product Specification Typical Performance Data @ -40 °C to 85 °C (Unless Otherwise Noted) Figure 9. Isolation – RF1 to RF2, RF2 to RF1 0 0 -20 -20 -40 -40 Isolation (dB) Isolation (dB) Figure 8. Isolation – RFC to RF2 -60 RF2 RF1 -60 -80 -80 -100 -100 0 200 400 600 800 1000 0 1200 200 400 600 800 1000 1200 Frequency (MHz) Frequency (MHz) Figure 10. Return Loss – RFC Figure 11. Return Loss – RF1, RF2 0 0 -10 -10 Return Loss (dB) Return Loss (dB) RF2 -20 -30 -20 RF1 -30 -40 -40 0 200 400 600 800 1000 1200 Frequency (MHz) ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 7 0 200 400 600 800 1000 1200 Frequency (MHz) Document No. 70-0097-01 │ UltraCMOS™ RFIC Solutions PE4231 Product Specification Figure 8. Evaluation Board Layouts Evaluation Kit The SPDT Switch Evaluation Kit board was designed to ease customer evaluation of the PE4231 SPDT switch. The RF common port is connected through a 75 Ω transmission line to the top left BNC connector, J1. Port 1 and Port 2 are connected through 75 Ω transmission lines to the top two BNC connectors on the right side of the board, J2 and J3. A through transmission line connects BNC connectors J4 and J5. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board is constructed of a two metal layer FR4 material with a total thickness of 0.031”. The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 0.021”, trace gaps of 0.030”, dielectric thickness of 0.028”, metal thickness of 0.0014” and εr of 4.4. J6 provides a means for controlling DC and digital inputs to the device. Starting from the lower left pin, the second pin to the right (J6-3) is connected to the device CNTL input. The fourth pin to the right (J6-7) is connected to the device VDD input. A decoupling capacitor (100 pF) is provided on both CNTL and VDD traces. It is the responsibility of the customer to determine proper supply decoupling for their design application. Removing these components from the evaluation board has not been shown to degrade RF performance. Figure 9. Evaluation Board Schematic J6-7 100 pF VDD RF1 CNTL GND GND GND RFC RF2 J2 Optional J6-3 100 pF Optional J1 J3 J5 Document No. 70-0097-01 │ www.psemi.com J4 ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 7 PE4231 Product Specification Figure 14. Package Drawing 8-lead MSOP TOP VIEW 0.65BSC .525BSC 7 8 6 12o REF 5 R 0.90 MIN 2.45±0.10 2X R 0.90 MIN GAGE PLANE 3.00±0.10 0o 0.25 6o 12o REF 0.55 ±0.15 0.51±0.13 -B- 1 0.51±0.13 2 3 4 .25 0.95 BSC A B C -C- 2.95±0.10 0.86±0.08 2.95±0.10 1.10 MAX -A0.10 A 0.33 0.08 +0.07 -0.08 0.10±0.05 3.00±0.10 4.90±0.15 A B C 3.00±0.10 FRONT VIEW SIDE VIEW Table 6. Ordering Information Order Code Part Marking Description Package 4231-01 4231 PE4231-08MSOP-50A 8-lead MSOP 50 units / Tube 4231-02 4231 PE4231-08MSOP-2000C 8-lead MSOP 2000 units / T&R 4231-00 PE4231-EK PE4231-08MSOP-EK Evaluation Kit 1 / Box 4231-51 4231 PE4231G-08MSOP-50A Green 8-lead MSOP 50 units / Tube 4231-52 4231 PE4231G-08MSOP-2000C Green 8-lead MSOP 2000 units / T&R ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 7 Document No. 70-0097-01 Shipping Method │ UltraCMOS™ RFIC Solutions PE4231 Product Specification Sales Offices United States Japan Peregrine Semiconductor Corp. Peregrine Semiconductor K.K. 9450 Carroll Park Drive San Diego, CA 92121 Tel 1-858-731-9400 Fax 1-858-731-9499 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: 011-81-3-3502-5211 Fax: 011-81-3-3502-5213 Europe China Peregrine Semiconductor Europe Peregrine Semiconductor Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: 011- 33-1-47-41-91-73 Fax : 011-33-1-47-41-91-73 28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: 011-86-21-5836-8276 Fax: 011-86-21-5836-7652 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0097-01 │ www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS is a trademark of Peregrine Semiconductor Corp. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 7