SAMSUNG KS57C0002

KS57C0002/0004
S M SUN G
4-BIT CMOS Microcontroller
Product Specification
OVERVIEW
The KS57C0002/0004 single-chip CMOS microcontroller is designed for high-performance using Samsung's
newest 4-bit CPU core. With a four-channel comparator, eight LED direct drive pins, serial I/O interface, and a
versatile
8-bit timer/countkxcellent design solution for a variety of general-purpose applications.
Up to 24 pins of the 30-pin SDIP package can be dedicated to I/O. Five vectored interrupts provide fast response
to internal and external events. In addition, the KS57C0002/0004's advanced CMOS technology ensures low
power consumption and a wide operating voltage range.
FEATURES
Memory
•
•
256 × 4-bit data memory
(KS57C0002)
512 × 4-bit data memory
(KS57C0004)
2048 × 8-bit program memory
(KS57C0002)
4096 × 8-bit program memory
(KS57C0004)
•
Watch Timer
•
•
Interval generation: 0.5 s,
3.9ms at 32768 Hz
Four frequency outputs to the
BUZ pin
8-Bit Serial I/O Interface
Stop mode (system clock
stops)
Oscillation Sources
•
Crystal, ceramic, or RC for
system clock (RC is only for
the KS57C0002)
•
Crystal, ceramic: 4.19 MHz
(typical)
•
8-bit transmit/receive mode
24 I/O Pins
•
8-bit receive-only mode
•
RC: 1 MHz
•
I/O: 18 pins, including 8 highcurrent pins
•
LSB-first or MSB-first
transmission selectable
•
CPU clock divider circuit
(by 4, 8, or 64)
•
Input only: 6 pins
•
Internal or external clock
source
Instruction Execution Times
Comparator
•
4-channel mode with internal
reference (4-bit resolution)
and 16-step variable
reference voltage
•
3-channel mode with external
reference
•
150 mV resolution (minimum)
8-Bit Basic Timer
•
Programmable interval timer
8-Bit Timer/Counter
•
Programmable interval timer
•
External event counter
function
•
Timer/counter clock output to
TCLO0 pin
•
Bit Sequential Carrier
•
Support for 16-bit serial data
transfer in arbitrary format
0.95, 1.91, 15.3 µs at 4.19
MHz
Operating Temperature
• – 40 °C to 85 °C
Interrupts
•
Two external interrupt vectors
Operating Voltage Range
•
Three internal interrupt
vectors
•
•
Two quasi-interrupts
Memory-Mapped I/O Structure
•
Data memory bank 15
Power-Down Modes
•
Idle mode (only CPU clock
stops)
2–1
2.7 V to 6.0 V
Package Type
•
30 SDIP, 32 SOP
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
BASIC
TIMER
RESET
8-BIT
TIMER/
COUNTER
Xin
I/O PORT 3
P4.0–P4.3
I/O PORT 4
P5.0–P5.3
I/O PORT 5
Xout
STACK
POINTER
CLOCK
SERIAL
I/O
PORT
PROGRAM
COUNTER
INTERNAL
INTERRUPTS
PROGRAM
STATUS
WORD
INSTRUCTION
DECODER
ARITHMETIC
LOGIC UNIT
P6.0 / KS0
P6.1 / KS1
P6.2 / KS2
P6.3 / BUZ
P0.0 / SCK
P0.1 / SO
P0.2 / SI
I/O PORT 0
INTERRUPT
CONTROL
BLOCK
P3.0 / TCL0
P3.1 / TCLO0
P3.2 / CLO
WATCH
TIMER
INPUT
PORT 1
P1.0 / INT0
P1.1 / INT1
INPUT
PORT 2
P2.0 / CIN0
P2.1 / CIN1
P2.2 / CIN2
P2.3 / CIN3
FLAGS
I/O PORT 6
COMPARATOR
2 K/ 4 K
256 / 512
x 4-BIT
BYTE
DATA
PROGRAM
MEMORY
MEMORY
a
Figure 1. KS57C0002/0004 Block Diagram
1
30
P0.1 / SO
2
29
P0.2 / SI
3
28
P1.0 / INT0
4
27
P1.1 / INT1
5
26
P2.0 / CIN0
6
25
P2.1 / CIN1
7
24
P2.2 / CIN2
8
P2.3 / CIN3
9
22
P3.0 / TCL0
10
21
P3.1 / TCLO0
11
20
P3.2 / CLO
12
19
RESET
13
18
TEST
14
17
V SS
15
16
P0.0 /
SCK
A
KS57C0002/04
(Top View)
23
P0.0/ SCK
1
32
VDD
P6.3 / BUZ
P0.1/SO
2
31
P6.3/BUZ
P6.2 / KS2
P0.2/SI
3
30
P6.2/KS2
P6.1 / KS1
P1.0/INT0
4
29
P6.1/KS1
P6.0 / KS0
NC
5
28
P6.0/KS0
P5.3
P1.1/INT1
6
27
P5.3
P5.2
P2.0/CIN0
7
26
P5.1
8
KS57C0002/04
25
(Top View)
P5.2
P2.1/CIN1
P5.0
P2.2/CIN2
9
24
P5.0
P4.3
P2.3/CIN3
10
23
P4.3
P4.2
P3.0/TCL0
11
22
P4.2
P4.1
P3.1/TCLO0
12
21
NC
P4.0
P3.2/CLO
13
20
P4.1
Xout
RESET
14
19
P4.0
TEST
15
18
Xout
VSS
16
17
Xin
V DD
Xin
30 SDIP
P5.1
32 SOP
Figure 2. KS57C0002/0004 Pin Assignments (32 SOP, 30 SDIP)
S MSUN G
September 1996
2–2
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Table 1. KS57C0002/0004 Pin Descriptions
Pin Name
Pin Type
Description
Number
Share Pin
P0.0
P0.1
P0.2
I/O
3-bit I/O port. 1-bit or 3-bit read/write and test is
possible. Pull-up resistors are assignable to input pins
by software and are automatically disabled for output
pins. Pins are individually configurable as input or
output.
1
2
3
SCK
P1.0
P1.1
I
2-bit input port. 1-bit or 2-bit read and test is possible.
Pull-up resistors are assignable by software.
4
5
INT0
INT1
P2.0–P2.3
I
4-bit input port. 1-bit or 4-bit read and test is possible.
6–9
CIN0–CIN3
10
11
12
TCL0
TCLO0
CLO
SO
SI
P3.0
P3.1
P3.2
I/O
Same as port 0
P4.0–P4.3
P5.0–P5.3
I/O
4-bit I/O ports.
1-, 4-, or 8-bit read/write and test is possible.
Pins are individually configurable as input or output.
Ports can be configurable as n-channel open-drain by
mask option (maximum 9V).
18–21
22–25
—
P6.0
P6.1
P6.2
P6.3
I/O
4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Pull-up resistors are assignable to input pins by
software and are automatically disabled for output
pins. Pins individually configurable as input or output.
26
27
28
29
KS0
KS1
KS2
BUZ
INT0
I
External interrupts with rising/falling edge detection
4
P1.0
INT1
I
External interrupts with rising/falling edge detection
5
P1.1
CIN0–CIN3
I
4-channel comparator input.
CIN0–CIN2: comparator input only.
CIN3: comparator input or external reference input
6–9
P2.0–P2.3
SCK
I/O
Serial interface clock signal
1
P0.0
SO
I/O
Serial data output
2
P0.1
SI
I/O
Serial data input
3
P0.2
TCL0
I/O
External clock input for timer/counter
10
P3.0
TCLO0
I/O
Timer/counter clock output
11
P3.1
CLO
I/O
CPU clock output
12
P3.2
BUZ
I/O
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at
4.19 MHz for buzzer sound
29
P6.3
KS0–KS2
I/O
Quasi-interrupt input with falling edge detection
26–28
P6.0–P6.2
V DD
—
Main power supply
30
—
V SS
—
Ground
15
—
RESET
I
Reset signal
13
—
TEST
I
Test signal input (must be connected to VSS)
14
—
X in, Xout
—
Crystal, ceramic, or RC oscillator signal for system
clock
16, 17
—
S MSUN G
ELECTRONICS
2–3
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
Table 2. Supplemental KS57C0002/0004 Pin Data
Pin Numbers
Pin Names
Share Pins
Reset Value
Circuit Type
I/O
Input
5
1, 2, 3
P0.0–P0.2
4, 5
P1.0, P1.1
INT0, INT1
I
Input
3
6–9
P2.0–P2.3
CIN0–CIN3
I
Input
6, 8 *
10–12
P3.0–P3.2
TCL0, TCLO0, CLO
I/O
Input
5
13
RESET
—
I
—
9
14
TEST
—
I
—
—
15
V SS
—
—
—
—
16, 17
Xin, Xout
—
—
—
—
18–21
P4.0–P4.3
—
I/O
Input
7
22–25
P5.0–P5.3
—
I/O
Input
7
26–29
P6.0–P6.3
KS0, KS1, KS2,
BUZ
I/O
Input
5
30
V DD
—
—
—
—
*
SCK
, SO, SI
I/O Type
I/O circuit type 8 is for P2.3 only.
S MSUN G
September 1996
2–4
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
VDD
VDD
P-CHANNEL
P-CHANNEL
DATA
OUT
IN
N-CHANNEL
N-CHANNEL
OUTPUT
DISABLE
Figure 6. Pin Circuit Type 4
Figure 3. Pin Circuit Type 1
VDD
PULL-UP
RESISTOR
RESISTOR
ENABLE
IN
DATA
SCHMITT TRIGGER
OUTPUT
DISABLE
P-CHANNEL
CIRCUIT
TYPE 4
I/O
CIRCUIT TYPE 2
Figure 7. Pin Circuit Type 5
Figure 4. Pin Circuit Type 2
VDD
PULL-UP
RESISTOR
DIGITAL INPUT
RESISTOR
ENABLE
P-CHANNEL
ANALOG INPUT
IN
SCHMITT TRIGGER
Figure 5. Pin Circuit Type 3
Figure 8. Pin Circuit Type 6
S MSUN G
ELECTRONICS
2–5
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
VDD
DIGITAL INPUT
P-CHANNEL
DATA
(MASK
OPTION)
ANALOG INPUT
N-CHANNEL
OUTPUT
DISABLE
EXTERNAL VREF
MAXIMUM INPUT VOLTAGE: 9 V
Figure 10. Pin Circuit Type 8
Figure 9. Pin Circuit Type 7
VDD
IN
Schmitt Trigger Input
Figure 11. Pin Circuit Type 9
S MSUN G
September 1996
2–6
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
PROGRAM MEMORY (ROM)
— 16-byte general-purpose area
— 16-byte area for vector addresses
ROM maps for KS57C0002/0004 devices are mask
programmable at the factory. In their standard
configuration, the device's 2048 × 8-bit (KS57C0002),
or 4096 × 8-bit (KS57C0004) program memory has
four areas that are directly addressable by the
program counter ( PC):
— 96-byte instruction reference area
— 1920-byte (KS57C0002), 3968-byte (KS57C0004)
general-purpose area
0000H
VECTOR
ADDRESS AREA
7
000FH
0010H
GENERAL-PURPOSE
AREA
001FH
0020H
INSTRUCTION
REFERENCE AREA
6
5
4
3
0000H
RESET
0002H
INTB
0004H
INT0
0006H
INT1
0008H
INTS
000AH
INTT0
2
1
0
007FH
0080H
KS57C0002
GENERAL-PURPOSE
AREA 1
07FFH
0800H
KS57C0004
GENERAL-PURPOSE
AREA 2
0FFFH
Figure 12. ROM Map
Figure 13. Vector Address Map
DATA MEMORY (RAM)
— 256×4 -bit general-purpose area in bank1
(KS57C0004 only)
In its standard configuration, the 256× 4 -bit
(KS57C0002), or the 512 ×4-bit (KS57C0004) data
memory has four areas:
— 128× 4-bit area in bank 15 for memory-mapped
I/O addresses
— 32 ×4-bit working registers
I/O MAP FOR HARDWARE REGISTERS
— 224× 4-bit general-purpose area in bank0 which
is also used as the stack area
Table 3 contains detailed information about I/O
mapping for peripheral hardware in bank 15 (register
locations F80H–FFFH).
S MSUN G
ELECTRONICS
2–7
September 1996
KS57C0002 /0004 MICROCONTROLLER
ADDRESSING
MODE
RAM
AREAS
PRODUCT SPECIFICATION
DA
DA.b
EMB = 0
EMB = 1
@HL
@H + DA.b
EMB = 0
EMB = 1
@WX
@WL
mema.b
memb.@L
X
X
X
000 H
01FH
020 H
07FH
080 H
WORKING
REGISTERS
BANK 0
(GENERAL
REGISTERS
AND STACK)
SMB = 0
SMB = 0
SMB = 1
SMB = 1
0FFH
100 H
BANK 1
KS57C0004
ONLY
(GENERAL
REGISTERS)
1FFH
F80H
BANK 15
(PERIPHERAL
HARDWARE
REGISTERS)
FB0H
FBFH
FC0H
SMB = 15
SMB = 15
FF0H
FFFH
NOTES: 1. 'X' means don't care.
2. Blank columns indicate RAM areas that are not addressable, given the addressing method
and enable memory bank (EMB) flag setting shown in the column headers.
Figure 14. Data Memory (RAM) Address Structure
S MSUN G
September 1996
2–8
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Table 3. I/O Map for Memory Bank 15
Memory Bank 15
Addressing Mode
Address
Register
Name
R/W
1-Bit
4-Bit
8-Bit
F81H–F80H
SP
Stack Pointer
R/W
No
No
Yes
F85H
BMOD
Basic Timer Mode Register
W
.3
Yes
No
F87H–F86H
BCNT
Basic Timer Counter Register
R
No
No
Yes
F89H–F88H
WMOD
Watch Timer Mode Register
W
No
No
Yes
F91H–F90H
TMOD0
Timer/Counter 0 Mode Register
W
.3
No
Yes
F95H–F94H
TCNT0
Timer/Counter 0 Counter Register
R
No
No
Yes
F97H–F96H
TREF0
Timer/Counter 0 Reference Reg
W
No
No
Yes
FB0H
PSW
Yes
FB1H
IS1
IS0
EMB
ERB
R/W
Yes
Yes
C (2)
SC2
SC1
SC0
R
No
No
FB2H
IPR
SIO Mode Register
W
IME
Yes
No
FB3H
PCON
Power Control Register
W
No
Yes
No
FB4H
IMOD0
External Interrupt 0 Mode Register
W
No
Yes
No
FB5H
IMOD1
External Interrupt 1 Mode Register
W
No
Yes
No
FB6H
IMODK
External Key Interrupt Mode Reg
W
No
Yes
No
FB8H
"0"
"0"
IEB
IRQB
R/W
Yes
Yes
No
FBAH
"0"
"0"
IEW
IRQW
R/W
Yes
Yes
No
FBCH
"0"
"0"
IET0
IRQT0
R/W
Yes
Yes
No
FBDH
"0"
"0"
IES
IRQS
FBEH
IE1
IRQ1
IE0
IRQ0
FBFH
"0"
"0"
IEK
IRQK
R/W
Yes
Yes
Yes
FC0H
BSC0
Bit Sequential Carrier 0
FC1H
BSC1
Bit Sequential Carrier 1
FC2H
BSC2
Bit Sequential Carrier 2
FC3H
BSC3
Bit Sequential Carrier 3
FD0H
CLMOD
Clock Mode Register
W
No
Yes
No
FD4H
CMPREG
Comparison Result Register
R
No
Yes
No
FD7H–FD6H
CMOD
Comparator Mode Register
R/W
No
No
Yes
FDDH–FDCH
PUMOD
Pull-up Mode Register
W
No
No
Yes
FE1H–FE0H
SMOD
SIO Mode Register
W
.3
No
Yes
FE2H
P2MOD
Port 2 Mode Register
W
No
Yes
No
FE5H–FE4H
SBUF
SIO Buffer Register
R/W
No
No
Yes
FE9H–FE8H
PMG1
Port Mode Group 1
W
No
No
Yes
FEBH–FEAH
PMG2
Port Mode Group 2
S MSUN G
ELECTRONICS
2–9
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
Table 3. I/O Map for Memory Bank 15 (Concluded)
Memory Bank 15
Addressing Mode
Address
Register
Name
R/W
1-Bit
4-Bit
8-Bit
FEDH–FECH
PMG3
Port Mode Group 3
W
No
No
Yes
FF0H
P0
Port 0
R/W
Yes
Yes
No
FF1H
P1
Port 1
R
No
FF2H
P2
Port 2
R
No
FF3H
P3
Port 3
R/W
No
FF4H
P4
Port 4
R/W
Yes
FF5H
P5
Port 5
R/W
FF6H
P6
Port 6
R/W
No
NOTES:
1. Bit 0 in the WMOD register must be set to "0".
2. The carry flag can be read or written by specific bit manipulation instructions only.
S MSUN G
September 1996
2–10
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
BIT SEQUENTIAL CARRIER (BSC)
incrementing or decrementing the value of the L
register.
The bit sequential carrier (BSC) is a 16-bit general
register that is mapped in data memory bank 15.
Using the BSC, you can specify sequential addresses
and bit locations using 1-bit indirect addressing
(memb.@L).
For 8-bit manipulations, the 4-bit register names
BSC0 and BSC2 must be specified and the upper and
lower 8 bits manipulated separately. If the values of
the L register are 0H at BSC0.@L, the address and bit
location assignment is FC0H.0. If the L register
content is FH at BSC0.@L, the address and bit
location assignment is FC3H.3.
BSC bit addressing is independent of the current EMB
value. In this way, programs can process 16-bit data
by moving the bit location sequentially and then
Table 4. BSC Register Organization
Name
Address
Bit 3
Bit 2
Bit 1
Bit 0
BSC0
FC0H
BSC0.3
BSC0.2
BSC0.1
BSC0.0
BSC1
FC1H
BSC1.3
BSC1.2
BSC1.1
BSC1.0
BSC2
FC2H
BSC2.3
BSC2.2
BSC2.1
BSC2.0
BSC3
FC3H
BSC3.3
BSC3.2
BSC3.1
BSC3.0
☞ PROGRAMMING TIP — Using the BSC Register to Output 16-Bit Data
To use the bit sequential carrier (BSC) register to output 16-bit data (5937H) to the P3.0 pin:
AGN LDB
BITS
EMB
SMB
15
LD
EA,#37H
LD
BSC0,EA
LD
EA,#59H
LD
BSC2,EA
SMB
0
LD
L,#0H
C,BSC0.@L
LDB
P3.0,C
INCS
L
JR
AGN
RET
;
;
;
;
;
;
;
BSC0 ← A, BSC1 ← E
BSC2 ← A, BSC3 ← E
P3.0 ← C
S MSUN G
ELECTRONICS
2–11
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
INTERRUPTS
The KS57C0002/0004 microcontroller has two external interrupts, three internal interrupts, and two quasiinterrupts. Table 5 shows the conditions for each interrupt generation. The request flags that actually generate
these interrupts are cleared by hardware when the service routine is vectored. However, the quasi-interrupt's
request flags must be cleared by software.
IMOD1
IMOD0
IEK
INTB
INT0
INT1
#
IEW
IET0
IES
IE1
IE0
IEB
IRQB
IRQ0
@
IRQ1
@
INTS
IRQS
INTT0
IRQT0
INTW
IRQW
IRQK
INTK (KS0–KS2)
IMODK
POWER-DOWN
MODE
RELEASE SIGNAL
IME
IPR
INTERRUPT CONTROL UNIT
IS1 IS0
VECTOR INTERRUPT
GENERATOR
# = Noise filtering circuit
@ = Edge detection circuit
Figure 15. Interrupt Control Circuit Diagram
S MSUN G
September 1996
2–12
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Table 5. Interrupt Request Flag Conditions and Priorities
*
Interrupt
Source
Internal /
External
INTB
I
INT0
Condition for IRQx Flag Setting
Interrupt
Priority
Request Flag
Name
Reference time interval signal from basic timer
1
IRQB
E
Rising or falling edge detected at INT0 pin
2
IRQ0
INT1
E
Rising or falling edge detected at INT1 pin
3
IRQ1
INTS
I
Completion signal for serial transmit-and-receive
or receive-only operation
4
IRQS
INTT0
I
Signals for TCNT0 and TREF0 registers match
5
IRQT0
INTK *
E
Falling edge is detected at any of the KS0–KS2
pins
—
IRQK
INTW *
I
Time interval of 0.5 s or 3.19 ms
—
IRQW
The INTK and INTW are quasi-interrupts and INTK are used only for testing incoming signals.
INTERRUPT ENABLE FLAGS (IEx)
INTERRUPT PRIORITY
IEx flags, when set to "1", enable specific interrupt
requests to be serviced. When the interrupt request
flag is set to "1", an interrupt will not be serviced until
its corresponding IEx flag is also enabled. The IPR
register contains a global disable bit, IME, which
disables all interrupt at once.
Each interrupt source can also be individually
programmed to high levels by modifying the IPR
register. When IS1 = 0 and IS0 = 1, a low-priority
interrupt can itself be interrupted by a high-priority
interrupt, but not by another low-priority interrupt.
If you clear the interrupt status flags (IS1 and IS0) to
"0" in a interrupt service routine, a high-priority
interrupt can be interrupted by low-priority interrupt
(multi-level interrupt). Before the IPR can be modified
by 4-bit write instructions, all interrupts must first be
disabled by a DI instruction.
Table 6. Interrupt Enable and Request Flag
Address
Bit 3
Bit 2
Bit 1
Bit 0
FB8H
0
0
IEB
IRQB
FBAH
0
0
IEW
IRQW
FBBH
0
0
0
0
FBCH
0
0
IET0
IRQT0
FBDH
0
0
IES
IRQS
FBEH
IE1
IRQ1
IE0
IRQ0
FBFH
0
0
IEK
IRQK
When all interrupts are low priority (the lower three
bits of the IPR register are "0"), the interrupt
requested first will have high priority. Therefore, the
first-requested interrupt cannot be superseded by any
other interrupt.
If two or more interrupt requests are received
simultaneously, the priority level is determined
according to the standard interrupt priorities, where
the default priority is assigned by hardware when the
lower three IPR bits = "0".
NOTES:
1. IEx refers to all interrupt enable flags.
2. IRQx refers to all interrupt request flags.
3. IEx = "0" is interrupt disable mode.
4. IEx = "1" is interrupt enable mode.
S MSUN G
ELECTRONICS
2–13
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
In this case, the higher-priority interrupt request is
serviced and the other interrupt is inhibited. Then,
when the high-priority interrupt is returned from its
service routine by an IRET instruction, the inhibited
service routine is started.
EXTERNAL INTERRUPTS
The external interrupt mode registers (IMOD0 and
IMOD1) are used to control the triggering edge of the
input signal at the INT0 and INT1 pins, respectively.
When a sampling clock rate of fx/64 is used for INT0,
an interrupt request flag must be cleared before 16
machine cycles have elapsed. Since the INT0 pin has
a clock-driven noise filtering circuit built into it, please
take the following precautions when you use it:
Table 7. Interrupt Priority Register Settings
IPR.2
IPR.1
IPR.0
Result of IPR Bit Setting
0
0
0
Process all interrupt
requests at low priority.
0
0
1
INTB
0
1
0
INT0
0
1
1
INT1
1
0
0
INTS
1
0
1
INTT0
— To trigger an interrupt, the input signal width at
INT0 must be at least two times wider than the
pulse width of the clock selected by IMOD0. This
is true even when the INT0 pin is used for
general-purpose input.
— Since the INT0 input sampling clock does not
operate during Stop or Idle mode, you cannot use
INT0 to release power-down mode.
When modifying the IMOD0 and IMOD1 registers, it is
possible to accidentally set an interrupt request flag.
Table 8. Default Priorities
Source
Default Priority
INTB
1
To avoid unwanted interrupts, take these precautions
when writing your programs:
INT0
2
1. Disable all interrupts with a DI instruction.
INT1
3
2. Modify the IMOD0 or IMOD1 register.
INTS
4
3. Clear all relevant interrupt request flags.
INTT0
5
4. Enable the interrupt by setting the appropriate IEx
flag.
5. Enable all interrupts with an EI instructions.
Table 9. IMOD0 and IMOD1 Register Organization (4-Bit W)
IMOD0.3
0
IMOD0.1
IMOD0.0
Effect of IMOD0 Settings
0
Select CPU clock for sampling
1
Select fx/64 sampling clock
0
0
0
Rising edge detection
0
0
1
Falling edge detection
0
1
0
Both rising and falling edge detection
0
1
1
IRQ0 flag cannot be set to "1"
0
0
0
IMOD1.0
0
0
0
0
Rising edge detection
0
0
0
1
Falling edge detection
Effect of IMOD1 Settings
S MSUN G
September 1996
2–14
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
EXTERNAL KEY INTERRUPT MODE REGISTER
The external key interrupt (INTK) mode register, IMODK, is used to select KS pins as interrupt input pins. When a
falling edge is detected at one of the KS0–KS2 pins, the IRQK flag is set to "1". This generates an interrupt
request and a release signal for power-down mode. To generate a key interrupt on a falling signal edge at KS0–
KS2, all of the KS0–KS2 pins must be configured to input mode.
If one or more of the pins which are configured as key Interrupt (KS0–KS2) are in Low input or Low output state,
the key Interrupt can not be occurred.
Table 10. IMODK Register Bit Settings (4-Bit W)
0
IMODK.2
IMODK.1
IMODK.0
Effect of IMODK Settings
0
0
0
0
Disable key interrupt
0
0
0
1
Select falling edge at KS0
0
0
1
0
Select falling edge at KS1
0
0
1
1
Select falling edge at KS0–KS1
0
1
0
0
Select falling edge at KS2
0
1
0
1
Select falling edge at KS0, KS2
0
1
1
0
Select falling edge at KS1–KS2
0
1
1
1
Select falling edge at KS0–KS2
KS2
KS1
KS0
FALLING
EDGE
DETECTION
CIRCUIT
IMODK
IRQK
NOTE: To generate a key interrupt on a falling edge at KS0–KS2, all KS0–KS2 pins must be
configured to input mode.
Figure 15-1. Circuit diagram for KS0-KS2 Pins
S MSUN G
ELECTRONICS
2–15
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
OSCILLATOR CIRCUITS
The KS57C0002/0004 system clock circuit is shown in Figure 16 below. By manipulating bits 1 and 0 of the
PCON register, the system clock frequency can be divided by 4, 8, or 64.
SYSTEM
OSCILLATOR
CIRCUIT
X in
fx
X out
WATCH TIMER
BASIC TIMER
TIMER/COUNTER 0
CLOCK OUTPUT CIRCIT
COMPARATOR
FREQUENCY
DIVIDING
CIRCUIT
OSCILLATOR
STOP
1/2
1/16
CPU
CLOCK
SELECTOR
1/4
CPU STOP SIGNAL
( IDLE MODE)
PCON.0
PCON.1
IDLE
PCON.2
STOP
PCON.3
OSCILLATOR
CONTROL
CIRCUIT
WAIT RELEASE SIGNAL
INTERNAL RESET SIGNAL
POWER-DOWN RELEASE SIGNAL
PCON.3,2 CLEAR
Figure 16. Clock Circuit Diagram
S MSUN G
September 1996
2–16
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Xin
Xin
Xin
R
Xout
Xout
Xout
Figure 17. Crystal/Ceramic
Oscillator
Figure 18. External Clock
Figure 19. RC Oscillator (only
for the KS57C0002)
POWER CONTROL REGISTER (PCON)
The power control register, PCON, is used to select the CPU clock frequency and to control CPU operating and
power-down modes. PCON bits 3 and 2 are controlled by the STOP and IDLE instructions, which engage the
Stop and Idle power-down modes, respectively. Using these instructions, you can initiate a power-down mode at
any time, regardless of the current value of the enable memory bank flag (EMB).
Table 11. Power Control Register (PCON) Organization (4-Bit W)
PCON Bit Settings
Resulting CPU Operating Mode
PCON.3
PCON.2
0
0
Normal CPU operating mode
0
1
Idle power-down mode
1
0
Stop power-down mode
PCON Bit Settings
Resulting CPU Clock Frequency
PCON.1
PCON.0
0
0
fx/64
1
0
fx/8
1
1
fx/4
☞ PROGRAMMING TIP — Setting the CPU Clock
To set the CPU clock to 0.95 µs at 4.19 MHz:
BITS
SMB
LD
LD
EMB
15
A,#3H
PCON,A
S MSUN G
ELECTRONICS
2–17
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
INSTRUCTION CYCLE TIMES
The unit of time that equals one machine cycle varies depending on how the oscillator clock signal is divided.
Table 12. Instruction Cycle Times for CPU Clock Rates
Selected
CPU Clock
Resulting Frequency
fx/64
Oscillation
Source
Cycle Time (µs)
65.5 kHz
fx/8
524.0 kHz
fx/4
1.05 MHz
15.3
fx = 4.19 MHz
1.91
0.95
CLOCK OUTPUT CIRCUIT
The clock output circuit outputs clock pulses to the CLO pin. The clock output mode register, CLMOD, is used to
enable or disable clock output to the CLO pin and to select the CPU clock source and frequency. To output a
frequency, the clock output pin CLO/P3.2 must be set to output mode and the pin's latch must be cleared to "0".
Bit 2 in the CLMOD register must always be "0".
Table 13. Clock Output Mode Register (CLMOD) Organization
CLMOD Bit Settings
Resulting Clock Output
CLMOD.1
CLMOD.0
Clock Source
Frequency
0
0
CPU clock (fx/4, fx/8, fx/64)
1.05 MHz, 524 kHz, 65.5 kHz
0
1
fx/8
524 kHz
1
0
fx/16
262 kHz
1
1
fx/64
65.5 kHz
CLMOD.3
Result of CLMOD.3 Setting
0
Clock output is disabled
1
Clock output is enabled
NOTE: Frequencies assume that fx = 4.19 MHz.
CLMOD.3
C LO
CLMOD.2
4
CLMOD.1
CLMOD.0
CLOCK
SELECT OR
P3.2 OUTPUT LATCH
PM3.2
CLOCKS
(fx/8, fx/16, fx/64, CPU clock )
Figure 20. CLO Output Pin Circuit Diagram
S MSUN G
September 1996
2–18
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
☞ PROGRAMMING TIP — CPU Clock Output to the CLO Pin
To output the CPU clock to the CLO pin:
BITS
SMB
LD
LD
BITR
LD
LD
EMB
15
EA,#40H
PMG1,EA
P3.2
A,#9H
CLMOD,A
;
Or BITR EMB
;
;
P3.2 ← Output mode
Clear P3.2 output latch
POWER-DOWN
In Stop mode, system clock oscillation is halted
(assuming it is currently operating), and peripheral
hardware components are powered-down. The effect
of Stop mode on specific peripheral hardware
components — CPU, basic timer, serial I/O, timer/
counters 0, and watch timer — and on external
interrupt requests, is detailed in Table 14.
The KS57C0002/0004 microcontroller has two powerdown modes to reduce power consumption: Idle and
Stop. In Idle mode, the CPU clock stops while
peripherals and the oscillator continue to operate
normally.
Table 14. Hardware Operation During Power-Down Modes
Operation
Stop Mode (STOP)
Idle Mode (IDLE)
Clock oscillator
System clock oscillation stops
CPU clock oscillation stops (system clock
oscillation continues)
Basic timer
Basic timer stops
Basic timer operates (with IRQB set at
each reference interval)
Serial interface
Operates only if external SCK input is
selected as the serial I/O clock
Operates if a clock other than the CPU
clock is selected as the serial I/O clock
Timer/counter 0
Operates only if TCL0 is selected as the
counter clock
Timer/counter 0 operates
Comparator
Comparator operation is stopped
Comparator operates
Watch timer
Watch timer operation is stopped
Watch timer operates
External interrupts
INT1 and INTK are acknowledged; INT0
is not serviced
INT1 and INTK are acknowledged;
INT0 is not serviced
CPU
All CPU operations are disabled
All CPU operations are disabled
Power-down mode
release signal
Interrupt request signals (except INT0)
Interrupt request signals (except INT0)
are enabled by an interrupt enable flag or are enabled by an interrupt enable flag or
by RESET input
by RESET input
S MSUN G
ELECTRONICS
2–19
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
RECOMMENDED CONNECTIONS FOR UNUSED PINS
To reduce overall power consumption, please configure unused pins according to the guidelines described in
Table 15.
Table 15. Unused Pin Connections for Reduced Power Consumption
Pin/Share Pin Names
Recommended Connection
P0.0 / SCK
P0.1 / SO
P0.2 / SI
Input mode: Connect to VDD
Output mode: Do not connect
P1.0 / INT0 – P1.1 / INT1
Connect to VDD
P2.0 / CIN0
P2.1 / CIN1
P2.2 / CIN2
P2.3 / CIN3
Connect to VDD
P3.0 / TCLO0
P3.1 / TCLO1
P3.2 / CLO
P3.3 / BUZ
P4.0–P4.3, P5.0–P5.3
P6.0 / KS0 – P6.3 / BUZ
Input mode: Connect to VDD
Output mode: Do not connect
TEST
Connect to VSS
RESET
Table 16 provides detailed information about hardware register values after a RESET occurs during power-down
mode or during normal operation.
Table 16. Hardware Register Values After
Hardware Component
or Subcomponent
Program counter (PC)
RESET
If RESET Occurs During
Power-Down Mode
If RESET Occurs During
Normal Operation
Lower three bits of address 0000H Lower three bits of address 0000H
are transferred to PC10–8, and the are transferred to PC10–8, and the
contents of 0001H to PC7–0.
contents of 0001H to PC7–0.
Program Status Word (PSW):
Carry flag (C)
Retained
Undefined
Skip flag (SC0–SC2)
0
0
Interrupt status flags (IS0, IS1)
0
0
Bank enable flags (EMB, ERB)
Bit 6 of address 0000H in program
memory is transferred to the ERB
flag, and bit 7 of the address to the
EMB flag.
Bit 6 of address 0000H in program
memory is transferred to the ERB
flag, and bit 7 of the address to the
EMB flag.
Undefined
Undefined
Stack pointer (SP)
S MSUN G
September 1996
2–20
ELECTRONICS
PRODUCT SPECIFICATION
Table 16. Hardware Register Values After
Hardware Component
or Subcomponent
KS57C0002 /0004 MICROCONTROLLER
RESET
(Continued)
If RESET Occurs During
Power-Down Mode
If RESET Occurs During
Normal Operation
Values retained
Undefined
Values retained (Note 1)
Undefined
0, 0
0, 0
0
0
Power control register (PCON)
0
0
Clock output mode register (CLMOD)
0
0
Interrupt request flags (IRQx)
0
0
Interrupt enable flags (IEx)
0
0
Interrupt priority flag (IPR)
0
0
Interrupt master enable flag (IME)
0
0
INT0 mode register (IMOD0)
0
0
INT1 mode register (IMOD1)
0
0
INTK mode register (IMODK)
0
0
Output buffers
Off
Off
Output latches
0
0
Port mode flags (PM)
0
0
Pull-up resistor mode reg (PUMOD)
0
0
Port 2 mode register (PWMOD)
0
0
Count register (BCNT)
Undefined
Undefined
Mode register (BMOD)
0
0
0
0
FFH, FFFFH
FFH, FFFFH
Mode registers (TMOD0)
0
0
Output enable flags (TOE0)
0
0
Data Memory (RAM):
General registers E, A, L, H, X, W, Z,
Y
General-purpose registers
Bank selection registers (SMB, SRB)
BSC register (BSC0–BSC3)
Clocks:
Interrupts:
I/O Ports:
Basic Timer:
Timer/Counter 0:
Count registers (TCNT0)
Reference registers (TREF0)
Note1: The values of the 0F8H-0FDH are not retained when a
RESET
signal is input.
S MSUN G
ELECTRONICS
2–21
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
Table 16. Hardware Register Values After
Hardware Component
or Subcomponent
RESET
(Continued)
If RESET Occurs During
Power-Down Mode
If RESET Occurs During
Normal Operation
0
0
0
0
Undefined
Undefined
SIO mode register (SMOD)
0
0
SIO interface buffer (SBUF)
Values retained
Undefined
Watch Timer:
Watch timer mode register (WMOD)
Comparator
Comparator mode register (CMOD)
Comparison result register
Serial I/O Interface:
PORT MODE FLAGS (PM FLAGS)
I/O PORTS
Port mode flags (PM) are used to configure I/O ports
0 and 3–6 to input or output mode. It does this by
setting or clearing the corresponding I/O buffer. If a
PM bit is "0", the corresponding I/O pin is set to input
mode. If the PM bit is "1", the corresponding pin is set
to output mode.
The KS57C0002/0004 has two input ports and five I/O
ports. There are total of 6 input pins and 18
configurable I/O pins, including 8 high-current I/O
pins. This gives a total number of 24 I/O pins.
Table 17. Port Mode Flag Map
PM Group ID
PMG1
PMG2
PMG3
Address
Bit 3
Bit 2
Bit 1
Bit 0
FE8H
"0"
PM0.2
PM0.1
PM0.0
FE9H
"0"
PM3.2
PM3.1
PM3.0
FEAH
PM4.3
PM4.2
PM4.1
PM4.0
FEBH
"0"
"0"
"0"
"0"
FECH
PM5.3
PM5.2
PM5.1
PM5.0
FEDH
PM6.3
PM6.2
PM6.1
PM6.0
S MSUN G
September 1996
2–22
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
☞ PROGRAMMING TIP — Configuring I/O Ports as Input or Output
Configure P0.0 and P3.0 as an output port and the other ports as input ports:
BITS
SMB
LD
LD
LD
LD
LD
LD
EMB
15
EA,#11H
PMG1,EA
EA,#00H
PMG2,EA
EA,#00H
PMG3,EA
;
P0.0 and P3.0 ← Output
;
P4 ← Input
;
P5, P6 ← Input
PORT 2 MODE REGISTER (P2MOD)
PULL-UP RESISTOR MODE REGISTER (PUMOD)
P2MOD register settings determine if port 2 is used
either for analog input or for digital input.
The pull-up resistor mode register, PUMOD, is used
to assign internal pull-up resistors to specific I/O ports.
When a configurable I/O port pin is used as an output
pin, its assigned pull-up resistor is automatically
disabled, even though the pin's pull-up is enabled by a
corresponding PUMOD bit setting.
FE2H
4-Bit W
P2MOD.3
P2MOD.2
P2MOD.1
P2MOD.0
When bit = "1", a pull-up resistor is assigned to the
corresponding I/O port: PUMOD.3 for port 3,
PUMOD.6 for port 6, and so on.
When a P2MOD bit is set to "1", the corresponding pin
is configured as a digital input pin. When set to "0",
configured as an analog input pin: P2MOD.0 for P2.0,
P2MOD.1 for P2.1, P2MOD.2 for P2.2, and P2MOD.3
for P2.3.
Table 18. Pull-Up Resistor Mode Register (PUMOD) Organization (8-Bit W)
Address
Bit 3
Bit 2
Bit 1
Bit 0
FDCH
PUMOD.3
"0"
PUMOD.1
PUMOD.0
FDDH
"0"
PUMOD.6
"0"
"0"
☞ PROGRAMMING TIP — Enabling and Disabling I/O Port Pull-Up Resistors
P6 enable pull-up resistors, P0, P1, and P3 disable pull-up resistors.
BITS
SMB
LD
LD
EMB
15
EA,#40H
PUMOD,EA
;
P6 enable
S MSUN G
ELECTRONICS
2–23
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
PORT 0 CIRCUIT DIAGRAM
SCK
P0.0
LATCH
SMOD.1
SO
P0.1
P0.2
LATCH
LATCH
SMOD.7
SMOD.6
SMOD.5
V DD
SCK
PUMOD.0
SI
PM0.2
PM0.1
PM0.0
P0.0 / SCK
P0.1 / SO
P0.2 / SI
NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even
though the port's pull-up resistor is enabled by bit settings to the pull-up resistor
mode register (PUMOD).
Figure 21. I/O Port 0 Circuit Diagram
S MSUN G
September 1996
2–24
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
PORT 1 CIRCUIT DIAGRAM
V DD
V DD
INT0
INT1
PUMOD.1
IMOD0
N/R
Circuit
P1.0 / INT0
P1.1 / INT1
N/R = Noise reduction
Figure 22. Input Port 1 Circuit Diagram
PORT 2 CIRCUIT DIAGRAM
P2.0 / CIN0
DIGITAL INPUT
ANALOG INPUT
P2.1 / CIN1
DIGITAL INPUT
ANALOG INPUT
P2.2 / CIN2
DIGITAL INPUT
ANALOG INPUT
DIGITAL INPUT
P2.3 / CIN3
ANALOG INPUT
EXTERNAL REFERENCE
Figure 23. Port 2 Circuit Diagram
S MSUN G
ELECTRONICS
2–25
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
PORT 3 CIRCUIT DIAGRAM
V DD
PUMOD.3
TC0 CLOCK OUTPUT
CLOCK OUTPUT
PM3.2
PM3.1
PM3.0
P3.0 / TCL0
OUTPUT
LATCH
P3.1 / TCLO0
1, 4
P3.2 / CLO
M
U
1, 4
X
TCL0
NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even
though the port's pull-up resistor is enabled by bit settings to the pull-up resistor
mode register (PUMOD).
Figure 24. Port 3 Circuit Diagram
S MSUN G
September 1996
2–26
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
PORTS 4 AND 5 CIRCUIT DIAGRAM
x = 4, 5
b = 0, 1, 2, 3
V DD
P-CH
PMx.b
8
OUTPUT
LATCH
1, 4, 8
MASK OPTION
Px.b
N-CH
M
V SS
U
X
Figure 25. Circuit Diagram for Ports 4 and 5
S MSUN G
ELECTRONICS
2–27
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
PORT 6 CIRCUIT DIAGRAM
V DD
PUMOD.6
PM6.3
PM6.2
PM6.1
PM6.0
P6.0 / KS0
P6.1 / KS1
OUTPUT
LATCH
P6.2 / KS2
1, 4
P6.3 / BUZ
M
U
1, 4
X
NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even
though the port's pull-up resistor is enabled by bit settings to the pull-up resistor
mode register (PUMOD).
Figure 26. Port 6 Circuit Diagram
S MSUN G
September 1996
2–28
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
BASIC TIMER (BT)
incrementing as it counts BT clocks until an overflow
occurs. An overflow causes the BT interrupt request
flag (IRQB) to be set to "1" to signal that the
designated time interval has elapsed. An interrupt
request is then generated, BCNT is cleared to "0", and
counting continues from 00H.
The basic timer generates interrupt requests atprecise
intervals. You can use the basic timer as a "watchdog"
timer for monitoring system events or use BT output
to stabilize clock oscillation when Stop mode is
released by an interrupt and following RESET.
Oscillation Stabilization Interval Control
Interval Timer Function
Setting bits 2–0 of the BMOD register determines the
time interval (also referred to as 'wait time') required to
stabilize clock signal oscillation when power-down
mode is released by an interrupt. When a RESET
signal is generated, the standard stabilization interval
for system clock oscillation following a RESET is
31.3ms at 4.19 MHz.
The measurement of elapsed time intervals is the
basic timer's primary function. The standard interval is
256 BT clock pulses. To restart the basic timer, set
bit 3 of the mode register BMOD to "1". The 8-bit
counter register, BCNT, is incremented each time a
clock signal is detected that corresponds to the
frequency selected by BMOD. BCNT continues
"CLEAR" SIGNAL
BITS
INSTRUCTION
CLEAR
BCNT
CLEAR
IRQB
BMOD.3
BMOD.2
CLOCK
BMOD.1
SELECTOR
INTERRUPT
REQUEST
OVERFLOW
BCNT
4
IRQB
1-BIT R/W
BMOD.0
8
CLOCK INPUT
CPU CLOCK
START SIGNAL
(POWER-DOWN RELEASE)
Figure 27. Basic Timer Circuit Diagram
S MSUN G
ELECTRONICS
2–29
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
BASIC TIMER MODE REGISTER (BMOD)
BMOD.3, is used to restart the basic timer. When
BMOD.3 is set to "1", the contents of the BT counter
register (BCNT) and the BT interrupt request flag
(IRQB) are both cleared to "0", and timer operation is
restarted.
The basic timer mode register, BMOD, is used to
select input frequency and oscillation stabilization
time. The most significant bit of the BMOD register,
Table 19. Basic Timer Mode Register (BMOD) Organization (4-Bit W)
BMOD.3
1
Basic Timer Enable/Disable Control Bit
Start basic timer; clear IRQB, BCNT, and BMOD.3 to "0".
BMOD.2
BMOD.1
BMOD.0
Basic Timer Input Clock
Oscillation Stabilization
0
0
0
fx/212 (1.02 kHz)
2 20/fx (250 ms)
0
1
1
fx/29 (8.18 kHz)
2 17/fx (31.3 ms)
1
0
1
fx/27 (32.7 kHz)
2 15/fx (7.82 ms)
1
1
1
fx/25 (131 kHz)
2 13/fx (1.95 ms)
NOTES:
1. Clock frequencies and stabilization intervals assume a system oscillator clock frequency (fx) of 4.19 MHz.
2. fx = system clock frequency.
3. Oscillation stabilization time is the time required to stabilize clock signal oscillation after Stop mode is released.
4. The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.
5. BMOD.3 is bit addressable.
BASIC TIMER COUNTER (BCNT)
NOTE
Always execute a BCNT read operation
twice to eliminate the possibility of
reading unstable data while the counter
is incrementing. If, after two consecutive
reads, the BCNT values match, you can
select the latter value as valid data. Until
the results of the consecutive reads
match, however, the read operation
must be repeated until the validation
condition is met.
BCNT is an 8-bit counter register for the basic timer.
When BCNT has incremented to hexadecimal 'FFH', it
is cleared to '00H' and an overflow is generated. The
overflow causes the interrupt request flag, IRQB, to
be set to "1". When the interrupt request is generated,
BCNT immediately resumes counting incoming clock
signals.
S MSUN G
September 1996
2–30
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
☞ PROGRAMMING TIP — Using the Basic Timer
1. To read the basic timer count register (BCNT):
BCNTR
BITS
SMB
LD
LD
LD
CPSE
JR
EMB
15
EA,BCNT
YZ,EA
EA,BCNT
EA,YZ
BCNTR
2. When Stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms:
BITS
SMB
LD
LD
STOP
NOP
NOP
NOP
CPU
OPERATION
EMB
15
A,#0BH
BMOD,A
;
;
NORMAL
OPERATING MODE
Wait time is 31.3 ms
Set stop power-down mode
STOP MODE
IDLE MODE
NORMAL
OPERATING MODE
(31.3 ms)
STOP
INSTRUCTION
STOP MODE IS
RELEASED BY
INTERRUPT
3. To set the basic timer interrupt interval time to 1.95 ms (at 4.19 MHz):
BITS
SMB
LD
LD
EI
BITS
EMB
15
A,#0FH
BMOD,A
IEB
;
Basic timer interrupt enable flag is set to "1"
4. Clear BCNT and the IRQB flag and restart the basic timer:
BITS
SMB
BITS
EMB
15
BMOD.3
S MSUN G
ELECTRONICS
2–31
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
8-BIT TIMER/COUNTER 0 (TC0)
Timer/counter 0 can supply a clock signal to the clock
selector circuit of the serial I/O interface for data
shifter and clock counter operations. (These internal
SIO operations are controlled in turn by the SIO mode
register, SMOD). This clock generation function lets
you adjust data transmission rates across the serial
interface.
Timer/counter 0 (TC0) is used to count system
'events' by identifying the transition (high-to-low or
low-to-high) of incoming square wave signals.
To indicate that an event has occurred, or that a
specified time interval has elapsed, TC0 generates an
interrupt request. By counting signal transitions and
comparing the current counter value with the
reference register value, TC0 can be used to measure
specific time intervals.
P3.0
CLOCKS
(fx/210, fx/2 6, fx/2 4, fx)
TCL0
8
8
TMOD0.7
TCNT0
TMOD0.6
8
8-BIT
COMPARATOR
CLOCK
SELECTOR
TMOD0.5
TMOD0.4
TREF0
CLEAR
TMOD0.3
TMOD0.2
CLEAR
TMOD0.1
SET
TMOD0.0
INVERTED
CLEAR
TOL0
IRQT0
SERIAL
I/O
TCLO0
PM3.1
P3.1 LATCH
TOE0
Figure 28. TC0 Circuit Diagram
PROGRAMMABLE TIMER/COUNTER FUNCTION
The content of TCNT0 is then cleared to 00H, and
TC0 continues counting.
Timer/counter 0 can generate interrupt requests at
various intervals, based on the selected system clock
frequency. The reference register, TREF0, stores the
value for the number of clock pulses to be generated
between interrupt requests. The counter register,
TCNT0, counts the incoming clock pulses, which are
compared to the TREF0 value as TCNT0 is
incremented. When TREF0 = TCNT0, the TC0
interrupt request flag (IRQT0) is set to "1", the status
of TOL0 is inverted, and the interrupt is generated.
EVENT COUNTER FUNCTION
Timer/counter 0 can be used to monitor or detect
system 'events' by using the external clock input at
the TCL0 pin (I/O port 3.0) as the counter source. To
activate the TC0 event counter function, P3.0/TCL0
must be set to input mode. With the exception of the
different TMOD0.4–TMOD0.6 settings, the operation
sequence for TC's event counter function is identical
to its programmable timer/counter function.
S MSUN G
September 1996
2–32
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
TC0 CLOCK FREQUENCY OUTPUT
Using timer/counter, you can output a modifiable clock frequency to the TC0 clock output pin, TCLO0. To enable
the output to the TCLO0/P3.1, the pin must be set to output mode when the timer output enable flag (TOE0) has
been enabled.
☞ PROGRAMMING TIP — TC0 Signal Output to the TCLO0 Pin
Output a 30 ms pulse width signal to the TCLO0 pin:
BITS
SMB
LD
LD
LD
LD
LD
LD
BITR
BITS
EMB
15
EA,#79H
TREF0,EA
EA,#4CH
TMOD0,EA
EA,#20H
PMG1,EA
P3.1
TOE0
;
;
P3.1 ← Output mode
P3.1 clear
By selecting an external clock source, you can divide the incoming clock signal by the TREF0 value and then
output this modified clock frequency to the TCLO0 pin.
☞ PROGRAMMING TIP — External TCL0 Clock Output to the TCLO0 Pin
Output external TCL0 clock pulse to the TCLO0 pin (divide by four):
EXTERNAL (TCL0)
CLOCK PULSE
TCLO0
OUTPUT
PULSE
BITS
SMB
LD
LD
LD
LD
LD
LD
BITR
BITS
EMB
15
EA,#01H
TREF0,EA
EA,#0CH
TMOD0,EA
EA,#20H
PMG1,EA
P3.1
TOE0
;
;
P3.1 ← Output mode
P3.1 clear
S MSUN G
ELECTRONICS
2–33
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
TC0 MODE REGISTER (TMOD0)
TMOD0 is the 8-bit mode control register for timer/counter 0. When TMOD0.3 is set to "1", the contents of TCNT0,
IRQT0, and TOL0 are cleared, counting starts from 00H, and TMOD0.3 is automatically reset to "0" for normal
TC0 operation. When TC0 operation stops (TMOD0.2 = "0"), the contents of the TC0 counter register, TCNT0, are
retained until TC0 is re-enabled.
Table 20. TC0 Mode Register (TMOD0) Organization (8-Bit W)
Bit Name
Setting
TMOD0.7
0
Resulting TC0 Function
Address
MSB value always logic zero
TMOD0.6
TMOD0.5
F91H
0,1
Specify input clock edge and internal frequency
TMOD0.4
TMOD0.3
1
Clear TCNT0, IRQT0, and TOL0. Then immediately resume
counting. (This bit is automatically cleared to "0" when counting
resumes.)
TMOD0.2
0
Disable timer/counter; retain TCNT0 contents
1
Enable timer/counter
TMOD0.1
0
Value always "0"
TMOD0.0
0
LSB value always "0"
F90H
Table 21. TMOD0.6, TMO0.5, and TMOD0.4 Bit Settings
TMOD0.6
TMOD0.5
TMOD0.4
Resulting Counter Source and Clock Frequency
0
0
0
External clock input (TCL0) on rising edges
0
0
1
External clock input (TCL0) on falling edges
1
0
0
fx/210 = 4.09 kHz
1
0
1
fx /26 = 65.5 kHz
1
1
0
fx/24 = 262 kHz
1
1
1
fx = 4.19 MHz
NOTE: 'fx' = system clock
S MSUN G
September 1996
2–34
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
☞ PROGRAMMING TIP — Restarting TC0 Counting Operation
1. Set TC0 timer interval to 4.09 kHz:
BITS
SMB
LD
LD
EI
BITS
EMB
15
EA,#4CH
TMOD0,EA
IET0
2. Clear TCNT0, IRQT0, and TOL0. Then, restart the TC0 counting operation:
BITS
SMB
BITS
EMB
15
TMOD0.3
☞ PROGRAMMING TIP — Setting a TC0 Timer
TC0 REFERENCE REGISTER (TREF0)
TREF0 is used to store a reference value to be
compared to the incrementing TCNT0 register in order
to identify an elapsed time interval.
Use the following formula to calculate the correct
value to load to the TREF0 reference register:
To set a 30 ms timer interval for TC0, given fx =
4.19MHz, follow these steps.
1. Select the timer/counter mode register with a
maximum setup time of 62.5 ms (assume that the
TC0 counter clock = fx/2 10, and TREF0 is FFH):
TC0 timer interval =
(TREF0 value + 1) ×
Interval
1
TMOD0frequencysetting
2. Calculate the TREF0 value:
TREF0value+1
4.09kHz
(assuming a TREF0 value ≠ 0)
30 ms =
TC0 OUTPUT ENABLE FLAG (TOE0)
TREF0 + 1 =
The 1-bit timer/counter 0 output enable flag TOE0
controls output from TC0 to the TCLO0 pin.
TREF0 value = 7AH – 1 = 79H
F92H
0
3. Load the value 79H to the TREF0 register:
1-Bit R/W
TOE0
0
30ms
= 122.9 = 7AH
244µs
BITS
SMB
LD
LD
LD
LD
0
When you set the TOE0 flag to "1", the contents of
TOL0 can be output to the TCLO0 pin.
EMB
15
EA,#79H
TREF0,EA
EA,#4CH
TMOD0,EA
S MSUN G
ELECTRONICS
2–35
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
WATCH TIMER
software as soon as a requested interrupt service
routine has been executed.
Watch timer functions include real-time and watchtime measurement and interval timing for the system
clock. It is also used as a clock source for generating
buzzer output.
To start the watch timer, set bit 2 of the watch timer
mode register, WMOD.2, to "1". The watch timer
starts, the interrupt request flag IRQW is automatically
set to "1", and interrupt requests commence in 0.5second intervals. Because the watch timer functions
as a quasi-interrupt instead of a vectored interrupt, the
IRQW flag should be cleared to "0" by program
The watch timer can generate a steady 2 kHz, 4 kHz,
8 kHz, or 16 kHz signal to the BUZ pin. To generate a
BUZ signal, clear the output latch for I/O port 6.3 to
"0" and set the port 6.3 output mode flag (PM6.3) to
output mode.
By setting WMOD.1 to "1", the watch timer functions
in high-speed mode, generating an interrupt every
3.91 ms. High-speed mode is useful for timing events
during program debugging sequences.
P6.3 LATCH
PM6.3
WMOD.7
0
BUZ
WMOD.5
8
MUX
WMOD.4
0
fw/16 (2 KHz)
ENABLE / DISABLE
fw/8
(4 kHz)
fx = SYSTEM CLOCK
fw = WATCH TIMER FREQUENCY
fw/2 (16 kHz)
fw/4
(8 kHz)
WMOD.2
SELECTOR
CIRCUIT
WMOD.1
IRQW
0
FREQUENCY
CLOCK
DIVIDING
SELECTOR 32.768 kHz
CIRCUIT
fw
fw/2 7
fw/214 (2 Hz)
GND fx/128
Figure 29. Watch Timer Circuit Diagram
S MSUN G
September 1996
2–36
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
WATCH TIMER MODE REGISTER (WMOD)
The watch timer mode register WMOD is used to select specific watch timer operations.
Table 22. Watch Timer Mode Register (WMOD) Organization (8-Bit W)
Bit Name
Values
WMOD.7
WMOD.6
0
Disable buzzer (BUZ) signal output
1
Enable buzzer (BUZ) signal output
"0"
WMOD.5 – .4
Function
Always "0"
0
0
2 kHz buzzer (BUZ) signal output
0
1
4 kHz buzzer (BUZ) signal output
1
0
8 kHz buzzer (BUZ) signal output
1
1
16 kHz buzzer (BUZ) signal output
WMOD.3
"0"
WMOD.2
0
Disable watch timer; clear frequency dividing circuits
1
Enable watch timer
0
Normal mode; sets IRQW to 0.5 s
1
High-speed mode; sets IRQW to 3.91 ms
0
Always "0"
WMOD.1
WMOD.0
Address
F89H
Always "0"
F88H
NOTE: System clock frequency (fx) is assumed to be 4.19 MHz.
☞ PROGRAMMING TIP — Using the Watch Timer
1. Select a 0.5 second interrupt, and 2 kHz buzzer enable:
BITS
SMB
LD
LD
BITR
LD
LD
BITS
EMB
15
EA,#80H
PMG3,EA
P6.3
EA,#84H
WMOD,EA
IEW
;
;
P6.3 ← Output mode
Clear P6.3 output latch
;
;
;
0.5 second check
No, return
Yes, 0.5 second interrupt generation
;
Increment HOUR, MINUTE, SECOND
2. Sample real-time clock processing method:
CLOCK
BTSTZ
RET
•
•
•
IRQW
S MSUN G
ELECTRONICS
2–37
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
COMPARATOR
an external reference voltage is input at P2.3, the
other three pins (P2.0–P2.2) in port 2 are used for
analog input. Unused port 2 pins must be connected
to VDD.
Port 2 can be used as a analog input port for the 4channel comparator block. The reference voltage for
the comparator can be supplied either internally or
externally at P2.3.
When a conversion is completed, the result is saved
in the comparison result register CMPREG. The initial
values of the CMPREG are undefined and the
comparator operation is disabled by a RESET.
When internal reference voltage is used, four
channels (P2.0–P2.3) are used for analog inputs and
the internal reference voltage is varies at 16 levels. If
P2.0 / CIN0
M
P2.1 / CIN1
+
U
P2.2 / CIN2
–
X
COMPARISON
RESULT
REGISTER
(CMPREG)
4
P2.3 / CIN3
VREF
(EXTERNAL)
M
INTERNAL BUS
U
X
VDD
CMOD.7
CMOD.6
1/2R
CMOD.5
R
M
R
U
VREF
(INTERNAL)
0
8
CMOD.3
CMOD.2
X
CMOD.1
1/2R
CMOD.0
Figure 30 Comparator Circuit Diagram
S MSUN G
September 1996
2–38
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
COMPARATOR MODE REGISTER (CMOD)
When CMOD.5 is set to "1":
The comparator mode register (CMOD) is used to set
the operation mode of the comparator. Based on the
CMOD.5 bit setting, an internal or an external
reference voltage is input for the comparator, as
follows:
— External reference voltage is supplied from
P2.3/CIN3.
— P2.0 to P2.2 are used as the analog input pins.
When CMOD.5 is "0":
— The comparator can detect a 150 mV difference
between the reference voltage and analog input
voltages.
— A reference voltage is selected by the CMOD.0 to
CMOD.3 bit settings.
— Bits 0–2 in the CMPREG register contain the
results (the content of bit 3 is not used).
— P2.0 to P2.3 are used as analog input pins.
Bit 6 in the CMOD register controls conversion time
while bit 7 enables or disables comparator operation
to reduce power consumption.
— The internal digital-to-analog converter generates
16 reference voltages.
— The comparator can detect a 150 mV difference
between the reference voltage and analog input
voltages.
— Comparator results are written into 4-bit
comparison result register (CMPREG).
CMOD.7 CMOD.6 CMOD.5
0
CMOD.3 CMOD.2
CMOD.1 CMOD.0
FD6H–FD7H
Reference voltage (VREF) selection:
VDD x (n + 0.5)/16, n = 0 to 15
1: CIN3; external reference, CIN0–2; analog input
0: Internal reference, CIN0–3; analog input
1: Conversion time (4 x 24 /fx, 15.2 µs @4.19MHz)
0: Conversion time (4 x 27 /fx, 121.6 µs @4.19MHz)
1: Comparator operation enable
0: Comparator operation disable
Figure 31. Comparator Mode Register Organization
PORT 2 MODE REGISTER (P2MOD)
When a P2MOD bit is set to "1", the corresponding pin
is configured as a digital input pin. When it is "0", the
corresponding pin is configured as an analog input:
P2MOD.0 for P2.0, P2MOD.1 for P2.1, P2MOD.2 for
P2.2, and P2MOD.3 for P2.3.
P2MOD register settings determine if port 2 is used
for analog or digital input.
FE2H
P2MOD.3
4-Bit W
P2MOD.2
P2MOD.1
P2MOD.0
S MSUN G
ELECTRONICS
2–39
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
COMPARATOR OPERATION
The comparison result is calculated as follows:
The comparator compares analog voltage input at
CIN0–CIN3 with an external or internal reference
voltage (VREF) that is selected by CMOD register.
The result is written to the comparison result register
CMPREG at address FD4H.
If "1"
Analog input voltage ≥ VREF + 150 mV
If "0"
Analog input voltage ≤ VREF – 150 mV
To obtain a comparison result, the data must be read
out from the CMPREG register after VREF is updated
by changing the CMOD value after a conversion time
has elapsed.
ANALOG INPUT
VOLTAGE (CIN0–3)
REFERENCE
VOLTAGE (VREF)
COMPARISON TIME
(CMPCLK x 4)
COMPARATOR CLOCK
(CMPCLK, fx/16, fx/128)
COMPARISON
START
COMPARISON
END
COMPARISON
RESULT (CMPREG)
UNKNOWN
1
0
1
Figure 32. Conversion Characteristics
☞ PROGRAMMING TIP — Programming the Comparator
The following program example converts the analog voltage input at CIN0–CIN2 pins into 4-bit digital code.
WAIT LD
BITR
LD
LD
LD
EMB
A,#0H
P2MOD,A
EA,#8XH
LD
A,#0H
INCS
JR
LD
LD
CMOD,EA
A
WAIT
A,CMPREG
P4,A
;
;
;
Analog input selection (CIN0–CIN3)
x = 0–F, comparator enable
Internal reference, conversion time (121.6 µs)
;
;
Read the result
Output the result from port 4
S MSUN G
September 1996
2–40
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
SERIAL I/O INTERFACE
Using the serial I/O interface, you can exchange 8-bit data with an external device. The serial interface can run off
an internal or an external clock source, or the TOL0 signal that is generated by the 8-bit timer/counter 0, TC0. If
you use the TOL0 clock signal, you can modify its frequency to adjust the serial data transmission rate.
INTERNAL BUS
8
LSB or MSB first
SO
SBUF (8-BIT)
SI
CLK
R
Q
SCK
IRQS
TOL0
CLOCK
SELECTOR
fx/210
D
CLK
R
Q
CLK
S
fx/2
SMOD.7
SMOD.6 SMOD.5
Q0 Q1 Q2
3-BIT COUNTER
CLEAR
SMOD.3 SMOD.2
–
SMOD.1 SMOD.0
8
Figure 33. Serial I/O Interface Circuit Diagram
S MSUN G
ELECTRONICS
2–41
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
SERIAL I/O MODE REGISTER (SMOD)
SERIAL I/O BUFFER REGISTER (SBUF)
The serial I/O mode register (SMOD) specifies the
operation mode of the serial interface. SMOD register
settings enable you to select either MSB-first or LSBfirst serial transmission, and to operate in transmitand-receive mode or receive-only mode. When
SMOD.3 is set to "1", the contents of the serial
interface interrupt request flag, IRQS, and the 3-bit
serial clock counter are cleared, and SIO operations
are initiated. When the SIO transmission starts,
SMOD.3 is cleared to "0".
When the serial interface operates in transmit-andreceive mode (SMOD.1 = "1"), transmit data in the
SIO buffer register are output to the SO pin at the rate
of one bit for each falling edge of the SIO clock.
Receive data is simultaneously input from the SI pin
to SBUF at the rate of one bit for each rising edge of
the SIO clock.
When receive-only mode is used, incoming data is
input to the SIO buffer at the rate of one bit for each
rising edge of the SIO clock. SBUF can be read or
written using 8-bit RAM control instructions.
Table 23. SIO Mode Register (SMOD) Organization (8-Bit W)
SMOD.0
0
Most significant bit (MSB) is transmitted first
1
Least significant bit (LSB) is transmitted first
0
Receive-only mode; output buffer is off
1
Transmit-and-receive mode
0
Disable the data shifter and clock counter; retain contents of IRQS flag when serial
transmission is halted
1
Enable the data shifter and clock counter; set IRQS flag to "1" when serial
transmission is halted
SMOD.3
1
Clear IRQS flag and 3-bit clock counter to "0"; initiate transmission and then reset
this bit to "0"; this bit is also bit-addressable.
SMOD.4
0
Bit not used; value is always "0"
SMOD.7
SMOD.6
SMOD.5
0
0
0
External clock at SCK pin
0
0
1
Use TOL0 clock from TC0
0
1
x
CPU clock: fx/4, fx/8, fx/64
Enable SBUF read/write
1
0
0
4.09 kHz clock: fx/210
SBUF is enabled when SIO
operation is halted or when SCK
goes high.
1
1
1
262 kHz clock: fx/2 4
SMOD.1
SMOD.2
Clock Selection
R/W Status of SBUF
SBUF is enabled when SIO
operation is halted or when SCK
goes high.
NOTES:
1. 'fx' = system clock; 'x' means 'don't care.'
2. kHz frequency ratings assume a system clock (fx) running at 4.19 MHz.
3. The SIO clock selector circuit cannot select a fx/2 4 clock if the CPU clock is fx/64.
S MSUN G
September 1996
2–42
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
SCK
SI
DI7
SO
DO7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO6
DO5
DO4
DO3
DO2
DO1
DO0
IRQS
TRANSMIT
COMPLETE
SET SMOD.3
Figure 34. SIO Timing in Transmit/Receive Mode
SCK
DI7
SI
DI6
DI5
DI4
DI3
DI2
DI1
DI0
HIGH IMPEDANCE
SO
IRQS
TRANSMIT
COMPLETE
SET SMOD.3
Figure 35. SIO Timing in Receive-Only Mode
S MSUN G
ELECTRONICS
2–43
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
☞ PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O
1. Transmit the data value 48H through the serial I/O interface using an internal clock frequency of fx/24 and in
MSB-first mode:
BITS
SMB
LD
LD
LD
LD
LD
LD
EMB
15
EA,#03H
PMG1,EA
EA,#48H
SBUF,EA
EA,#0EEH
SMOD,EA
; P0.0 / SCK and P0.1 / SO ← Output
;
;
; SIO data transfer
☞ PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)
SCK / P0.0
EXTERNAL
DEVICE
SO / P0.1
KS57C0002
2. Use CPU clock to transfer and receive serial data at high speed:
STEST
BITR
LD
LD
LD
LD
LD
LD
BITR
BTSTZ
JR
LD
LD
EMB
EA,#03H
PMG1,EA
EA,TDATA
SBUF,EA
EA,#4FH
SMOD,EA
IES
IRQS
STEST
EA,SBUF
RDATA,EA
; P0.0 / SCK and P0.1 / SO ← Output, P0.2 / SI ← Input
; TDATA address = Bank0(20H–7FH)
; SIO start
; SIO Interrupt Enable
; RDATA address = Bank0 (20H–7FH)
S MSUN G
September 1996
2–44
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
☞ PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)
3. Transmit and receive an internal clock frequency of 4.09 kHz (at 4.19 MHz) in LSB-first mode:
INTS
BITR
LD
LD
LD
LD
LD
LD
EI
BITS
•
•
•
PUSH
PUSH
BITR
LD
EMB
EA,#03H
PMG1,EA
EA,TDATA
SBUF,EA
EA,#8FH
SMOD,EA
XCH
LD
BITS
POP
POP
IRET
EA,SBUF
RDATA,EA
SMOD.3
EA
SB
; P0.0 / SCK and P0.1 / SO ← Output, P0.2 / SI ← Input
; TDATA address = Bank0 (20H–7FH)
; SIO start
IES
; SIO Interrupt Enable
SB
EA
EMB
EA,TDATA
; Store SMB, SRB
; Store EA
;
;
;
;
;
EA ← Transmit data
TDATA address = Bank0 (20H–7FH)
Transmit data ↔ Receive data
RDATA address = Bank0 (20H–7FH)
SIO start
SCK / P0.0
EXTERNAL
DEVICE
SO / P0.1
SI / P0.2
KS57C0002
S MSUN G
ELECTRONICS
2–45
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
☞ PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)
4. Transmit and receive an external clock in LSB-first mode:
INTS
BITR
LD
LD
LD
LD
LD
LD
EI
BITS
•
•
•
PUSH
PUSH
BITR
LD
EMB
EA,#02H
PMG1,EA
EA,TDATA
SBUF,EA
EA,#0FH
SMOD,EA
XCH
LD
BITS
POP
POP
IRET
EA,SBUF
RDATA,EA
SMOD.3
EA
SB
; P0.1 / SO ← Output, P0.0 / SCK and P0.2/SI← Input
; TDATA address = Bank0 (20H–7FH)
; SIO start
IES
; SIO Interrupt Enable
SB
EA
EMB
EA,TDATA
; Store SMB, SRB
; Store EA
;
;
;
;
;
EA ← Transmit data
TDATA address = Bank0 (20H–7FH)
Transmit data ↔ Receive data
RDATA address = Bank0 (20H–7FH)
SIO start
SCK / P0.0
EXTERNAL
DEVICE
SO / P0.1
SI / P0.2
KS57C0002
S MSUN G
September 1996
2–46
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
ELECTRICAL DATA
Table 24. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Symbol
Conditions
Rating
Units
Supply Voltage
V DD
—
– 0.3 to + 7.0
V
Input Voltage
V I1
– 0.3 to VDD + 0.3
– 0.3 to + 9
V
Ports 4, 5
CMOS push-pull
Open-drain
V I2
Output Voltage
Output Current High
Output Current Low
All I/O ports except 4 and 5
VO
—
IOH
IOL
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
V
One I/O port active
–5
mA
All I/O ports active
– 15
Ports 0, 3, and 6
5
mA
Ports 4 and 5
30
All ports, total
+ 100
Operating Temperature
TA
—
– 40 to + 85
°C
Storage Temperature
Tstg
—
– 65 to + 150
°C
Table 25. D.C. Electrical Characteristics
(TA = – 40 ° C to + 85 °C, VDD = 2.7 V to 6.0 V)
Parameter
Symbol
Input High
Voltage
Input Low
Voltage
Output High
Voltage
*
Conditions
Min
Typ
Max
Units
V
V IH1
Ports 4 and 5
0.7V DD
—
V DD
V IH2
Ports 0, 1, 2, 3, 6, and RESET
0.8V DD
—
V DD
V IH3
X in and Xout
V DD – 0.5
—
V DD
V IL1
Ports 4 and 5
—
—
0.3V DD
V IL2
Ports 0, 1, 2, 3, 6,
V IL3
X in and Xout
V OH
V DD = 4.5 V to 6.0 V
IOH = – 1 mA
Ports 0, 3, 4, 5, 6
V DD – 1.0
V DD = 4.5 V to 6.0 V
IOH = – 3.0 mA
Ports 0, 3, 4, 5, 6
V DD – 2.0
and RESET
V
0.2V DD
*
—
—
V
The value is 0.2V at KS57C0002 or 0.4V at KS57C0004.
S MSUN G
ELECTRONICS
2–47
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
Table 25. D.C. Electrical Characteristics (Continued)
(TA = – 40 ° C to + 85 °C, VDD = 2.7 V to 6.0 V)
Parameter
Output Low
Voltage
Symbol
V OL
Conditions
V DD = 4.5 V to 6.0 V
IOL = 15 mA
Ports 4 and 5 only
Min
Typ
Max
Units
—
0.4
2
V
—
0.4
V DD = 4.5 V to 6.0 V
IOL = 1.6 mA
Ports 0, 3, 6 only
V DD = 4.5 V to 6.0 V
IOL = 4.0 mA
Ports 0, 3, 6 only
Input High
Leakage
Current
Input Low
Leakage
Current
2
ILIH1
V IN = VDD
All input pins except Xin and Xout
—
ILIH2
V IN = VDD
X in and Xout
20
ILIH3
V IN = 9 V
Ports 4 and 5 are open-drain
10
ILIL1
V IN = 0 V
All input pins except Xin, Xout and
—
—
—
µA
3
µA
–3
RESET
ILIL2
V IN = 0 V
X in and Xout
ILOH1
V O = VDD
All output pins except for port 4
and port 5
ILOH2
VO = 9 V
Ports 4 and 5 are open-drain
Output Low
Leakage
Current
ILOL
VO = 0 V
—
—
–3
µA
Pull-Up
Resistor
RL1
V IN = 0 V; VDD = 5 V ± 10%
Port 0, 1, 3, 6
15
40
80
KΩ
V IN = 0 V; VDD = 3 V ± 10%
Port 0, 1, 3, 6
30
V IN = 0 V; VDD = 5 V ± 10%
100
230
400
V IN = 0 V; VDD = 3 V ± 10%
200
490
800
Output High
Leakage
Current
RL2
– 20
RESET
RESET
—
—
µA
3
10
200
KΩ
S MSUN G
September 1996
2–48
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Table 25. D.C. Electrical Characteristics (Concluded)
(TA = – 40 ° C to + 85 °C, VDD = 2.7 V to 6.0 V)
Parameter
Symbol
Supply
Current (1)
Conditions
Min
Typ
Max
Units
—
2.5
8
mA
0.62
1.2
1.2
1.8
Idle mode; VDD = 3 V ± 10%
4.19 MHz crystal oscillator
C1 = C2 = 22 pF
0.58
1.0
Stop mode
V DD = 5 V ± 10%
0.5
5
Stop mode
V DD = 3 V ± 10%
0.3
3
V DD = 5 V ± 10% (2)
4.19 MHz crystal oscillator
C1 = C2 = 22 pF
IDD1
V DD = 3 V ± 10% (3)
4.19 MHz crystal oscillator
C1 = C2 = 22 pF
Idle mode; VDD = 5 V ± 10%
4.19 MHz crystal oscillator
C1 = C2 = 22 pF
IDD2
IDD3
—
mA
µA
NOTES:
1. The currents in the following circuits are not included; on-chip pull-up resistors, output port drive currents and comparator.
2. For high-speed controller operation, set the PCON register to 0011B.
3. For low-speed controller operation, set the PCON register to 0000B.
CPU CLOCK
1.0475 MHz
1.00 MHz
750 kHz
500 kHz
250 kHz
15.6 kHz
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 36. Standard Operating Voltage Range
S MSUN G
ELECTRONICS
2–49
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
Table 26. Oscillator Characteristics
(TA = – 40 °C to + 85 °C, VDD = 5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
Xin
Xout
C1
Parameter
Test Condition
Min
Typ
Max
Units
Oscillation frequency (1)
—
0.4
—
4.5
MHz
After V DD reaches
the minimum level of
its variable range
—
—
4
ms
—
0.4
4.19
4.5
MHz
V DD = 2.7 V to 4.5 V
—
—
30
ms
V DD = 4.5 V to 6.0 V
—
—
10
ms
Xin input frequency (1)
—
0.4
—
4.5
MHz
Xin input high and low
level width (t XH , tXL)
—
100
—
150
ns
0.4
—
2
MHz
C2
Stabilization time (2)
Crystal
Oscillator
Xin
Oscillation frequency (1)
Xout
C1
C2
Stabilization time (2)
External
Clock
RC
Oscillator
(3)
Xin
Xout
Xin
Xout
Oscillation frequency
limitation
V DD = 5 V
R
NOTES:
1. Oscillation frequency and X in input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillator stabilization after a reset or termination of Stop mode.
3. RC is only for the KS57C0002.
S MSUN G
September 1996
2–50
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Table 27. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
—
—
15
pF
Output
Capacitance
COUT
—
—
15
pF
CIO
—
—
15
pF
I/O Capacitance
Table 28. Comparator Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 4.0 V to 6.0 V, VSS = 0 V)
Parameter
Symbol
Condition
Min
Typ
Max
Units
—
—
0
—
V DD
V
Reference Voltage
Range
V REF
—
0
—
V DD
V
Input Voltage Accuracy
V CIN
—
—
—
±150
mV
Input Leakage Current
ICIN, IREF
—
–3
—
3
µA
Min
Typ
Max
Units
V DD = 4.5 V to 6.0 V
0.95
—
64
µs
V DD = 2.7 V to 4.5 V
3.8
V DD = 4.5 V to 6.0 V
0
—
1
MHz
275
kHz
—
—
µs
—
—
ns
Input Voltage Range
Table 29. A.C. Electrical Characteristics
(TA = – 40 ° C to + 85 °C, VDD = 2.7 V to 6.0 V)
Parameter
Symbol
Instruction Cycle
Time
TCL0 Input
Frequency
tCY
fTI
Conditions
V DD = 2.7 V to 4.5 V
TCL0 Input High,
Low Width
SCK Cycle Time
tTIH, tTIL
tKCY
V DD = 4.5 V to 6.0 V
0.48
V DD = 2.7 V to 4.5 V
1.8
V DD = 4.5 V to 6.0 V; Input
800
V DD = 4.5 V to 6.0 V; Output
1600
V DD = 2.7 V to 4.5 V; Input
3200
V DD = 2.7 V to 4.5 V; Output
3800
S MSUN G
ELECTRONICS
2–51
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
Table 29. A.C. Electrical Characteristics (Continued)
(TA = – 40 ° C to + 85 °C, VDD = 2.7 V to 6.0 V)
Parameter
SCK High, Low
Width
Symbol
tKH , tKL
Conditions
V DD = 4.5 V to 6.0 V; Input
V DD = 4.5 V to 6.0 V; Output
V DD = 2.7 V to 4.5 V; Input
V DD = 2.7 V to 4.5 V; Output
SI Setup Time to
SCK High
SI Hold Time to
SCK High
Output Delay for
SCK to SO
Interrupt Input
High, Low Width
RESET Input
Low
Width
*
tSIK
tKSI
tKSO
Typ
Max
Units
400
—
—
ns
—
—
ns
—
—
ns
—
300
ns
tKCY /2 –
50
1600
tKCY /2 –
150
Input
100
Output
150
Input
400
Output
400
V DD = 4.5 V to 6.0 V; Input
—
V DD = 4.5 V to 6.0 V; Output
250
V DD = 2.7 V to 4.5 V; Input
1000
V DD = 2.7 V to 4.5 V; Output
1000
*
tINTH, tINTL INT0
tRSL
Min
INT0, INT1, KS0–KS2
10
Input
10
—
—
µs
—
—
µs
The minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
0.8 VDD
0.2 VDD
0.8 VDD
MEASUREMENT
POINTS
0.2 VDD
Figure 37. A.C. Timing Measurement Points (Except for Xin)
S MSUN G
September 1996
2–52
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Table 30. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Condition
Min
Typ
Max
Units
Data Retention
Supply Voltage
V DDDR
—
2.0
—
6.0
V
Data Retention
Supply Current
IDDDR
—
—
0.1
10
µA
Release Signal Set
Time
tSREL
—
0
—
—
ms
Oscillation
Stabilization Time (1)
tWAIT
When released by RESET
—
2 17/fx
—
ms
When released by interrupt
—
(2)
—
ms
NOTES:
1. During oscillation stabilization time, CPU operation must be stopped to avoid instability during oscillator startup.
2. The basic timer causes a delay of 2 17/fx after a reset.
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
tSREL
Figure 38. Stop Mode Release Timing When Initiated By RESET
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
tSREL
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 39. Stop Mode Release Timing When Initiated By Interrupt Request
S MSUN G
ELECTRONICS
2–53
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
1 / fx
tXL
tXH
Xin
VDD – 0.5 V
0.4 V
Figure 40 Clock Timing Measurement at Xin
1 / fTI
tTIL
tTIH
0.8 VDD
0.2 VDD
TCL0
Figure 41. TCL0 Timing
tRSL
RESET
0.2 V DD
Figure 42. Input Timing for
tINTL
RESET Signal
tINTH
INT0, 1
KS0 to KS2
0.8 VDD
0.2 V DD
Figure 43. Input Timing for External Interrupts
S MSUN G
September 1996
2–54
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
tCKY
tKL
tKH
SCK
0.8 V DD
0.2 VDD
tSIK
tKSI
0.8 VDD
SI
INPUT DATA
0.2 VDD
tKSO
SO
OUTPUT DATA
Figure 44. Serial Data Transfer Timing
S MSUN G
ELECTRONICS
2–55
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
CHARACTERISTIC CURVES
NOTE
The characteristic values shown in the following graphs are based on actual test measurements.
They do not, however, represent guaranteed operating values.
IDD1 vs. FREQUENCY (CPU CLOCK = fx/4, fx = 1, 2, 4.2 MHz)
OPERATING CURRENT IDD1 (mA)
4
3.5
VDD = 5.5 V
3
2.5
2
1.5
1
VDD = 3.3 V
0.5
0
0.0
1.0
2.0
3.0
4.0
5.0
FREQUENCY (MHz)
Figure 45. Frequency VS. IDD1
IDD2 vs. FREQUENCY (CPU CLOCK = fx/4, fx/64, fx = 4.2 MHz)
IDLE CURRENT IDD2 (mA)
1.5
VDD = 5.5 V
1
0.5
VDD = 3.3 V
0
0.0
1.0
2.0
3.0
4.0
5.0
FREQUENCY (MHz)
Figure 46. Frequency VS. IDD2
S MSUN G
September 1996
2–56
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
OPERATING CURRENT IDD1 (mA)
IDD1 vs. VDD (CPU CLOCK = fx/4, fx/64, fx = 4.2 MHz)
4
3.5
fx/4
3
2.5
2
fx/64
1.5
1
0.5
0
3.0
4.0
5.0
6.0
7.0
POWER SUPPLY VOLTAGE VDD (V)
Figure 47. VDD VS. IDD1
S MSUN G
ELECTRONICS
2–57
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
NOTES
S MSUN G
September 1996
2–58
ELECTRONICS
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
NOTES
S MSUN G
ELECTRONICS
2–59
September 1996